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* ARC: clk: introduce HSDK pll driverEugeniy Paltsev2017-08-305-0/+473
| | | | | | | | | | | | | | | | | | | | | | | HSDK board manages its clocks using various PLLs. These PLL have same dividers and corresponding control registers mapped to different addresses. So we add one common driver for such PLLs. Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and ODIV. Output clock value is managed using these dividers. We add pre-defined tables with supported rate values and appropriate configurations of IDIV, FBDIV and ODIV for each value. As of today we add support for PLLs that generate clock for the HSDK arc cpus, system, ddr, AXI tunnel and hdmi. By this patch we add support for several plls (arc cpus pll and others), so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll and regular probing for others plls. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: zte: constify clk_div_tableArvind Yadav2017-08-301-3/+3
| | | | | | | | | | clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: imx: constify clk_div_tableArvind Yadav2017-08-305-12/+12
| | | | | | | | | | clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: uniphier: add ethernet clock control supportKunihiko Hayashi2017-08-301-0/+10
| | | | | | | | Add clock control for ethernet controller on Pro4, PXs2, LD11 and LD20. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: gemini: hands off PCI OE bitLinus Walleij2017-08-301-7/+0
| | | | | | | | This bit is pin control, and needs to be carefully managed by the new pin control driver. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: ux500: prcc: constify clk_ops.Arvind Yadav2017-08-301-3/+3
| | | | | | | | | | | | | | clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_prcc" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_prcc non-const clk_ops argument as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: ux500: sysctrl: constify clk_ops.Arvind Yadav2017-08-301-4/+4
| | | | | | | | | | | | | | clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_sysctrl" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_sysctrl non-const clk_ops argument as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: ux500: prcmu: constify clk_ops.Arvind Yadav2017-08-301-7/+7
| | | | | | | | | | | | | | clk_ops are not supposed to change at runtime. All functions working with clk_ops provided by <linux/clk-provider.h> work with const clk_ops. So mark the non-const clk_ops as const. Here, Function "clk_reg_prcmu" is used to initialized clk_init_data. clk_init_data is working with const clk_ops. So make clk_reg_prcmu non-const clk_ops argument as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: msm8996-gcc: add missing smmu clksSrinivas Kandagatla2017-08-232-0/+30
| | | | | | | This patch adds missing LPASS smmu clks which are required by the audio driver. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Fix Tegra210 PLLU initializationAlex Frid2017-08-231-2/+4
| | | | | | | | | | | | - Added necessary delays in PLLU enable sequence during initialization - Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were missing). Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Correct Tegra210 UTMIPLL poweron delayAlex Frid2017-08-231-3/+3
| | | | | | | | | | | | | Increased Tegra210 UTMIPLL power on delay to 20us (spec maximum is 15us). Also remove a few empty lines to make it more clear the ACTIVE_DLY_COUNT and ENABLE_DLY_COUNT fields. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Fix T210 PLLRE registrationAlex Frid2017-08-231-20/+1
| | | | | | | | | | | | | | | | | Switched Tegra210 PLLRE registration to common PLL ops instead of special PLLRE ops used on previous Tegra chips. The latter ops do not follow chip specific PLL frequency table, and do not apply chip specific rate calculation method. Removed unnecessary default rate setting that duplicates h/w reset state, and is overwritten by clock initialization, anyway. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Update T210 PLLSS (D2/DP) registrationAlex Frid2017-08-231-39/+9
| | | | | | | | | | | | | | | | | | | | | Remove from Tegra210 PLLSS registration code sections that - attempt to set PLL minimum rate (unnecessary, and dangerous if PLL is already enabled on boot) - apply pre-Tegra210 defaults settings - check IDDQ setting (duplicated with Tegra210 PLLSS check defaults) Replaced setting of reference clock with check that default oscillator selection is not changed, and failed registration otherwise as validation was only done with the oscillator as the reference clock. Reordered registration, so that PLL initialization is called after VCOmin adjustment. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Re-factor T210 PLLX registrationAlex Frid2017-08-234-49/+10
| | | | | | | | | | | | | | | Tegra210 PLLX uses the same sequences than then PLLC instances. So there is no need to have a special registration function and ops struct for it. Simplify the code by changing all references to the Tegra210 PLLX registration function to the Tegra210 PLLC registration function and avoid duplicate functionality. Based on work by Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: don't warn for pll_d2 defaults unnecessarilyPeter De Schrijver2017-08-231-2/+4
| | | | | | | | | | | If the PLL is on, only warn if the defaults are not yet set. Otherwise be silent. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: change post IDDQ release delay to 5usPeter De Schrijver2017-08-231-1/+1
| | | | | | | | | | | Increase delay after PLL IDDQ release to 5us per PLL specifications. based on work by Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2CAlex Frid2017-08-231-1/+2
| | | | | | | | | | | I2C controllers are also on the APB bus and therefor need this flag to handle resets correctly. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Fix T210 effective NDIV calculationAlex Frid2017-08-231-4/+5
| | | | | | | | | | | Don't take the fractional part into account to calculate the effective NDIV if fractional ndiv is not enabled. Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Init cfg structure in _get_pll_mnpPeter De Schrijver2017-08-231-0/+2
| | | | | | | | | | | | | Not all fields are read from the hw depending on the PLL type. Make sure the other fields are 0 by clearing the structure beforehand to prevent users such as the rate re-calculation code from using bogus values. Based on work by Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra210: remove non-existing VFIR clockPeter De Schrijver2017-08-231-1/+0
| | | | | | | Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: disable SSC for PLL_D2Peter De Schrijver2017-08-231-1/+1
| | | | | | | | | PLLD2 is used for HDMI which does not allow Spread Spectrum clocking. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: Enable PLL_SS for Tegra210Peter De Schrijver2017-08-231-1/+1
| | | | | | | | | | | | Make sure the pll_ss ops are compiled even when only building for Tegra210. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com> Tested-by: Shreshtha Sahu <ssahu@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: tegra: fix SS control on PLL enable/disablePeter De Schrijver2017-08-231-20/+24
| | | | | | | | | | | PLL SS was only controlled when setting the PLL rate, not when the PLL itself is enabled or disabled. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: qcom: msm8916: Fix bimc gpu clock opsGeorgi Djakov2017-08-231-1/+1
| | | | | | | | | | | | | | The clock bimc_gpu_clk_src is incorrectly set to use the shared rcg2 ops, which are for RCGs with child branches controlled by different CPUs. The result of the incorrect ops is that the GPU's PM runtime may leave this clock set at a very low rate. Fix this issue by using the correct rcg2 ops. Fixes: a2e8272f3f89 ("clk: qcom: Add MSM8916 gpu clocks") Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: ti: make clk_ops constBhumika Goyal2017-08-233-4/+4
| | | | | | | | | Make these const as they are only stored in the const field of a clk_init_data structure. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'clk-renesas-for-v4.14-tag1' of ↵Stephen Boyd2017-08-2315-85/+674
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: * Add more module clocks for R-Car V2H and M3-W, * Add support for the R-Car Gen3 USB 2.0 clock selector PHY, * Add support for the new R-Car D3 SoC, * Allow compile-testing of all (sub)drivers now all dummy infrastructure is available, * Small fixes and cleanups. * tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add USB3.0 clock clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY clk: renesas: cpg-mssr: Add R8A77995 support clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3 clk: renesas: Add r8a77995 CPG Core Clock Definitions clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table clk: renesas: rcar-gen3-cpg: Drop superfluous variable clk: renesas: Allow compile-testing of all (sub)drivers clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks clk: renesas: div6: Document fields used for parent selection
| * clk: renesas: r8a7796: Add USB3.0 clockHiromitsu Yamasaki2017-08-171-0/+1
| | | | | | | | | | | | | | | | | | This patch adds USB3.0-IF0 clock for R8A7796 SoC. Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHYYoshihiro Shimoda2017-08-174-0/+249
| | | | | | | | | | | | | | | | | | | | R-Car USB 2.0 controller can change the clock source from an oscillator to an external clock via a register. So, this patch adds support the clock source selector as a clock driver. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: cpg-mssr: Add R8A77995 supportGeert Uytterhoeven2017-08-166-1/+251
| | | | | | | | | | | | | | | | | | | | | | | | | | Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 CPG code. Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev. 0.55, Jun. 30, 2017. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org>
| * clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocksGeert Uytterhoeven2017-08-162-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | On R-Car Gen3 SoCs with a Spread Spectrum Clock Generator (e.g. R-Car D3), a peripheral clock divider has been added, to select between clean and spread spectrum parents. Add a new clock type to the R-Car Gen3 driver core to handle this. To avoid increasing the size of struct cpg_core_clk, both parents and dividers are stored in the existing parent resp. div fields. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3Geert Uytterhoeven2017-08-164-37/+41
| | | | | | | | | | | | | | | | | | | | | | On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider value different from one. Extend struct rcar_gen3_cpg_pll_config to handle this. As all multipliers and dividers are small, table size increase can be kept limited by storing them in u8s instead of unsigned ints, which saves ca. 0.5 KiB for a generic kernel. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: renesas: Add r8a77995 CPG Core Clock DefinitionsGeert Uytterhoeven2017-08-161-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | Add all R-Car D3 Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2f ("List of Clocks [R-Car D3]") of the R-Car Series, 3rd Generation Hardware User's Manual (Rev. 0.55, Jun. 30, 2017). Note that internal CPG clocks (S0, S1, S2, S3, S1C, S3C, SDSRC, and SSPSRC) are not included, as they are used as internal clock sources only, and never referenced from DT. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div tableWolfram Sang2017-07-191-26/+20
| | | | | | | | | | | | | | | | | | Do the checks for accessing the SD divider table only when the rate gets updated, namely on init and set_rate. In all other cases, reuse the last value. This simplifies code, runtime load, and error reporting. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: rcar-gen3-cpg: Drop superfluous variableWolfram Sang2017-07-191-2/+1
| | | | | | | | | | | | | | 'rate' is not used, so we can use 'parent_rate' directly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: Allow compile-testing of all (sub)driversGeert Uytterhoeven2017-07-171-19/+19
| | | | | | | | | | | | | | | | | | | | Enable compile-testing of the remaining clock drivers and subdrivers, now dummies are available for of_clk_get_from_provider(), of_device_compatible_match(), and rcar_rst_read_mode_pins(), and the CPG/MSSR driver core has been converted from of_match_node() to of_device_get_match_data(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocksGeert Uytterhoeven2017-07-171-0/+7
| | | | | | | | | | | | | | Add the module clocks for the Image Renderer Light (SRAM) Extended 3 (IMR-LX3/LSX3) Distortion Correction Engines on R-Car V2H. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * clk: renesas: div6: Document fields used for parent selectionGeert Uytterhoeven2017-07-171-0/+3
| | | | | | | | | | | | | | | | | | Add the missing documentation for the fields in struct div6_clock related to parent selection for DIV6 clocks with selectable parents, as found in R/SH-Mobile SoCs. Fixes: c6d67fb037f4eaaf ("clk: shmobile: div6: support selectable-input clocks") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: rockchip: Mark rockchip_fractional_approximation staticStephen Boyd2017-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | Silence the sparse warning clk/rockchip/clk.c:172:6: warning: symbol 'rockchip_fractional_approximation' was not declared. Should it be static? Cc: Elaine Zhang <zhangqing@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge tag 'v4.14-rockchip-clk1' of ↵Stephen Boyd2017-08-239-123/+611
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk driver updates from Heiko Stuebner: The biggest change is fixing the jitter on the fractional clock-type Rockchip socs experience with the default approximation. For that we introduce the ability to override it with a clock-specific approximation and use that to create the needed rate settings as described in the Rockchip soc manuals (same for all Rockchip socs). Apart from that we have support for the rk3126 clock controller which is similar to the rk3128 with some minimal differences and a lot of improvements and fixes for the rv1108 clock controller (missing clocks, some clock-ids, naming fixes, register fixes). * tag 'v4.14-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix the rv1108 clk_mac sel register description clk: rockchip: rename rv1108 macphy clock to mac clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocks clk: rockchip: add rk3228 SCLK_SDIO_SRC clk id clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC ID clk: rockchip: add rk3228 sclk_sdio_src ID clk: rockchip: add special approximation to fix up fractional clk's jitter clk: fractional-divider: allow overriding of approximation clk: rockchip: modify rk3128 clk driver to also support rk3126 dt-bindings: add documentation for rk3126 clock clk: rockchip: add some critical clocks for rv1108 SoC clk: rockchip: rename some of clks for rv1108 SoC clk: rockchip: fix up some clks describe error for rv1108 SoC clk: rockchip: support more clks for rv1108 clk: rockchip: fix up the pll clks error for rv1108 SoC clk: rockchip: support more rates for rv1108 cpuclk clk: rockchip: fix up indentation of some RV1108 clock-ids clk: rockchip: rename the clk id for HCLK_I2S1_2CH clk: rockchip: add more clk ids for rv1108
| * | clk: rockchip: fix the rv1108 clk_mac sel register descriptionElaine Zhang2017-08-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The source clock ordering is wrong, as shown in the TRM: cru_sel24_con[8] rmii_extclk_sel clock source select control register 1'b0: from internal PLL 1'b1: from external IO Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rename rv1108 macphy clock to macElaine Zhang2017-08-222-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | This MAC has no internal phy for rv1108 and the whole clock infrastructure hasn't been used yet, so is safe to fix. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: add rv1108 ACLK_GMAC and PCLK_GMAC clocksElaine Zhang2017-08-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add gmac aclk and pclk clock gates. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: add rk3228 SCLK_SDIO_SRC clk idElaine Zhang2017-08-221-1/+1
| | | | | | | | | | | | | | | | | | | | | In some special circumstances, may be need to reparent clk for sclk_sdio_src. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | Merge branch 'v4.14-shared/clkids' into v4.14-clk/nextHeiko Stuebner2017-08-222-0/+3
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| | * | clk: rockchip: add rv1108 ACLK_GAMC and PCLK_GMAC IDElaine Zhang2017-08-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch exports gmac aclk and pclk for dts reference. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| | * | clk: rockchip: add rk3228 sclk_sdio_src IDElaine Zhang2017-08-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch exports sdio src clock for dts reference. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | clk: rockchip: add special approximation to fix up fractional clk's jitterElaine Zhang2017-08-081-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | >From Rockchips fractional divider description: 3.1.9 Fractional divider usage To get specific frequency, clocks of I2S, SPDIF, UARTcan be generated by fractional divider. Generally you must set that denominator is 20 times larger than numerator to generate precise clock frequency. So the fractional divider applies only to generate low frequency clock like I2S, UART. Therefore add a special approximation function that handles this special requirement. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | clk: fractional-divider: allow overriding of approximationElaine Zhang2017-08-082-8/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fractional dividers may have special requirements concerning numerator and denominator selection that differ from just getting the best approximation. For example on Rockchip socs the denominator must be at least 20 times larger than the numerator to generate precise clock frequencies. Therefore add the ability to provide custom approximation functions. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | clk: rockchip: modify rk3128 clk driver to also support rk3126Elaine Zhang2017-08-081-14/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rk3128 and rk3126 have some gate registers describe differences. So need to make some distinctions. The RK3126 and RK3128 Same clock description we move it to the common clock branches. And the different clks description use the own clock branches. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | dt-bindings: add documentation for rk3126 clockElaine Zhang2017-08-081-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This add bindings documentation for rk3126 SoCs. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 07:15:02 +0000