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* mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F IDBrian Norris2012-09-291-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | Datasheets for the following Samsung NAND parts (both MLC and SLC) describe extensions to the Samsung 6-byte extended ID decoding table: K9GBG08U0A (MLC, 6-byte ID) K9GAG08U0F (MLC, 6-byte ID) K9FAG08U0M (SLC, 6-byte ID) The table found in K9GAG08U0F, p.44, contains a superset of the information found in other previous datasheets. This patch adds support for all of these chips, with 512B and 640B OOB sizes. It also changes the detection pattern such that this table applies to all Samsung 6-byte ID NAND, not just MLC. This is safe, according to the NAND parameter data I have collected: Note that nand_base.c does not yet support the bad block marker scheme defined for these chips (i.e., scan 1st and last page for BB markers). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: decode Hynix MLC, 6-byte ID lengthBrian Norris2012-09-291-1/+44
| | | | | | | | | | | | | | Hynix has introduced a new ID decoding scheme for their newer MLC, some of which don't support ONFI. The following devices all follow the pattern given in the datasheet for Hynix H27UBG8T2B, p.22: Hynix H27UAG8T2A Hynix H27UBG8T2A Hynix H27UBG8T2B Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: increase max OOB size to 640Brian Norris2012-09-291-1/+1
| | | | | | | | | Some Hynix and Samsung MLC NAND have 640B OOB size. Sooner or later, we should dynamically allocate the buffers that use these macros. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: add generic READ ID length calculation functionsBrian Norris2012-09-291-7/+65
| | | | | | | | | | | | | | | | When decoding the extended ID bytes of a NAND chip, we have to calculate the ID length according to some heuristic patterns (e.g., Does the ID wrap around? Does it end in trailing zeros?). Currently, these heuristics are built into complicated if/else blocks that can be hard to understand. Now, these checks can be done generically in a function, making them more robust and reusable. In fact, this sort of calculation is needed in future additions to nand_base.c. And with this advancement, we get the added benefit of a more readable "extended ID decode". Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: split simple ID decode into its own functionBrian Norris2012-09-291-20/+31
| | | | | | | | | | | | | | When detecting NAND parameters, the code gets a little ugly so that the logic is obscured. Try to remedy that by moving code to separate functions that have well-defined purposes. This patch splits out the simple ID decode functionality, where all the information regarding NAND size/blocksize/pagesize/oobsize/busw is encoded in the first two bytes of the ID string. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: split extended ID decoding into its own functionBrian Norris2012-09-291-55/+67
| | | | | | | | | | | | | When detecting NAND parameters, the code gets a little ugly so that the logic is obscured. Try to remedy that by moving code to separate functions that have well-defined purposes. This patch splits out the extended ID decode functionality, which handles decoding the 3rd-8th ID bytes to determine NAND device parameters. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: split BB marker options decoding into its own functionBrian Norris2012-09-291-27/+39
| | | | | | | | | | | | | When detecting NAND parameters, the code gets a little ugly so that the logic is obscured. Try to remedy that by moving code to separate functions that have well-defined purposes. This patch splits the bad block marker options detection into its own function, away from the other parameters (e.g., chip size, page size, etc.). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: remove redundant ID readBrian Norris2012-09-291-8/+2
| | | | | | | | | Instead of reading 2 bytes then later 8 bytes, we can simply read all 8 bytes from the start. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: remove unnecessary variableBrian Norris2012-09-291-3/+1
| | | | | | | | We don't actually use the 'ret' variable; we set it, test it, and then it dies. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: docg4: add missing HAS_IOMEM dependencyPeter Huewe2012-09-291-1/+1
| | | | | | | | | | | | | | | | | | | | | While building an allyesconfig for UML I received this error message(s): drivers/mtd/nand/docg4.c: In function 'probe_docg4': drivers/mtd/nand/docg4.c:1272:2: error: implicit declaration of function 'ioremap' [-Werror=implicit-function-declaration] drivers/mtd/nand/docg4.c:1272:10: warning: assignment makes pointer from integer without a cast [enabled by default] drivers/mtd/nand/docg4.c:1327:2: error: implicit declaration of function 'iounmap' [-Werror=implicit-function-declaration] which is caused by the missing implementations on UML. This patch adds this missing HAS_IOMEM dependency and prevents the driver from being build on platforms with no HAS_IOMEM Signed-off-by: Peter Huewe <peterhuewe@gmx.de> Acked-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: gpmi: initialize the timing registers only one timeHuang Shijie2012-09-292-0/+9
| | | | | | | | | | | | The current code initializes the timing registers at very time we call the gpmi_begin(). This really wastes the cpu cycles. Add a new flag to let the gpmi driver initializes the timing registers only one time. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: gpmi: add EDO feature for imx6qHuang Shijie2012-09-293-1/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the frequency on the nand chip pins is above 33MHz, the nand EDO(extended Data Out) timing could be applied. The GPMI implements a Feedback read strobe to sample the read data in the EDO timing mode. This patch adds the EDO feature for the gpmi-nand driver. For some onfi nand chips, the mode 4 is the fastest; while for other onfi nand chips, the mode 5 is the fastest. This patch only adds the support for the fastest asynchronous timing mode. So this patch only supports the mode 4 and mode 5. I tested several Micron's ONFI nand chips with EDO enabled, take Micron MT29F32G08MAA for example (in mode 5, 100MHz): 1) The test result BEFORE we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 3632 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 3554 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 3592 KiB/s ....................................... ================================================= 2) The test result AFTER we add the EDO feature: ================================================= mtd_speedtest: MTD device: 2 mtd_speedtest: MTD device size 209715200, eraseblock size 524288, page size 4096, count of eraseblocks 400, pages per eraseblock 128, OOB size 218 ....................................... mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 19555 KiB/s ....................................... mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 17319 KiB/s ....................................... mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 18339 KiB/s ....................................... ================================================= 3) The read data performance is much improved by more then 5 times. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: gpmi: do not set the default values for the extra clocksHuang Shijie2012-09-291-10/+5
| | | | | | | | | | | | | | | | The default frequencies of the extra clocks are 200MHz. The current code sets the extra clocks to 44.5MHz. When i add the EDO feature to gpmi, i have to revert the extra clocks to 200MHz. So it is better that we do not set the default values for the extra clocks. The driver runs well even when we do not set the default values for extra clocks. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: gpmi: simplify the DLL setting codeHuang Shijie2012-09-291-13/+9
| | | | | | | | | The setting DLL code is a little mess. Just simplify the code and the comments. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: gpmi: add a new field for HW_GPMI_CTRL1Huang Shijie2012-09-293-0/+17
| | | | | | | | | add the WRN_DLY_SEL field for HW_GPMI_CTRL1. This field is used as delay for gpmi write strobe. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: gpmi: do not get the clock frequency in gpmi_begin()Huang Shijie2012-09-291-6/+4
| | | | | | | | | | | | | | | The current code will gets the clock frequency which is used by gpmi_nfc_compute_hardware_timing(). It makes the code a little mess. So move the `get clock frequency` code to the gpmi_nfc_compute_hardware_timing() itself. This makes the code tidy and clean. This patch also uses the macro NSEC_PER_SEC to replace the `1000000000`. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: gpmi: add a new field for HW_GPMI_TIMING1Huang Shijie2012-09-293-8/+22
| | | | | | | | | | | | | | | The gpmi_nfc_compute_hardware_timing{} should contains all the fields setting for gpmi timing registers. It already contains the fields for HW_GPMI_TIMING0 and HW_GPMI_CTRL1. So it is better to add a new field setting for HW_GPMI_TIMING1 in this data structure. This makes the code more clear in logic. This patch also changes some comments to make the code more readable. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add helpers to get the supportted ONFI timing modeHuang Shijie2012-09-291-0/+25
| | | | | | | | | | | | | | add onfi_get_async_timing_mode() to get the supportted asynchronous timing mode. add onfi_get_sync_timing_mode() to get the supportted synchronous timing mode. Also add the neccessary macros : the timing modes. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: add helpers to set/get features for ONFI nandHuang Shijie2012-09-292-0/+64
| | | | | | | | | Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand. Also add the necessary macros. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: fsl_ifc_nand: fix sparse warningsKim Phillips2012-09-291-3/+3
| | | | | | | | | | | | drivers/mtd/nand/fsl_ifc_nand.c:196:34: warning: cast removes address space of expression [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: warning: incorrect type in initializer (different address spaces) [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: expected unsigned int [noderef] [usertype] <asn:2>*mainarea [sparse] drivers/mtd/nand/fsl_ifc_nand.c:196:34: got unsigned int [usertype] *<noident> [sparse] ... Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nandsim: bugfix: fail if overridesize is too bigRichard Genoud2012-09-291-0/+1
| | | | | | | | | | | | | If override size is too big, the module was actually loaded instead of failing, because retval was not set. This lead to memory corruption with the use of the freed structs nandsim and nand_chip. Cc: stable@vger.kernel.org Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: docg4: ecc.read_page() returns 0 on uncorrectable errorsMike Dunn2012-09-291-0/+2
| | | | | | | | | | | | Currently the docg4's ecc.read_page() method returns -EBADMSG when uncorrectable bitflips occur. This is wrong; 0 should be returned in this case. An error code should only be returned by this method in the case of a hardware error (probably -EIO). Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: use NAND_BBT_SCAN_MAXBLOCKSRichard Genoud2012-09-291-4/+5
| | | | | | | | | | | | In nand_bbt.c, a hardcoded value was used instead of the define meant for that, so we use the define. There's no functional change. Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: remove bcmring NAND driverChristian Daudt2012-09-297-1255/+0
| | | | | | | | | | | This driver is being removed as part of the cleanup of the bcmring SoC from mainline as it is no longer maintained. Signed-off-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: expand description of read_page method in comment headerMike Dunn2012-09-291-2/+4
| | | | | | | | | In the absence of any formal documentation of the nand interface, I thought this patch to the header file might be helpful. Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand: clk: preparation for switch to common clock frameworkm-karicheri2@ti.com2012-09-291-3/+3
| | | | | | | | | | | | | | | | | As a first step towards migrating davinci platforms to use common clock framework, replace all instances of clk_enable() with clk_prepare_enable() and clk_disable() with clk_disable_unprepare(). Until the platform is switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just adds a might_sleep() call and would work without any issues. This will make it easy later to switch to common clk based implementation of clk driver from DaVinci specific driver. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: mtd_nandecctest: add double bit error detection testsAkinobu Mita2012-09-291-0/+79
| | | | | | | | | | | | | | | | | | This adds the double bit error detection test cases listed below: * Prepare data block with double bit error and ECC data without corruption, and verify that the uncorrectable error is detected by __nand_correct_data(). * Prepare data block with single bit error and ECC data with single bit error, and verify that the uncorrectable error is detected. * Prepare data block without corruption and ECC data with double bit error, and verify that the uncorrectable error is detected. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: mtd_nandecctest: add single bit error correction testAkinobu Mita2012-09-291-0/+37
| | | | | | | | | | | This adds the single bit error correction test case listed below: Prepare data block without corruption and ECC data with single bit error, and verify that the data block is preserved by __nand_correct_data(). Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: mtd_nandecctest: add no corruption testAkinobu Mita2012-09-291-0/+26
| | | | | | | | | | | This adds no corruptin test case listed below: Prepare data block and ECC data with no corruption, and verify that the data block is preserved by __nand_correct_data() Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: mtd_nandecctest: rewrite the test routineAkinobu Mita2012-09-291-23/+70
| | | | | | | | | | | | | | | This rewrites the entire test routine in order to make it easy to add more tests by later changes and minimize duplication of each tests as much as possible. Now that each test is described by the members of struct nand_ecc_test: - name: descriptive testname - prepare: function to prepare data block and ecc with artifical corruption - verify: function to verify the result of correcting data block Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: mtd_nandecctest: support injecting bit error for ecc codeAkinobu Mita2012-09-291-2/+16
| | | | | | | | | | | | | | | | | | | | | | Currently inject_single_bit_error() is used to inject single bit error into randomly selected bit position of the 256 or 512 bytes data block. Later change will add tests which inject bit errors into the ecc code. Unfortunately, inject_single_bit_error() doesn't work for the ecc code which is not a multiple of sizeof(unsigned long). Because bit fliping at random position is done by __change_bit(). For example, flipping bit position 0 by __change_bit(0, addr) modifies 3rd byte (32bit) or 7th byte (64bit) on big-endian systems. Using little-endian version of bitops can fix this issue. But little-endian version of __change_bit is not yet available. So this defines __change_bit_le() locally in a similar fashion to asm-generic/bitops/le.h and use it. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: tests: test for multi-bit error correctionIwo Mergler2012-09-292-0/+461
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This tests ECC biterror recovery on a single NAND page. Mostly intended to test ECC hardware and low-level NAND driver. There are two test modes: 0 - artificially inserting bit errors until the ECC fails This is the default method and fairly quick. It should be independent of the quality of the FLASH. 1 - re-writing the same pattern repeatedly until the ECC fails. This method relies on the physics of NAND FLASH to eventually generate '0' bits if '1' has been written sufficient times. Depending on the NAND, the first bit errors will appear after 1000 or more writes and then will usually snowball, reaching the limits of the ECC quickly. The test stops after 10000 cycles, should your FLASH be exceptionally good and not generate bit errors before that. Try a different page offset in that case. Please note that neither of these tests will significantly 'use up' any FLASH endurance. Only a maximum of two erase operations will be performed. Signed-off-by: Iwo Mergler <Iwo.Mergler@netcommwireless.com.au> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: cmdlinepart: make the partitions rule more strictShmulik Ladkani2012-09-291-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Huang Shijie <shijie8@gmail.com> explains: Assume we have a 1GiB(8Gib) NAND chip, and we set the partitions in the command line like this: #gpmi-nand:100m(boot),100m(kernel),1g(rootfs) In this case, the partition truncating occurs. The current code will get the following result: ---------------------------------- root@freescale ~$ cat /proc/mtd dev: size erasesize name mtd0: 06400000 00040000 "boot" mtd1: 06400000 00040000 "kernel" ---------------------------------- It is obvious that we lost the truncated partition `rootfs` which should be 824MiB in this case. Also, forbid 0-sized partitions. Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: nand/gpio: Convert to module_platform_driver()Sachin Kamat2012-09-291-14/+1
| | | | | | | | | module_platform_driver simplifies the code by eliminating module_init and module_exit calls. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: mxc_nand: Adapt the clock name to the new clock frameworkFabio Estevam2012-09-291-1/+1
| | | | | | | | | | | | With the new i.mx clock framework the mxc_nand clock is registered as: clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");0") So we do not need to pass "nfc" string and can use NULL instead. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: mxc_nand: Convert to module_platform_driver()Fabio Estevam2012-09-291-15/+3
| | | | | | | | Using module_platform_driver() makes the code smaller and cleaner. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: gpmi-nand: Convert to module_platform_driver()Fabio Estevam2012-09-291-22/+7
| | | | | | | | | Using module_platform_driver() makes the code smaller and cleaner. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: gpmi-nand: Improve logging styleFabio Estevam2012-09-291-3/+6
| | | | | | | | | Improve logging style by prefixing the pr_ messages with "gpmi_nand". Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: m25p80: Disable 4KiB erase for s25sl032p, s25sl064pMarek Vasut2012-09-291-2/+2
| | | | | | | | | | | | | | | | | Quoting from the datasheet for S25FL064P, rev. 05, Nov 18 2011, § 9.17: "A 64 kB[sic] sector erase (D8h) command issued on 4 kB or 8 kB erase sectors will erase all sectors in the specified 64 kB region. However, please note that a 4 kB sector erase (20h) or 8 kB sector erase (40h) command will not work on a 64 kB sector." Referring further to Table 8.1 and Table 8.2, it is clearly seen that most of the sectors are 64KiB; therefore disable this 4KiB erase support since it's valid only on first/last sectors. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* mtd: basic (read only) driver for BCMA serial flashRafał Miłecki2012-09-294-0/+116
| | | | | | | | | | | This registers MTD driver for serial flash platform device. Right now it supports reading only, writing still has to be implemented. Artem: minor amendments. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* Merge commit '371a00448f95adaa612cf1a0b31a11e7093bc706' of ↵David Woodhouse2012-09-29177-1751/+4948
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git' We need the following 2 patches from the 'net-next' tree for the BCMA flash driver: 371a004 bcma: detect and register NAND flash device d57ef3a bcma: detect and register serial flash device and this is why we are merging the net-next tree (presumably persistent) up to commit '371a004'. Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * bcma: detect and register NAND flash deviceRafał Miłecki2012-08-215-4/+48
| | | | | | | | | | Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
| * bcma: detect and register serial flash deviceRafał Miłecki2012-08-216-4/+146
| | | | | | | | | | Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
| * Merge branch 'for-john' of ↵John W. Linville2012-08-2184-617/+1245
| |\ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next Conflicts: drivers/net/wireless/mac80211_hwsim.c
| | * mac80211: clean up ieee80211_subif_start_xmitJohannes Berg2012-08-201-17/+6
| | | | | | | | | | | | | | | | | | | | | There's no need to carry around a return value that is always NETDEV_TX_OK anyway. Signed-off-by: Johannes Berg <johannes.berg@intel.com>
| | * mac80211: pass channel to ieee80211_send_probe_reqJohannes Berg2012-08-204-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In multi-channel scenarios, the channel that we will transmit a probe request on isn't always the current channel (which will be NULL anyway) but will instead be the channel that the AP is on. Pass the channel to the ieee80211_send_probe_req() function so it can be used in the different scenarios. The scan code continues to pass the current channel, of course. Signed-off-by: Johannes Berg <johannes.berg@intel.com>
| | * mac80211: convert ops checks to WARN_ONJohannes Berg2012-08-201-7/+5
| | | | | | | | | | | | | | | | | | | | | There's no need to BUG_ON when a driver registers invalid operations, warn and return an error. Signed-off-by: Johannes Berg <johannes.berg@intel.com>
| | * mac80211: check operating channel in scanJohannes Berg2012-08-201-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The optimisation of scanning only on the current channel should check the operating channel. Also modify it to compare channel pointer rather than the frequency. Signed-off-by: Johannes Berg <johannes.berg@intel.com>
| | * mac80211: use RX status band instead of current bandJohannes Berg2012-08-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even for single-channel devices it is possible that we switch the channel temporarily (e.g. for scanning) but while doing so process a received frame that was still received on the old channel, so checking the current band is racy. Use the band from status instead. Signed-off-by: Johannes Berg <johannes.berg@intel.com>
| | * mac80211: don't assume channel is set in tracingJohannes Berg2012-08-201-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the move to multi-channel and away from drv_config(), hw.conf.channel will not always be set, only for devices using the current API instead of the new channel context APIs. Check the channel is set before adding its frequency to the trace data. Also break some overly long lines in the code. Signed-off-by: Johannes Berg <johannes.berg@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 18:54:09 +0000