summaryrefslogtreecommitdiffstats
path: root/arch/arc/mm/cache.c
Commit message (Expand)AuthorAgeFilesLines
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-4/+1
* ARC: PAE40: don't panic and instead turn off hw iocVineet Gupta2019-04-021-15/+16
* Merge tag 'dma-mapping-4.21' of git://git.infradead.org/users/hch/dma-mappingLinus Torvalds2018-12-281-1/+1
|\
| * dma-mapping: bypass indirect calls for dma-directChristoph Hellwig2018-12-131-1/+1
* | ARC: IOC: panic if kernel was started with previously enabled IOCEugeniy Paltsev2018-11-121-3/+17
|/
* ARC: IOC: panic if both IOC and ZONE_HIGHMEM enabledEugeniy Paltsev2018-09-041-0/+13
* ARC: dma [IOC] Enable per device io coherencyEugeniy Paltsev2018-09-041-15/+8
* arc: fix type warnings in arc/mm/cache.cRandy Dunlap2018-07-301-3/+4
* ARC: add SMP_CACHE_BYTES value validateEugeniy Paltsev2018-07-301-0/+10
* mm: fix races between swapoff and flush dcacheHuang Ying2018-04-051-1/+1
* ARCv2: cache: fix slc_entire_op: flush only instead of flush-n-invEugeniy Paltsev2018-01-171-1/+4
* ARC: mm: Decouple RAM base address from kernel link addressEugeniy Paltsev2017-09-011-1/+1
* ARCv2: IOC: Tighten up the contraints (specifically base / size alignment)Eugeniy Paltsev2017-09-011-8/+19
* ARCv2: SLC: provide a line based flush routine for debuggingVineet Gupta2017-08-301-1/+53
* ARC: set boot print log level to PR_INFONoam Camus2017-08-281-1/+1
* ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoCVineet Gupta2017-08-041-6/+28
* ARCv2: PAE40: Explicitly set MSB counterpart of SLC region ops addressesAlexey Brodkin2017-08-041-2/+11
* ARCv2: SLC: Make sure busy bit is set properly for region opsAlexey Brodkin2017-08-041-0/+3
* ARCv2: mm: Merge 2 updates to DC_CTRL for region flushVineet Gupta2017-05-021-14/+32
* ARCv2: mm: Implement cache region flush operationsVineet Gupta2017-05-021-0/+68
* ARC: mm: Move full_page computation into cache version agnostic wrapperVineet Gupta2017-05-021-13/+12
* ARCv2: SLC: Make sure busy bit is set properly on SLC flushingAlexey Brodkin2017-03-301-0/+3
* ARC: Revert "ARC: mm: IOC: Don't enable IOC by default"Vineet Gupta2017-01-181-1/+1
* ARC: mm: split arc_cache_init to allow __init reaping of bulkVineet Gupta2017-01-181-14/+19
* ARCv2: IOC: Use actual memory size to setup aperture sizeVineet Gupta2017-01-181-2/+10
* ARCv2: IOC: Adhere to progamming model guidelines to avoid DMA corruptionVineet Gupta2017-01-181-0/+46
* ARCv2: IOC: refactor the IOC and SLC operations into own functionsVineet Gupta2017-01-181-21/+47
* ARC: mmu: clarify the MMUv3 programming modelVineet Gupta2017-01-041-1/+5
* ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcacheVineet Gupta2016-12-191-4/+9
* ARC: mm: No need to save cache version in @cpuinfoVineet Gupta2016-12-191-11/+4
* ARC: mm: IOC: Don't enable IOC by defaultVineet Gupta2016-11-281-1/+1
* ARCv2: boot log: print IOC exists as well as enabled statusVineet Gupta2016-10-281-6/+3
* ARCv2: IOC: use @ioc_enable not @ioc_exist where intendedVineet Gupta2016-10-241-4/+6
* ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 coresVineet Gupta2016-09-301-5/+18
* ARC: Elide redundant setup of DMA callbacksVineet Gupta2016-08-101-0/+9
* Fix typosAndrea Gelmini2016-05-301-3/+3
* mm, fs: get rid of PAGE_CACHE_* and page_cache_{get,release} macrosKirill A. Shutemov2016-04-041-1/+1
* ARCv2: ioremap: Support dynamic peripheral address spaceVineet Gupta2016-03-191-0/+7
* ARC: dma: ioremap: use phys_addr_t consistenctly in code pathsVineet Gupta2016-03-191-15/+15
* ARC: Fix misspellings in comments.Adam Buchbinder2016-03-111-1/+1
* mm: differentiate page_mapped() from page_mapcount() for compound pagesKirill A. Shutemov2016-01-151-2/+2
* ARC: mm: PAE40 supportVineet Gupta2015-10-291-4/+40
* ARC: mm: PAE40: switch to using phys_addr_t for physical addressesVineet Gupta2015-10-281-13/+13
* ARC: mm: preps ahead of HIGHMEM supportVineet Gupta2015-10-281-5/+11
* ARC: boot log: move helper macros to header for reuseVineet Gupta2015-10-171-3/+2
* ARC: Eliminate some ARCv2 specific code for ARCompact buildVineet Gupta2015-08-211-26/+32
* ARCv2: IOC: Allow boot time disableAlexey Brodkin2015-08-201-3/+4
* ARCv2: SLC: Allow boot time disableVineet Gupta2015-08-201-2/+19
* ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin2015-08-201-16/+98
* ARCv2: guard SLC DMA ops with spinlockAlexey Brodkin2015-07-061-2/+10
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 07:47:05 +0000