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* ARM: dts: aspeed: mtmitchell: Add I2C NVMe alias portChanh Nguyen2023-10-131-0/+267
| | | | | | | | | | | | | Adds the I2C alias ports to each NVMe drive via the backplane card. Besides that, it also adds the eeprom and temperature sensor on the backplane card. Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20231005035525.19036-8-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: mtmitchell: Remove redundant ADC configurationsChanh Nguyen2023-10-131-14/+1
| | | | | | | | | | | Mt.Mitchell DVT and later hardware do not use adc1. It only uses adc0 with channels 0, 1 and 2. This commit removes redundant ADC configurations. Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20231005035525.19036-7-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: mtmitchell: Add inlet temperature sensorChanh Nguyen2023-10-131-0/+5
| | | | | | | | | | Add the inlet temperature at address 0x48, which is connected via BMC I2C8. Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20231005035525.19036-6-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: mtjade: Add the gpio-hogChanh Nguyen2023-10-131-0/+14
| | | | | | | | | | | | | Add the GPIOR5 as a gpio-hog with output high so that can power the OCP card once the BMC booting. Add the GPIOAC5 as a gpio-hog with output high to notice the BMC state. Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20231005035525.19036-4-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: mtjade, mtmitchell: Add new gpio-line-namesChanh Nguyen2023-10-132-25/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new gpio-line-names from the Mt.Jade and Mt.Mitchell HW schematic. Mt.Jade GPIOB5: presence-cpu0 GPIOF0: ps0-pgood GPIOF1: ps1-pgood GPIOG2: host0-shd-ack-n GPIOH0: uart1-mode1 GPIOH1: uart2-mode1 GPIOH2: uart3-mode1 GPIOH3: uart4-mode1 GPIOH7: i2c6-reset-n GPIOH3: host0-reboot-ack-n GPIOM4: s0-i2c9-alert-n GPIOM5: s1-i2c9-alert-n GPIOQ6: led-identify GPIOS0: s0-vr-hot-n GPIOS1: s1-vr-hot-n GPIOS5: vr-pmbus-sel-n GPIOY3: bmc-vga-en-n GPIOZ3: s0-rtc-lock GPIOAC2: spi0-program-sel GPIOAC3: spi0-backup-sel Mt.Mitchell: GPIOC3: bmc-debug-mode GPIOE1: eth-phy-int-n GPIOH0: jtag-program-sel GPIOH1: fpga-program-b GPIOW3: s1-pcp-pgood Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20231005035525.19036-3-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: mtjade, mtmitchell: Update gpio-line-namesChanh Nguyen2023-10-132-24/+24
| | | | | | | | | | Update GPIO line-name to follow naming convention specified at github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20231005035525.19036-2-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Minerva: Add Facebook Minerva CMC boardYang Chen2023-10-132-0/+266
| | | | | | | | | Add linux device tree entry related to the Minerva Chassis Management Controller (CMC) specific devices connected to the Aspeed SoC (AST2600). Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com> Link: https://lore.kernel.org/r/20230914125648.3966519-3-yangchen.openbmc@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: bonnell: Add reserved memory for TPM event logEddie James2023-09-221-1/+7
| | | | | | | | | | | Trusted boot support requires the platform event log passed up from the bootloader. In U-Boot, this can now be accomplished with a reserved memory region, so add a region for this purpose to the Bonnell BMC devicetree. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20230616142610.356623-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Fix pca954x i2c-mux node namesGeert Uytterhoeven2023-08-1223-136/+136
| | | | | | | | | | | | | | | | | | "make dtbs_check": arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dtb: i2c-switch@70: $nodename:0: 'i2c-switch@70' does not match '^(i2c-?)?mux' From schema: Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml arm/boot/dts/aspeed-bmc-bytedance-g220a.dtb: i2c-switch@70: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c@0', 'i2c@1', 'i2c@2', 'i2c@3' were unexpected) From schema: Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml ... Fix this by renaming PCA954x nodes to "i2c-mux", to match the I2C bus multiplexer/switch DT bindings and the Generic Names Recommendation in the Devicetree Specification. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: aspeed: Add AST2600 I3C control pinsDylan Hung2023-08-101-0/+10
| | | | | | | | | Add pinctrl support for the I3C1 and I3C2 pins. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Jeremy Kerr <jk@codeconstruct.com.au> Link: https://lore.kernel.org/r/20230809134413.3614535-1-dylan_hung@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: everest: Move common devices upJoel Stanley2023-08-101-71/+70
| | | | | | | | Other systems have the SoC devices listed before the FSI description. Move them up in order to make them similar. Link: https://lore.kernel.org/r/20230809074921.116987-6-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: everest: Reorganise FSI descriptionEddie James2023-08-101-627/+921
| | | | | | | | | Use the P10 quad FSI CFAM description to reduce duplication and add the I2C responders and associated engines. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20230809074921.116987-5-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: rainier: Reorganise FSI descriptionJoel Stanley2023-08-101-676/+2
| | | | | | | Use the P10 quad FSI CFAM description to reduce duplication. Link: https://lore.kernel.org/r/20230809074921.116987-4-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: bonnell: Reorganise FSI descriptionJoel Stanley2023-08-101-354/+30
| | | | | | | Use the P10 dual FSI CFAM description to reduce duplication. Link: https://lore.kernel.org/r/20230809074921.116987-3-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add P10 FSI descriptionsEddie James2023-08-102-0/+1685
| | | | | | | | These will be used by BMCs attached to a IBM Power10 server CPU. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20230809074921.116987-2-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: yosemite4: add Facebook Yosemite 4 BMCDelphine CC Chiu2023-08-102-0/+625
| | | | | | | | | | | Add linux device tree entry for Yosemite 4 devices connected to BMC. The Yosemite 4 is a Meta multi-node server platform, based on AST2600 SoC. Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20230810070032.335161-3-Delphine_CC_Chiu@wiwynn.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: wedge400: Set eMMC max frequencyTao Ren2023-08-101-0/+1
| | | | | | | | | | Set eMMC max frequency to 25MHz to prevent intermittent eMMC access failures. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20230803230324.731268-4-rentao.bupt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: wedge400: Enable more ADC channelsTao Ren2023-08-101-1/+2
| | | | | | | | | | Enable ASPEED-ADC channels 5-8 to support voltage monitoring of all the Wedge400 hardware revisions. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20230803230324.731268-3-rentao.bupt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Update spi alias in Facebook AST2500 Common dtsiTao Ren2023-08-101-0/+4
| | | | | | | | | | Set FMC controller to "spi0" in ast2500-facebook-netbmc-common.dtsi so the spi bus is consistent with the flash labels defined in flash layout. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20230803230324.731268-2-rentao.bupt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: rainier: Remove TPM deviceLakshmi Yadlapati2023-08-101-5/+0
| | | | | | | | TPM is disabled in Rainier, remove TPM device. Signed-off-by: Lakshmi Yadlapati <lakshmiy@us.ibm.com> Link: https://lore.kernel.org/r/20230725141606.1641080-2-lakshmiy@us.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Add AST2600 VUARTsJoel Stanley2023-08-101-0/+20
| | | | | | | | The AST2600 has two more vuarts, placed between the existing two in the memory map. Link: https://lore.kernel.org/r/20230620042257.73665-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: mtmitchell: Add MCTPChanh Nguyen2023-08-101-0/+9
| | | | | | | | Enable MCTP driver on I2C3 bus for MCTP transaction Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Link: https://lore.kernel.org/r/20230620092537.20007-4-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: mtmitchell: Update ADC sensors for Mt.Mitchell DVT systemsChanh Nguyen2023-08-101-41/+66
| | | | | | | | | Change to use I2C ADC controller (ltc2497) for Mt.Mitchell DVT and later hardware. Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Link: https://lore.kernel.org/r/20230620092537.20007-3-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: mtmitchell: Enable the BMC UART8 and UART9Chanh Nguyen2023-08-101-0/+13
| | | | | | | | | The BMC UART8 and UART9 were connected to the Secpro and Mpro console of socket S1 on the Mt.Mitchell system. Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Link: https://lore.kernel.org/r/20230620092537.20007-2-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: Adding Inventec Starscream BMCChen PJ2023-07-102-0/+390
| | | | | | | | | Initial introduction of Inventec Starscream x86 family equipped with AST2600 BMC SoC. Signed-off-by: Chen PJ <Chen.pj@inventec.com> Link: https://lore.kernel.org/r/20230703060222.24263-2-chen.pj@inventec.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: aspeed: bonnell: Add DIMM SPDEddie James2023-07-101-0/+20
| | | | | | | | | Add the DIMM SPD to the processor I2C busses. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20230322140348.569397-5-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
* ARM: dts: Move .dts files to vendor sub-directoriesRob Herring2023-06-2176-0/+38736
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
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