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* ARM: dts: BCM5301X: Drop "clock-names" from the SPI nodeRafał Miłecki2023-07-271-1/+0
| | | | | | | | | | | | | | | | [ Upstream commit d3c8e2c5757153bbfad70019ec1decbca86f3def ] There is no such property in the SPI controller binding documentation. Also Linux driver doesn't look for it. This fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: spi@18029200: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20230503122830.3200-1-zajec5@gmail.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
* ARM: dts: BCM5301X: Add interrupt properties to GPIO nodeFlorian Fainelli2021-12-011-0/+2
| | | | | | | | | | | | [ Upstream commit 40f7342f0587639e5ad625adaa15efdd3cffb18f ] The GPIO controller is also an interrupt controller provider and is currently missing the appropriate 'interrupt-controller' and '#interrupt-cells' properties to denote that. Fixes: fb026d3de33b ("ARM: BCM5301X: Add Broadcom's bus-axi to the DTS file") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
* ARM: dts: BCM5301X: Fix I2C controller interruptFlorian Fainelli2021-12-011-1/+1
| | | | | | | | | | | | | | [ Upstream commit 754c4050a00e802e122690112fc2c3a6abafa7e2 ] The I2C interrupt controller line is off by 32 because the datasheet describes interrupt inputs into the GIC which are for Shared Peripheral Interrupts and are starting at offset 32. The ARM GIC binding expects the SPI interrupts to be numbered from 0 relative to the SPI base. Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT") Tested-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
* ARM: dts: BCM5301X: Fixup SPI bindingRafał Miłecki2021-07-201-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | [ Upstream commit d5aede3e6dd1b8ca574600a1ecafe1e580c53f2f ] 1. Reorder interrupts 2. Fix typo: s/spi_lr_overhead/spi_lr_overread/ 3. Rename node: s/spi-nor@0/flash@0/ This fixes: arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dt.yaml: spi@18029200: interrupt-names: 'oneOf' conditional failed, one must be fixed: ['spi_lr_fullness_reached', 'spi_lr_session_aborted', 'spi_lr_impatient', 'spi_lr_session_done', 'spi_lr_overhead', 'mspi_done', 'mspi_halted'] is too long Additional items are not allowed ('spi_lr_session_aborted', 'spi_lr_impatient', 'spi_lr_session_done', 'spi_lr_overhead', 'mspi_done', 'mspi_halted' were unexpected) 'mspi_done' was expected 'spi_l1_intr' was expected 'mspi_halted' was expected 'spi_lr_fullness_reached' was expected 'spi_lr_session_aborted' was expected 'spi_lr_impatient' was expected 'spi_lr_session_done' was expected 'spi_lr_overread' was expected From schema: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dt.yaml: spi-nor@0: $nodename:0: 'spi-nor@0' does not match '^flash(@.*)?$' From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
* ARM: dts: BCM5301X: Fixed QSPI compatible stringFlorian Fainelli2020-09-171-1/+1
| | | | | | | | | | | [ Upstream commit b793dab8d811e103665d6bddaaea1c25db3776eb ] The string was incorrectly defined before from least to most specific, swap the compatible strings accordingly. Fixes: 1c8f40650723 ("ARM: dts: BCM5301X: convert to iProc QSPI") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
* ARM: dts: BCM5301X: Fix MDIO node address/size cellsFlorian Fainelli2020-01-121-2/+2
| | | | | | | | | | | | | | [ Upstream commit 093c3f94e922d83a734fc4da08cc5814990f32c6 ] The MDIO node on BCM5301X had an reversed #address-cells and #size-cells properties, correct those, silencing checker warnings: .../linux/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: mdio@18003000: #address-cells:0:0: 1 was expected Reported-by: Simon Horman <simon.horman@netronome.com> Fixes: 23f1eca6d59b ("ARM: dts: BCM5301X: Specify MDIO bus in the DT") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
* ARM: dts: BCM5301X: Fix most DTC W=1 warningsFlorian Fainelli2019-06-221-6/+4
| | | | | | | Fix the bulk of the unit_address_vs_reg warnings and unnecessary \#address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: Kill off skeleton{64}.dtsiRob Herring2019-01-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: BCM5301X: Describe Northstar pins mux controllerRafał Miłecki2018-11-301-0/+44
| | | | | | | | This describes hardware & will allow referencing pin functions. The first usage is UART1 which allows supporting devices using it. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: Specify flash partitionsRafał Miłecki2018-08-311-1/+4
| | | | | | | | | | | | | | | Most devices use Broadcom standard partitions which allows them to be described with the "brcm,bcm947xx-cfe-partitions". Exceptions are: 1) TP-LINK devices which use "os-image" partition with TRX containing kernel only + separated rootfs partition. 2) Asus RT-AC87U with custom "asus" partition. This commit also removes undocumented and unsupported linux,part-probe binding which got accidentally upstreamed while describing SPI controller. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* Merge tag 'arm-soc/for-4.19/devicetree' of ↵Olof Johansson2018-07-141-8/+27
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/Broadcom/stblinux into next/dt This pull request contains Broadcom ARM-based SoCs Device Tree changes for 4.19, please pull the following: - Clement adds ethernet aliases to the Cygnus DTS include file such that a DT aware bootloader such as u-boot can properly insert MAC addresses - Mohamed adds a Device Tree node for the HWRNG found on Cygnus SoCs - Vivek migrates all the BCM5301x (Northstar) Device Tree sources to use the proper USB 3.0 PHY representation using its parent MDIO bus. Vivek also completes the Linksys EA9500 Device Tree by adding support for LEDs, internal and external switches. - Rafal adds the ARM architected timer to the BCM53573 Device Tree include file. - Eric adds the Performance Monitoring Unit to the BCM2837 DTS include file since it was absent before - Boris adds the BCM283x transposer block to the Device Tree - Stefan adds the Raspberry Pi Compute Module (CM1) Device Tree include and sources. * tag 'arm-soc/for-4.19/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: BCM5301X: Add support for Linksys EA9500 ARM: dts: BCM53573: Add architected timer ARM: dts: BCM5301X: Make USB 3.0 PHY use MDIO PHY driver ARM: dts: cygnus: enable iproc-hwrng ARM: dts: cygnus: add ethernet0 alias ARM: dts: bcm283x: Add Transposer block ARM: dts: bcm283x: Add the PMU to the devicetree. ARM: dts: add Raspberry Pi Compute Module and IO board Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: dts: BCM5301X: Make USB 3.0 PHY use MDIO PHY driverVivek Unune2018-07-091-8/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the USB 3.0 PHY in bcm5301x.dtsi uses platform driver which requires register range "ccb-mii" <0x18003000 0x1000>. This range overlaps with MDIO cmd and param registers (<0x18003000 0x8>). Essentially, the platform driver partly acts like a MDIO bus driver, hence to use of this register range. In some Northstar devices like Linksys EA9500, secondary switch is connected via external MDIO. The only way to access and configure the external switch is via MDIO bus. When we enable the MDIO bus in it's current state, the MDIO bus and any child buses fail to register because of the register range overlap. On Northstar, the USB 3.0 PHY is connected at address 0x10 on the internal MDIO bus. This change moves the usb3_phy node and makes it a child node of internal MDIO bus. Thanks to Rafał Miłecki's commit af850e14a7ae ("phy: bcm-ns-usb3: add MDIO driver using proper bus layer") the same USB 3.0 platform driver can now act as USB 3.0 PHY MDIO driver. Tested on Linksys Panamera (EA9500) Signed-off-by: Vivek Unune <npcomplete13@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | ARM: dts: BCM5301x: Fix i2c controller interrupt typeFlorian Fainelli2018-06-181-1/+1
|/ | | | | | | The i2c controller should be using IRQ_TYPE_LEVEL_HIGH, fix that. Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* arm: dts: fix unit-address leading 0sRob Herring2017-10-201-3/+3
| | | | | | | | | | | | | Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: BCM5301X: Specify USB ports for each controllerRafał Miłecki2017-08-011-0/+34
| | | | | | | | | Northstar has 3 controllers: OHCI and EHCI (each with 2 ports) and XHCI (with just 1 port). Describe them in the DT. In future this will allow to reference them as trigger sources. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: Specify MDIO bus in the DTRafał Miłecki2017-06-121-0/+8
| | | | | | | | Northstar devices have MDIO bus that may contain various PHYs attached. A common example is USB 3.0 PHY (that doesn't have an MDIO driver yet). Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: Add CPU thermal sensor and zoneRafał Miłecki2017-06-121-0/+26
| | | | | | | | | | This uses CPU thermal sensor available on every Northstar chipset to monitor temperature. We don't have any cooling or throttling so only a critical trip was added. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: Specify serial console params in dtsi filesRafał Miłecki2017-03-221-4/+0
| | | | | | | | | | | | | | So far every Northstar device we have seen was using the same serial console params (115200n8). It probably make the most sense to put it in some proper dtsi files instead of repeating over and over for every single device. As different boards may use different bootloaders it seems the safest idea is to use board specific dtsi files. Just in case some vendor decides to use different UART (parameters) this can be always easily overwritten. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: Add I2C support to the DTJon Mason2017-03-181-0/+10
| | | | | | | | | Add I2C support to the bcm5301x Device Tree. Since no driver changes are needed to enable this hardware, only the device tree changes are required to make this functional. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: Add TWD WD Support to DTJon Mason2017-03-181-3/+12
| | | | | | | | | Add support for the ARM TWD Watchdog to the bcm5301x device tree. The ARM TWD timer allocated the register space for the WDT, so this patch necessitated shrinking that. Also, the GIC masks were added for these. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: Correct GIC_PPI interrupt flagsJon Mason2017-03-181-2/+2
| | | | | | | | | | | | | GIC_PPI flags were misconfigured for the timers, resulting in errors like: [ 0.000000] GIC: PPI11 is secure or misconfigured Changing them to being edge triggered corrects the issue Suggested-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Jon Mason <jon.mason@broadcom.com> Fixes: d27509f1 ("ARM: BCM5301X: add dts files for BCM4708 SoC") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: convert to iProc QSPIJon Mason2017-03-051-14/+36
| | | | | | | | | | | The iproc-qspi driver is the SPI driver that should be used going forward. Modify the SPI DT entry to use this driver, and add an entry in the bcm953012k DTS file to enable the SPI. Tested on the bcm953012k board. Signed-off-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: Set 5 GHz wireless frequency limits on Netgear R8000Rafał Miłecki2017-01-181-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Netgear R8000 is a tri-band home router. It has three BCM43602 chipsets two of them for 5 GHz band. Both seem the same and their firmwares report the same set of channels. The problem is due to hardware / board design there are extra limitations that should be respected. First PHY should be used for U-NII-2 and U-NII-3. Third PHY should be used for U-NII-1. Using them in a different way may result in wireless not working or in noticeably reduced performance. Basic version of this info was provided by Broadcom employee, then it has been verified by me using original vendor firmware (which has limitations hardcoded in UI). This patch uses recently introduced ieee80211-freq-limit property to describe these limitations at DT level. Referencing PCIe devices in DT required specifying all related bridges. Below you can see (a bit complex) PCI tree from R8000 that explains all entries that I needed to put in DT. 0000:00:00.0 14e4:8012 Bridge Device └─ 0000:01:00.0 14e4:aa52 Network Controller 0001:00:00.0 14e4:8012 Bridge Device └─ 0001:01:00.0 10b5:8603 Bridge Device ├─ 0001:02:01.0 10b5:8603 Bridge Device │ └─ 0001:03:00.0 14e4:aa52 Network Controller ├─ 0001:02:02.0 10b5:8603 Bridge Device │ └─ 0001:04:00.0 14e4:aa52 Network Controller ├─ 0001:02:03.0 000d:0000 0x000000 ├─ 0001:02:04.0 000d:0000 0x000000 ├─ 0001:02:05.0 000d:0000 0x000000 ├─ 0001:02:06.0 000d:0000 0x000000 ├─ (...) ├─ 0001:02:1d.0 000d:0000 0x000000 ├─ 0001:02:1e.0 000d:0000 0x000000 └─ 0001:02:1f.0 000d:0000 0x000000 Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: Specify USB controllers in DTRafał Miłecki2017-01-181-1/+32
| | | | | | | | | There are 3 separated controllers, one per USB /standard/. With PHY drivers in place they can be simply supported with generic drivers. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: BCM5301X: Specify USB 3.0 PHY in DTRafał Miłecki2016-10-191-0/+7
| | | | | | | | | | Driver for Northstar USB 3.0 PHY has been recently added under the name phy-bcm-ns-usb3. Add binding for it into the DT files. The only slightly tricky part is BCM47094 which uses different PHY version and requires different compatible value. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: BCM5301X: Specify PHY of USB 2.0 in DTRafał Miłecki2016-08-081-0/+11
| | | | | | | | | | Driver for Northstar USB 2.0 PHY was added in 4.7-rc1 by: commit d3feb4067335 ("phy: bcm-ns-usb2: new driver for USB 2.0 PHY on Northstar"). It should be used to let EHCI platform driver init PHY. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301x: Add RNG Device Tree nodeFlorian Fainelli2016-06-271-0/+5
| | | | | | | Add the DT node for the random number generator peripheral. Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: BCM5301X: Add SRAB interruptsFlorian Fainelli2016-06-131-0/+15
| | | | | | | | Add interrupt mapping for the Switch Register Access Block. Only 12 interrupts are usable at the moment even though up to 32 are dedicated to the SRAB. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: Enable SRAB switch and GMACs on 5301x DTSFlorian Fainelli2016-06-131-0/+27
| | | | | | | | | | | | | | Add the Switch Register Access Block which is a special piece of hardware allowing us to perform indirect read/writes towards the integrated BCM5301X Ethernet switch. We also add the 4 Gigabit MAC Device Tree nodes within the brcm,bus-axi bus node to get proper binding between the BCMA instantiated core and the Device Tree nodes. We will need that to be able to reference Ethernet Device Tree nodes in a future patch adding the switch ports layout. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: BCM5301X: Add DT entry for SPI controller and NOR flashRafał Miłecki2016-04-221-0/+14
| | | | | | | | Controller is present on every BCM4708* board but only few devices have serial flash attached so mark it as disabled by default. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: BCM5301X: Enable earlycon on tested devicesRafał Miłecki2016-04-131-0/+4
| | | | | | | | | This allows reporting & debugging problems occurring early in the boot process. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: BCM5301X: Set vcc-gpio for USB controllers of few devicesRafał Miłecki2016-04-131-0/+14
| | | | | | | | | There are few devices that have USB power controlled using GPIO. Linux USB host driver (bcma-hcd) already supports this by reading vcc-gpio from DT. Set it properly for all known devices. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: dts: enable clock support for BCM5301XJon Mason2015-11-201-21/+71
| | | | | | | | | Replace current device tree dummy clocks with real clock support for Broadcom Northstar SoCs. Signed-off-by: Jon Mason <jonmason@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: BCM5301X: Add profiling supportFelix Fietkau2015-08-111-0/+7
| | | | | | | Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: BCM5301X: activate some additional options in pl310 cache controllerHauke Mehrtens2015-08-111-0/+3
| | | | | | | | | | | | In the default Broadcom SDK the shared override is activated for this cache controller, do the same in the upstream code. Data and instruction prefetching is not activated by default for this cache controller on the bcm53xx SoC, do it manually like it is done in the vendor SDK. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: BCM5301X: add IRQ numbers for PCIe controllerHauke Mehrtens2015-06-061-0/+24
| | | | | | | | | The driver for the PCIe controller was just added, this adds the missing definition of the IRQ numbers to device tree. The driver itself will be automatically detected by bcma. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: BCM5301X: add NAND flash chip descriptionHauke Mehrtens2015-06-061-0/+12
| | | | | | | | | This adds the NAND flash chip description for a standard chip found connected to this SoC. This makes use of generic Broadcom NAND driver with the iProc interface. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: BCM5301X: Add buttons for Netgear R6250Rafał Miłecki2014-12-041-0/+1
| | | | | Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* ARM: BCM5301X: Add IRQs to Broadcom's bus-axi in DTS fileHauke Mehrtens2014-12-011-0/+34
| | | | | | | | | IRQ support for Broadcom's bus-axi driver bcma was merged into John Linville's wireless tree and will show up in 3.19. This patch makes use of this feature in the DTS file for the the BCM5301X SoCs. I left the PCIe controller out, because this still needs some discussion. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* ARM: BCM5301X: Add Broadcom's bus-axi to the DTS fileRafał Miłecki2014-11-271-0/+16
| | | | | | | | | This has been successfully tested on Netgear R6250 and two other development (unnamed) devices, all of them BCM4708 based. We also got a possitive feedback from R7000 (BCM4709) tester. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
* ARM: BCM5301X: add dts files for BCM4708 SoCHauke Mehrtens2014-02-191-0/+95
This uses the newly added BCM5301X SoC code. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Matt Porter <mporter@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-21 19:04:56 +0000