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* ARM: at91: pm: Add of_node_put() before gotoWan Jiabing2021-12-081-0/+2
| | | | | | | | | | | | | Fix following coccicheck warning: ./arch/arm/mach-at91/pm.c:643:1-33: WARNING: Function for_each_matching_node_and_match should have of_node_put() before goto Early exits from for_each_matching_node_and_match should decrement the node reference counter. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211014084555.21422-1-wanjiabing@vivo.com
* Merge tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2021-11-031-0/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC updates from Arnd Bergmann: "The SoC updates this time are mainly removing obsolete code from the OMAP2 platform, another step in the eternal cleanup of that platform. There are two new SoCs getting added: STMicroelectronics stm32mp13 and Microchip lan966. Both fit into existing platforms and require minimal changes here. A couple of MAINTAINER file updates relate to those changes, and update some file paths" * tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (28 commits) MAINTAINERS: Update BCM7XXX entry with additional patterns MAINTAINERS: add pinctrl-apple-gpio to ARM/APPLE MACHINE MAINTAINERS: Add pasemi i2c to ARM/APPLE MACHINE ARM: SPEAr: Update MAINTAINERS entries ARM: OMAP2+: Drop unused CM defines for am3 ARM: OMAP2+: Drop unused CM and SCRM defines for omap4 ARM: OMAP2+: Drop unused CM and SCRM defines for omap5 ARM: OMAP2+: Drop unused CM defines for dra7 ARM: OMAP2+: Drop unused PRM defines for am3 ARM: OMAP2+: Drop unused PRM defines for am4 ARM: OMAP2+: Drop unused PRM defines for omap4 ARM: OMAP2+: Drop unused PRM defines for omap5 ARM: OMAP2+: Drop unused PRM defines for dra7 ARM: OMAP2+: Fix comment typo ARM: OMAP2+: Fix typo in some comments ARM: at91: add basic support for new SoC family lan966 dt-bindings: arm: at91: Document lan966 pcb8291 and pcb8290 boards ARM: at91: Documentation: add lan966 family ARM: at91: Documentation: add sama7g5 family MAINTAINERS: add an entry for NXP S32G boards ...
| * ARM: at91: add basic support for new SoC family lan966Kavyasree Kotagiri2021-10-041-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces Microchip LAN966 ARMv7 based SoC family of multiport gigabit AVB/TSN-capable ethernet switches. It supports two SKUs: 4-port LAN9662 with multiprotocol processing support and 8-port LAN9668 switch. LAN966 family includes copper and serial ethernet interfaces, peripheral interfaces such as PCIe, USB, TWI, SPI, UART, QSPI, SD/eMMC, Parallel Interface (PI) as well as synchronization and trigger inputs/outputs. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [nicolas.ferre@microchip.com: merged patches for this SoC introduction] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210831102138.2476-1-kavyasree.kotagiri@microchip.com Link: https://lore.kernel.org/r/20211004105926.5696-5-kavyasree.kotagiri@microchip.com
* | ARM: at91: pm: preload base address of controllers in tlbClaudiu Beznea2021-10-041-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In suspend/resume procedure for AT91 architecture different controllers (PMC, SHDWC, RAM, RAM PHY, SFRBU) are accessed to do the proper settings for power saving. Commit f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") introduced the access to RAMC PHY controller for SAMA7G5. The access to this controller is done after RAMC ports are closed, thus any TLB walk necessary for RAMC PHY virtual address will fail. In the development branch this was not encountered. However, on current kernel the issue is reproducible. To solve the issue the previous mechanism of pre-loading the TLB with the RAMC PHY virtual address has been used. However, only the addition of this new pre-load breaks the functionality for ARMv5 based devices (SAM9X60). This behavior has been encountered previously while debugging this code and using the same mechanism for pre-loading address for different controllers (e.g. pin controller, the assumption being that other requested translations are replaced from TLB). To solve this new issue the TLB flush + the extension of pre-loading the rest of controllers to TLB (e.g. PMC, RAMC) has been added. The rest of the controllers should have been pre-loaded previously, anyway. Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5") Depends-on: e42cbbe5c9a2 ("ARM: at91: pm: group constants and addresses loading") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210930154219.2214051-4-claudiu.beznea@microchip.com
* | ARM: at91: pm: group constants and addresses loadingClaudiu Beznea2021-10-041-8/+9
| | | | | | | | | | | | | | | | | | Group constants and addresses loading. This commit prepares the field for the next one. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210930154219.2214051-3-claudiu.beznea@microchip.com
* | ARM: at91: pm: switch backup area to vbat in backup modeClaudiu Beznea2021-09-141-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | Backup area is now switched to VDDIN33 at boot (with the help of bootloader). When switching to backup mode we need to switch backup area to VBAT as all the other power sources are cut off. The resuming from backup mode is done with the help of bootloader, so there is no need to do something particular in Linux to restore backup area power source. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210830100927.22711-1-claudiu.beznea@microchip.com
* | ARM: at91: pm: do not panic if ram controllers are not enabledClaudiu Beznea2021-09-141-16/+62
|/ | | | | | | | | | | | | | In case PM is enabled but there is no RAM controller information in DT the code will panic. Avoid such scenarios by not initializing platform specific PM code in case RAM controller is not provided via DT. Reported-by: Eugen Hristev <eugen.hristev@microchip.com> Fixes: 827de1f123ba0 ("ARM: at91: remove at91_dt_initialize and machine init_early()") Fixes: 892e1f4a3ae58 ("ARM: at91: pm: add sama7g5 ddr phy controller") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210823131915.23857-2-claudiu.beznea@microchip.com
* ARM: at91: pm: add sama7g5 shdwcClaudiu Beznea2021-07-191-0/+1
| | | | | | | | Add SAMA7G5 SHDWC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-25-claudiu.beznea@microchip.com
* ARM: at91: pm: add pm support for SAMA7G5Claudiu Beznea2021-07-193-0/+40
| | | | | | | | Add support for SAMA7G5 power management modes: standby, ulp0, ulp1, backup. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-24-claudiu.beznea@microchip.com
* ARM: at91: sama7: introduce sama7 SoC familyEugen Hristev2021-07-192-0/+33
| | | | | | | | | | Introduce new family of SoCs, sama7, and first SoC, sama7g5. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea@microchip.com: keep only the sama7_dt] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-23-claudiu.beznea@microchip.com
* ARM: at91: pm: add sama7g5's pmcClaudiu Beznea2021-07-191-0/+6
| | | | | | | | Add SAMA7G5's PMC to compatible list. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-22-claudiu.beznea@microchip.com
* ARM: at91: pm: add backup mode support for SAMA7G5Claudiu Beznea2021-07-192-1/+9
| | | | | | | | | | Adapt at91_pm_backup_init() to work for SAMA7G5. Also, set the LPM pin to shutdown controller. This will signal to PMIC that it needs to switch to the state corresponding to backup mode. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-21-claudiu.beznea@microchip.com
* ARM: at91: pm: save ddr phy calibration data to securamClaudiu Beznea2021-07-191-1/+59
| | | | | | | | | | | | | | | | The resuming from backup mode is done with the help of bootloader. The bootloader reconfigure the DDR controller and DDR PHY controller. To speed-up the resuming process save the PHY calibration data into SECURAM before suspending (securam is powered on backup mode). This data will be later used by bootloader in DDR PHY reconfiguration process. Also, in the process or recalibration the first 8 words of the memory may get corrupted. To solve this, these 8 words are saved in the securam and restored by bootloader in the process of PHY configuration. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-20-claudiu.beznea@microchip.com
* ARM: at91: pm: add sama7g5 ddr phy controllerClaudiu Beznea2021-07-191-6/+21
| | | | | | | | | | SAMA7G5 self-refresh procedure accesses also the DDR PHY registers. Adapt the code so that the at91_dt_ramc() to look also for DDR PHYs, in case it is mandatory. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-19-claudiu.beznea@microchip.com
* ARM: at91: pm: add sama7g5 ddr controllerClaudiu Beznea2021-07-191-3/+6
| | | | | | | | | Add SAMA7G5 DDR controller to the list of DDR controller compatibles. At the moment there is no standby support. Adapt the code for this. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com
* ARM: at91: pm: wait for ddr power mode offClaudiu Beznea2021-07-191-0/+5
| | | | | | | | Wait for DDR power mode off before shutting down the core. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-16-claudiu.beznea@microchip.com
* ARM: at91: pm: add support for 2.5V LDO regulator controlClaudiu Beznea2021-07-192-0/+30
| | | | | | | | | Add support to disable/enable 2.5V LDO regulator when entering/exiting any ULP mode. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-15-claudiu.beznea@microchip.com
* ARM: at91: pm: add support for MCK1..4 save/restore for ulp modesClaudiu Beznea2021-07-191-0/+126
| | | | | | | | Add support for MCK1..4 save restore for ULP modes. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-14-claudiu.beznea@microchip.com
* ARM: at91: pm: add self-refresh support for sama7g5Claudiu Beznea2021-07-193-0/+203
| | | | | | | | Add self-refresh support for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-13-claudiu.beznea@microchip.com
* ARM: at91: pm: add support for waiting MCK1..4Claudiu Beznea2021-07-191-13/+35
| | | | | | | | | | SAMA7G5 has 5 master clocks 0..4. MCK0 is controlled differently than MCK 1..4. MCK 1..4 should also be saved/restored in the last phase of suspend/resume. Thus, adapt wait_mckrdy to support also MCK1..4. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-10-claudiu.beznea@microchip.com
* ARM: at91: pm: s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/gClaudiu Beznea2021-07-191-2/+2
| | | | | | | | | Replace CONFIG_SOC_SAM9X60 with CONFIG_HAVE_AT91_SAM9X60_PLL as the SAM9X60's PLL is also present on SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-9-claudiu.beznea@microchip.com
* ARM: at91: pm: avoid push and pop on stack while memory is in self-refershClaudiu Beznea2021-07-191-192/+205
| | | | | | | | | | | | For the previous AT91 RAM controller and self-refresh procedure this had no side effects. However, for SAMA7G5 the self-refresh procedure doesn't allow this anymore as the RAM controller ports are closed before switching it to self-refresh. This commits prepares the code for the following ones adding self-refresh and PM support for SAMA7G5. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-8-claudiu.beznea@microchip.com
* ARM: at91: pm: use r7 instead of tmp1Claudiu Beznea2021-07-191-6/+12
| | | | | | | | | Use r7 instead of tmp1 in macros. This prepares the filed for next commits. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-7-claudiu.beznea@microchip.com
* ARM: at91: pm: do not initialize pdevClaudiu Beznea2021-07-191-1/+1
| | | | | | | | There is no need to initialize pdev. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-6-claudiu.beznea@microchip.com
* ARM: at91: pm: check for different controllers in at91_pm_modes_init()Claudiu Beznea2021-07-191-52/+91
| | | | | | | | | | | | | at91_pm_modes_init() checks for proper nodes in device tree and maps them accordingly. Up to SAMA7G5 all AT91 SoCs had the same mapping b/w power saving modes and different controllers needed in the final/first steps of suspend/resume. SAMA7G5 is not aligned with the old SoCs thus the code is adapted for this. This patch prepares the field for next commits. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-5-claudiu.beznea@microchip.com
* ARM: at91: pm: document at91_soc_pm structureClaudiu Beznea2021-07-191-0/+8
| | | | | | | | Document at91_soc_pm structure. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-4-claudiu.beznea@microchip.com
* ARM: at91: pm: move the setup of soc_pm.bu->suspendedClaudiu Beznea2021-07-191-3/+12
| | | | | | | | | | | Move the setup of soc_pm.bu->suspended in platform_suspend::begin function so that the PMC code in charge with clocks suspend/resume to differentiate b/w standard PM mode and backup mode. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-3-claudiu.beznea@microchip.com
* ARM: at91: pm: move pm_bu to soc_pm data structureClaudiu Beznea2021-07-191-13/+21
| | | | | | | | Move pm_bu to soc_pm data structure. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210415105010.569620-2-claudiu.beznea@microchip.com
* ARM: at91: add new SoC sama7g5Eugen Hristev2021-07-191-0/+18
| | | | | | | | | | | Add new SoC from at91 family : sama7g5 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea@microchip.com: Select PLL, generic clock and UTMI support, add PM configs] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210409113116.482199-1-eugen.hristev@microchip.com Link: https://lore.kernel.org/r/20210719080317.1045832-2-claudiu.beznea@microchip.com
* ARM: at91: pm: Move prototypes to mutually included headerLee Jones2021-03-261-11/+8
| | | | | | | | | | | | | | | | | | | | | | | Both the caller and the supplier's source file should have access to the include file containing the prototypes. Fixes the following W=1 kernel build warning(s): drivers/pinctrl/pinctrl-at91.c:1637:6: warning: no previous prototype for ‘at91_pinctrl_gpio_suspend’ [-Wmissing-prototypes] 1637 | void at91_pinctrl_gpio_suspend(void) | ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/pinctrl/pinctrl-at91.c:1661:6: warning: no previous prototype for ‘at91_pinctrl_gpio_resume’ [-Wmissing-prototypes] 1661 | void at91_pinctrl_gpio_resume(void) | ^~~~~~~~~~~~~~~~~~~~~~~~ Cc: Russell King <linux@armlinux.org.uk> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20210303124149.3149511-1-lee.jones@linaro.org
* ARM: at91: use proper asm syntax in pm_suspendArnd Bergmann2021-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | Compiling with the clang integrated assembler warns about a recently added instruction: <instantiation>:14:13: error: unknown token in expression ldr tmp1, =#0x00020010UL arch/arm/mach-at91/pm_suspend.S:542:2: note: while in macro instantiation at91_plla_enable Remove the extra '#' character that is not used for the 'ldr' instruction when doing an indirect load of a constant. Fixes: 4fd36e458392 ("ARM: at91: pm: add plla disable/enable support for sam9x60") Tested-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20210204160129.2249394-1-arnd@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: at91: pm: remove unnecessary at91sam9x60_idleAlexandre Belloni2020-08-171-6/+1
| | | | | | | | | cpu_do_idle() is already the default action for arm_pm_idle, there is no need to open code it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20200804115622.63232-1-alexandre.belloni@bootlin.com
* ARM: at91: pm: of_node_put() after its usageClaudiu Beznea2020-08-171-0/+1
| | | | | | | | | Put node after it has been used. Fixes: 13f16017d3e3f ("ARM: at91: pm: Tie the USB clock mask to the pmc") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1596616610-15460-4-git-send-email-claudiu.beznea@microchip.com
* ARM: at91: pm: add per soc validation of pm modesClaudiu Beznea2020-08-171-1/+79
| | | | | | | | | | | Not all SoCs supports all the PM mode. User may end up settings, e.g. backup mode, on a non SAMA5D2 device, but the mode to not be valid. If backup mode is used on a devices not supporting it there will be no way of resuming other than rebooting. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1596616610-15460-3-git-send-email-claudiu.beznea@microchip.com
* ARM: at91: pm: add support for ULP0 fast wakeupClaudiu Beznea2020-08-173-10/+45
| | | | | | | | | | | | | | | | | ULP0 fast improves suspend/resume time with few milliseconds the drawback being the power consumption. The mean values measured for suspend/resume time are as follows (measured on SAMA5D2 Xplained board), ULP0 compared with fast ULP0: - ulp0 fast: suspend time: 169 ms, resume time: 216 ms - ulp0 : suspend time: 197 ms, resume time: 258 ms Current consumption while suspended (measured on SAMA5D2 Xplained board): - ulp0 fast: 730uA - ulp0 : 270uA Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1596616610-15460-2-git-send-email-claudiu.beznea@microchip.com
* ARM: at91: Replace HTTP links with HTTPS onesAlexander A. Klimov2020-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200713065859.31770-1-grandmaster@al2klimov.de
* ARM: at91: pm: add missing put_device() call in at91_pm_sram_init()yu kuai2020-07-181-3/+8
| | | | | | | | | | | if of_find_device_by_node() succeed, at91_pm_sram_init() doesn't have a corresponding put_device(). Thus add a jump target to fix the exception handling for this function implementation. Fixes: d2e467905596 ("ARM: at91: pm: use the mmio-sram pool to access SRAM") Signed-off-by: yu kuai <yukuai3@huawei.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200604123301.3905837-1-yukuai3@huawei.com
* Merge tag 'arm-soc-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2020-04-035-21/+210
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM SoC updates from Arnd Bergmann: "The code changes are mostly for 32-bit platforms and include: - Lots of updates for the Nvidia Tegra platform, including cpuidle, pmc, and dt-binding changes - Microchip at91 power management updates for the recently added sam9x60 SoC - Treewide setup_irq deprecation by afzal mohammed - STMicroelectronics stm32 gains earlycon support - Renesas platforms with Cortex-A9 can now use the global timer - Some TI OMAP2+ platforms gain cpuidle support - Various cleanups for the i.MX6 and Orion platforms, as well as Kconfig files across all platforms" * tag 'arm-soc-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (75 commits) ARM: qcom: Add support for IPQ40xx ARM: mmp: replace setup_irq() by request_irq() ARM: cns3xxx: replace setup_irq() by request_irq() ARM: spear: replace setup_irq() by request_irq() ARM: ep93xx: Replace setup_irq() by request_irq() ARM: iop32x: replace setup_irq() by request_irq() arm: mach-dove: Mark dove_io_desc as __maybe_unused ARM: orion: replace setup_irq() by request_irq() ARM: debug: stm32: add UART early console support for STM32MP1 ARM: debug: stm32: add UART early console support for STM32H7 ARM: debug: stm32: add UART early console configuration for STM32F7 ARM: debug: stm32: add UART early console configuration for STM32F4 cpuidle: tegra: Disable CC6 state if LP2 unavailable cpuidle: tegra: Squash Tegra114 driver into the common driver cpuidle: tegra: Squash Tegra30 driver into the common driver cpuidle: Refactor and move out NVIDIA Tegra20 driver into drivers/cpuidle ARM: tegra: cpuidle: Remove unnecessary memory barrier ARM: tegra: cpuidle: Make abort_flag atomic ARM: tegra: cpuidle: Handle case where secondary CPU hangs on entering LP2 ARM: tegra: Make outer_disable() open-coded ...
| * ARM: at91: pm: add quirk for sam9x60's ulp1Claudiu Beznea2020-02-181-0/+4
| | | | | | | | | | | | | | | | | | On SAM9X60 2 nop operations has to be introduced after setting WAITMODE bit in CKGR_MOR. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-9-git-send-email-claudiu.beznea@microchip.com
| * ARM: at91: pm: add plla disable/enable support for sam9x60Claudiu Beznea2020-02-181-4/+113
| | | | | | | | | | | | | | | | Add PLLA enable/disable support for SAM9X60. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-8-git-send-email-claudiu.beznea@microchip.com
| * ARM: at91: pm: s/sfr/sfrbu in pm_suspend.SClaudiu Beznea2020-02-181-3/+3
| | | | | | | | | | | | | | | | s/sfr/sfrbu in pm_suspend.S. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-6-git-send-email-claudiu.beznea@microchip.com
| * ARM: at91: pm: add pmc_version member to at91_pm_dataClaudiu Beznea2020-02-184-0/+14
| | | | | | | | | | | | | | | | | | | | | | This will be used to differentiate b/w different PLLs settings to be applied in the final/first steps of the suspend/resume process by doing PLL specific configurations. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-5-git-send-email-claudiu.beznea@microchip.com
| * ARM: at91: pm: add macros for plla disable/enableClaudiu Beznea2020-02-181-27/+30
| | | | | | | | | | | | | | | | | | | | Add macros for PLLA disable and enable (in disable macro the PLLA state will also be saved). This prepares the field for PLLA disable/enable for suspend/resume on SAM9X60. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-4-git-send-email-claudiu.beznea@microchip.com
| * ARM: at91: pm: revert do not disable/enable PLLA for ULP modesClaudiu Beznea2020-02-181-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2725d70aa5138284ba2cebf0ef51dd23e0c9ea21 ("ARM: at91: pm: do not disable/enable PLLA for ULP modes"). This is because PLLA is the clock source for CPU, PLLA should be disabled/enabled in the final/first phase of suspend/resume so that the power consumption in suspend/resume to be minimal and suspend/resume time to be minimized. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-3-git-send-email-claudiu.beznea@microchip.com
| * ARM: at91: pm: use proper master clock register offsetClaudiu Beznea2020-02-184-17/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SAM9X60's PMC has different master clock register offset than the other SoCs' PMC. Due to this, specify master clock register offset based on PMC compatible and pass it to pm_suspend.S since it is also needed in there. When PM part for SAM9X60 was published the SAM9X60's PMC (commit f6deae46039c ("clk: at91: add sam9x60 pmc driver")) wasn't integrated. Fixes: 01c7031cfa73 ("ARM: at91: pm: initial PM support for SAM9X60") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-2-git-send-email-claudiu.beznea@microchip.com
| * ARM: at91: Drop unneeded select of COMMON_CLKGeert Uytterhoeven2020-02-101-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Support for AT91/Microchip SoCs depends on ARCH_MULTIPLATFORM or ARM_SINGLE_ARMV7M, which both select COMMON_CLK. Hence there is no need for COMMON_CLK_AT91 to select COMMON_CLK. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20200121103722.1781-5-geert+renesas@glider.be Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* | .gitignore: add SPDX License IdentifierMasahiro Yamada2020-03-251-0/+1
|/ | | | | | | Add SPDX License Identifier to all .gitignore files. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: at91: pm: use of_device_id array to find the proper shdwc nodeClaudiu Beznea2020-01-101-1/+7
| | | | | | | | | | | | Use of_device_id array to find the proper shdwc compatibile node. SAM9X60's shdwc changes were not integrated when commit eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60") was integrated. Fixes: eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1576062248-18514-3-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: at91: pm: use SAM9X60 PMC's compatibleClaudiu Beznea2020-01-101-0/+1
| | | | | | | | | | | SAM9X60 PMC's has a different PMC. It was not integrated at the moment commit 01c7031cfa73 ("ARM: at91: pm: initial PM support for SAM9X60") was published. Fixes: 01c7031cfa73 ("ARM: at91: pm: initial PM support for SAM9X60") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1576062248-18514-2-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
* ARM: at91: pm: move SAM9X60's PM under its own SoC config flagClaudiu Beznea2019-12-104-19/+36
| | | | | | | | | | Move SAM9X60's PM part under SoC config flag. This allows the building of SAM9X60 platform withouth depending on CONFIG_SOC_AT91SAM9 flag, allowing us to select only necessary config flags for SAM9X60. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-4-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-27 18:36:48 +0000