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* | ARM: BCM: Clean up SMP support for Broadcom KonaKapil Hali2015-12-071-28/+54
| | | | | | | | | | | | | | | | | | | | These changes cleans up SMP implementaion for Broadcom's Kona SoC which are required for handling SMP for iProc family of SoCs at a single place for BCM NSP and BCM Kona. Signed-off-by: Kapil Hali <kapilh@broadcom.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | ARM: BCM5310X: activate erratas needed for SoCHauke Mehrtens2015-11-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The BCM4708 I have, which is probably the first generation which got to the consumer market, is using a ARM Cortex-A9 rev r3p0 and a L2C-310 rev r3p2 L2 cache controller. There are 3 workarounds for known erratas in the Linux kernel which could be activated and will be in this patch. There are currently no workarounds which have to be activated for the L2C-310 rev r3p2 in Linux. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | ARM: BCM5301X: remove workaround imprecise abort fault handlerLucas Stach2015-11-241-35/+0
|/ | | | | | | | | | | This is not needed anymore. Handling a potentially pending imprecise external abort left behind by the bootloader is now done in a slightly safer way inside the common ARM startup code. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Tested-by: Tyler Baker <tyler.baker@linaro.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* Merge tag 'armsoc-soc' of ↵Linus Torvalds2015-11-104-1/+53
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "New and/or improved SoC support for this release: Marvell Berlin: - Enable standard DT-based cpufreq - Add CPU hotplug support Freescale: - Ethernet init for i.MX7D - Suspend/resume support for i.MX6UL Allwinner: - Support for R8 chipset (used on NTC's $9 C.H.I.P board) Mediatek: - SMP support for some platforms Uniphier: - L2 support - Cleaned up SMP support, etc. plus a handful of other patches around above functionality, and a few other smaller changes" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits) ARM: uniphier: rework SMP operations to use trampoline code ARM: uniphier: add outer cache support Documentation: EXYNOS: Update bootloader interface on exynos542x ARM: mvebu: add broken-idle option ARM: orion5x: use mac_pton() helper ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte aligned ARM: sunxi: Add R8 support ARM: digicolor: select pinctrl/gpio driver arm: berlin: add CPU hotplug support arm: berlin: use non-self-cleared reset register to reset cpu ARM: mediatek: add smp bringup code ARM: mediatek: enable gpt6 on boot up to make arch timer working soc: mediatek: Fix random hang up issue while kernel init soc: ti: qmss: make acc queue support optional in the driver soc: ti: add firmware file name as part of the driver Documentation: dt: soc: Add description for knav qmss driver ARM: S3C64XX: Use PWM lookup table for mach-smartq ARM: S3C64XX: Use PWM lookup table for mach-hmt ARM: S3C64XX: Use PWM lookup table for mach-crag6410 ARM: S3C64XX: Use PWM lookup table for smdk6410 ...
| * ARM: brcmstb: Setup BIU control registers during bootFlorian Fainelli2015-10-091-0/+9
| | | | | | | | | | | | | | | | | | Call brcmstb_biuctrl_init() in brcmstb's init_irq machine descriptor callback since we need to setup the Bus Interface Unit before SMP in particular, but we also need to be able to remap registers. Acked-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * soc: add stubs for brcmstb SoC'sBrian Norris2015-09-141-0/+1
| | | | | | | | | | | | | | Used on BCM7xxx Set-Top Box chips (e.g., BCM7445). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * ARM: NSP: Add basic support for Broadcom Northstar Plus SoCJon Mason2015-09-143-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Broadcom Northstar Plus family of SoCs are used for switching control and management applications as well as residential router/gateway applications. The SoC features dual core Cortex A9 ARM CPUs, integrating several peripheral interfaces including multiple Gigabit Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash, SATA and several other IO controllers. Signed-off-by: Kapil Hali <kapilh@broadcom.com> Signed-off-by: Jon Mason <jonmason@broadcom.com> Acked-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabledArnd Bergmann2015-10-211-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_CYGNUS is set but CONFIG_COMMON_CLK_IPROC is disabled, the following link failures are caused: drivers/built-in.o: In function `cygnus_armpll_init': :(.init.text+0x1d290): undefined reference to `iproc_armpll_setup' drivers/built-in.o: In function `cygnus_genpll_clk_init': :(.init.text+0x1d2c4): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_lcpll0_clk_init': :(.init.text+0x1d304): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_mipipll_clk_init': :(.init.text+0x1d344): undefined reference to `iproc_pll_clk_setup' drivers/built-in.o: In function `cygnus_asiu_init': :(.init.text+0x1d370): undefined reference to `iproc_asiu_setup' It is fixed it by always selecting COMMON_CLK_IPROC from ARCH_BCM_IPROC, and making COMMON_CLK_IPROC a silent option (thus preventing it from being erroneously disabled by a user). Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'armsoc-soc' of ↵Linus Torvalds2015-09-011-0/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "New or improved SoC support: - add support for Atmel's SAMA5D2 SoC - add support for Freescale i.MX6UL - improved support for TI's DM814x platform - misc fixes and improvements for RockChip platforms - Marvell MVEBU suspend/resume support A few driver changes that ideally would belong in the drivers branch are also here (acked by appropriate maintainers): - power key input driver for Freescale platforms (svns) - RTC driver updates for Freescale platforms (svns/mxc) - clk fixes for TI DM814/816X + a bunch of other changes for various platforms" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: rockchip: pm: Fix PTR_ERR() argument ARM: imx: mach-imx6ul: Fix allmodconfig build clk: ti: fix for definition movement ARM: uniphier: drop v7_invalidate_l1 call at secondary entry memory: kill off set_irq_flags usage rtc: snvs: select option REGMAP_MMIO ARM: brcmstb: select ARCH_DMA_ADDR_T_64BIT for LPAE ARM: BCM: Enable ARM erratum 798181 for BRCMSTB ARM: OMAP2+: Fix power domain operations regression caused by 81xx ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend ARM: rockchip: set correct stabilization thresholds in suspend ARM: rockchip: rename osc_switch_to_32k variable ARM: imx6ul: add fec MAC refrence clock and phy fixup init ARM: imx6ul: add fec bits to GPR syscon definition rtc: mxc: add support of device tree dt-binding: document the binding for mxc rtc rtc: mxc: use a second rtc clock ARM: davinci: cp_intc: use IRQCHIP_SKIP_SET_WAKE instead of irq_set_wake callback soc: mediatek: Fix SCPSYS compilation ARM: at91/soc: add basic support for new sama5d2 SoC ...
| * ARM: brcmstb: select ARCH_DMA_ADDR_T_64BIT for LPAEGregory Fong2015-08-111-0/+1
| | | | | | | | | | | | | | | | | | | | Broadcom STB (BRCMSTB) has some 64-bit capable DMA and therefore needs dma_addr_t to be a 64-bit size. One user is the Broadcom SATA3 AHCI controller driver. Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: BCM: Enable ARM erratum 798181 for BRCMSTBGregory Fong2015-08-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | Commit 04fcab32d3fa1d3f6afe97e0ab431c5572e07a2c ("ARM: 8111/1: Enable erratum 798181 for Broadcom Brahma-B15") enables this erratum for affected Broadcom Brahma-B15 CPUs when CONFIG_ARM_ERRATA_798181=y. Let's make sure that config option is actually set. Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | ARM: appropriate __init annotation for const dataNicolas Pitre2015-07-282-2/+2
| | | | | | | | | | | | | | | | | | | | Init data marked const should be annotated with __initconst for correctness and not __initdata. In some cases the array gathering references to that data has to be marked const as well. This fixes LTO builds that otherwise fail with section mismatch errors. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* | ARM: BCM63xx: Remove custom secondary_startup functionFlorian Fainelli2015-07-114-28/+2
| | | | | | | | | | | | | | | | | | | | | | | | With commit 02b4e2756e01c623cc4dbceae4b07be75252db5b ("ARM: v7 setup function should invalidate L1 cache"), the default secondary_startup function for ARMv7 CPUs does invalidate the L1 cache, which was the sole reason why BCM63xx had to have its own secondary_startup implementation. Now that the secondary_startup takes care of this, we can completely remove that code. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | ARM: BCM63xx: fix parameter to of_get_cpu_node in bcm63138_smp_boot_secondarySudeep Holla2015-07-111-1/+1
|/ | | | | | | | | | | | | | | | of_get_cpu_node provides the device node associated with the given logical CPU and cpu_logical_map contains the physical id for each CPU in the logical ordering. Passing cpu_logical_map(cpu) to of_get_cpu_node is incorrect. This patch fixes the issue by passing the logical CPU number to of_get_cpu_node Fixes: ed5cd8163da8 ("ARM: BCM63xx: Add SMP support for BCM63138") Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: BCM: Do not select CONFIG_MTD_NAND_BRCMNANDFlorian Fainelli2015-07-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | This reverts 7dc95b40f599293aedf30432749ad25b51549041 ("ARM: BCM: Enable NAND support for iProc SoCs") since it creates an unmet dependency for MTD_NAND_BRCMNAND which depends on MTD and MTD_NAND, this results in the following build failure for brcmnand: LD init/built-in.o drivers/built-in.o: In function `brcmnand_remove': /home/fainelli/dev/linux/drivers/mtd/nand/brcmnand/brcmnand.c:2234: undefined reference to `nand_release' drivers/built-in.o: In function `brcmnand_init_cs': /home/fainelli/dev/linux/drivers/mtd/nand/brcmnand/brcmnand.c:1933: undefined reference to `nand_scan_ident' /home/fainelli/dev/linux/drivers/mtd/nand/brcmnand/brcmnand.c:1958: undefined reference to `nand_scan_tail' Makefile:931: recipe for target 'vmlinux' failed make: *** [vmlinux] Error 1 Instead, select this driver an all dependencies on the multi_v7_defconfig. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
* Merge tag 'armsoc-soc' into test-mergeKevin Hilman2015-06-248-96/+435
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM: SoC: platform support for v4.2 Our SoC branch usually contains expanded support for new SoCs and other core platform code. Some highlights from this round: - sunxi: SMP support for A23 SoC - socpga: big-endian support - pxa: conversion to common clock framework - bcm: SMP support for BCM63138 - imx: support new I.MX7D SoC - zte: basic support for ZX296702 SoC Conflicts: arch/arm/mach-socfpga/core.h Trivial remove/remove conflict with our cleanup branch. Resolution: remove both sides # gpg: Signature made Wed Jun 24 21:32:12 2015 PDT using RSA key ID D3FBC665 # gpg: Good signature from "Kevin Hilman <khilman@deeprootsystems.com>" # gpg: aka "Kevin Hilman <khilman@linaro.org>" # gpg: aka "Kevin Hilman <khilman@kernel.org>" # Conflicts: # arch/arm/mach-socfpga/core.h
| * Merge tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux ↵Arnd Bergmann2015-06-012-1/+3
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/soc Merge "changes for Broadcom SoCs": - Dan fixes an error path in the BCM63xx SMP code - Ray adds the relevant Kconfig selects to enable the Broadcom NAND driver on Cygnus - Kevin provides a change to the Broadcom GISB arbiter driver to make it work with MIPS-based big-endian STB SoCs (this was a long-standing change that had dependencies on code in drivers/of/*) - Gregory enables the use of GPIOLIB for brcmstb SoCs and bumps the number of GPIOs for these platforms * tag 'arm-soc/for-4.2/soc-part2' of http://github.com/broadcom/stblinux: ARM: brcmstb: Add default gpio number ARM: brcmstb: Select ARCH_WANT_OPTIONAL_GPIOLIB bus: brcmstb_gisb: Honor the "big-endian" and "native-endian" DT properties ARM: BCM: Enable NAND support for iProc SoCs ARM: BCM63xx: fix an error path in bcm63xx_pmb_power_on_cpu()
| | * ARM: brcmstb: Select ARCH_WANT_OPTIONAL_GPIOLIBGregory Fong2015-05-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Select ARCH_WANT_OPTIONAL_GPIOLIB from BRCMSTB to allow GPIOLIB and GPIO_BRCMSTB to be enabled. Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * ARM: BCM: Enable NAND support for iProc SoCsRay Jui2015-05-281-0/+1
| | | | | | | | | | | | | | | | | | | | | Select CONFIG_MTD_NAND_BRCMNAND for all iProc SoCs Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * ARM: BCM63xx: fix an error path in bcm63xx_pmb_power_on_cpu()Dan Carpenter2015-05-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | We need to unlock and unmap some resourses before returning. Fixes: 3f2a43c98d72 ('ARM: BCM63xx: Add secondary CPU PMB initialization sequence') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | Merge tag 'arm-soc/for-4.2/soc-take2' of http://github.com/broadcom/stblinux ↵Arnd Bergmann2015-05-226-5/+433
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/soc Merge mach-bcm changes from Florian Fainelli: This pull request contains the following changes: - Rafal adds an additional fault code to be ignored by the kernel on BCM5301X SoC - BCM63138 SMP support which: * common code to control the PMB bus, to be shared with a reset controller driver in drivers/reset * secondary CPU initialization sequence using PMB helpers * small changes suggested by Russell King to allow platforms to disable VFP * tag 'arm-soc/for-4.2/soc-take2' of http://github.com/broadcom/stblinux: ARM: BCM63xx: Add SMP support for BCM63138 ARM: vfp: Add vfp_disable for problematic platforms ARM: vfp: Add include guards ARM: BCM63xx: Add secondary CPU PMB initialization sequence ARM: BCM63xx: Add Broadcom BCM63xx PMB controller helpers ARM: BCM5301X: Ignore another (BCM4709 specific) fault code
| | * ARM: BCM63xx: Add SMP support for BCM63138Florian Fainelli2015-05-204-1/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for booting the secondary CPU on BCM63138, this involves: - locating the bootlut to write the reset vector - powering up the second CPU when we need to using the DT-supplied PMB references - disabling VFP when enabled such that we can keep having SMP Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * ARM: BCM63xx: Add secondary CPU PMB initialization sequenceFlorian Fainelli2015-05-201-0/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sequence to initialize a secondary CPU using the BCM63138 PMB is extremely specific and represents much more code than any other on-chip peripheral (AHCI, USB 3.0 or integrated Ethernet switch), as such we keep that code local and utilize Device Tree to lookup all the resources we need from the CPU device tree node. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * ARM: BCM5301X: Ignore another (BCM4709 specific) fault codeRafał Miłecki2015-05-201-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Broadcom ARM devices seem to generate some fault once per boot. We already have an ignoring handler for BCM4707/BCM4708, but BCM4709 generates different code. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | ARM: bcm2835: Move the restart/power_off handling to the WDT driverEric Anholt2015-05-141-73/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the WDT is what's used to drive restart and power off, it makes more sense to keep it there, where the regs are already mapped and definitions for them provided. Note that this means you may need to add CONFIG_BCM2835_WDT to retain functionality of your kernel. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Lee Jones <lee.jones@linaro.org>
| * | ARM: bcm2835: Drop the init_irq() hookEric Anholt2015-05-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is the default function that gets called if the hook is NULL. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
| * | ARM: bcm2835: Skip doing our own iotable_init() initializationEric Anholt2015-05-141-17/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | The only thing we were using this 16MB mapping of IO peripherals for was the uart's early debug mapping. If we just drop the map_io hook, the kernel will call debug_ll_io_init() for us, which maps the single page needed for the device. Signed-off-by: Eric Anholt <eric@anholt.net> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
* / ARM: v7 setup function should invalidate L1 cacheRussell King2015-06-014-56/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All ARMv5 and older CPUs invalidate their caches in the early assembly setup function, prior to enabling the MMU. This is because the L1 cache should not contain any data relevant to the execution of the kernel at this point; all data should have been flushed out to memory. This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, these typically do not search their caches when caching is disabled (as it needs to be when the MMU is disabled) so this change should be safe. ARMv7 allows there to be CPUs which search their caches while caching is disabled, and it's permitted that the cache is uninitialised at boot; for these, the architecture reference manual requires that an implementation specific code sequence is used immediately after reset to ensure that the cache is placed into a sane state. Such functionality is definitely outside the remit of the Linux kernel, and must be done by the SoC's firmware before _any_ CPU gets to the Linux kernel. Changing the data cache clean+invalidate to a mere invalidate allows us to get rid of a lot of platform specific hacks around this issue for their secondary CPU bringup paths - some of which were buggy. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: cygnus: fix const declaration bcm_cygnus_dt_compatStefan Agner2015-03-241-1/+1
| | | | | | | | | | | | | | | The const declaration for char* is actually duplicated, however the array of strings is currently not constant. However, typically the dt_compat array is declared as const char *const. Follow that convention and also add the __initconst macro for constant initialization data. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Scott Branden <sbranden@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Tested-by: Ray Jui <rjui@broadcom.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* ARM: make arrays containing machine compatible strings constUwe Kleine-König2015-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The definition static const char *axxia_dt_match[] __initconst = { ... defines a changable array of constant strings. That is you must not do: *axxia_dt_match[0] = 'k'; but axxia_dt_match[0] = "different string"; is fine. So the annotation __initconst is wrong and yields a compiler error when other really const variables are added with __initconst. As the struct machine_desc member dt_compat is declared as const char *const *dt_compat; making the arrays const is the better alternative over changing all annotations to __initdata. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: BCM: put back ARCH_MULTI_V7 dependency for mobileArnd Bergmann2015-02-181-2/+2
| | | | | | | | | | | | | | | | | | | A recent cleanup rearranged the Kconfig file for mach-bcm and accidentally dropped the dependency on ARCH_MULTI_V7, which makes it possible to now build the two mobile SoC platforms on an ARMv6-only kernel, resulting in a log of Kconfig warnings like warning: ARCH_BCM_MOBILE selects ARM_ERRATA_775420 which has unmet direct dependencies (CPU_V7) and which of course cannot work on any machine. This puts back the dependencies as before. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 64e74aa788f99 ("ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from Kconfig") Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Scott Branden <sbranden@broadcom.com>
* ARM: brcmstb: update CPU power management sequenceBrian Norris2015-01-121-22/+63
| | | | | | | | | | | | | | | | | | | The automatic CPU power state machine for B15 CPUs does not work reliably as-is. This patch implements a manual sequence in software to replace it. This was tested successfully with over 10,000 hotplug cycles of something like this: echo 0 > /sys/devices/system/cpu/cpu1/online echo 1 > /sys/devices/system/cpu/cpu1/online whereas the existing sequence often locks up after a few hundred cycles. Fixes: 62639c2f5332 ("ARM: brcmstb: reintroduce SMP support") Acked-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* Merge branch 'irq-core-for-linus' of ↵Linus Torvalds2014-12-101-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq core updates from Thomas Gleixner: "This is the first (boring) part of irq updates: - support for big endian I/O accessors in the generic irq chip - cleanup of brcmstb/bcm7120 drivers so they can be reused for non ARM SoCs - the usual pile of fixes and updates for the various ARM irq chips" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) irqchip: dw-apb-ictl: Add PM support irqchip: dw-apb-ictl: Enable IRQ_GC_MASK_CACHE_PER_TYPE irqchip: dw-apb-ictl: Always use use {readl|writel}_relaxed ARM: orion: convert the irq_reg_{readl,writel} calls to the new API irqchip: atmel-aic: Add missing entry for rm9200 irq fixups irqchip: atmel-aic: Rename at91sam9_aic_irq_fixup for naming consistency irqchip: atmel-aic: Add specific irq fixup function for sam9g45 and sam9rl irqchip: atmel-aic: Add irq fixups for at91sam926x SoCs irqchip: atmel-aic: Add irq fixup for RTT block irqchip: brcmstb-l2: Convert driver to use irq_reg_{readl,writel} irqchip: bcm7120-l2: Convert driver to use irq_reg_{readl,writel} irqchip: bcm7120-l2: Decouple driver from brcmstb-l2 irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers irqchip: bcm7120-l2: Use gc->mask_cache to simplify suspend/resume functions irqchip: bcm7120-l2: Fix missing nibble in gc->unused mask irqchip: bcm7120-l2: Make sure all register accesses use base+offset irqchip: bcm7120-l2, brcmstb-l2: Remove ARM Kconfig dependency irqchip: bcm7120-l2: Eliminate bad IRQ check irqchip: brcmstb-l2: Eliminate dependency on ARM code genirq: Generic chip: Add big endian I/O accessors ...
| * irqchip: bcm7120-l2: Decouple driver from brcmstb-l2Kevin Cernekee2014-11-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Some chips, such as BCM6328, only require bcm7120-l2. Some BCM7xxx STB configurations only require brcmstb-l2. Treat them as two separate entities, and update the mach-bcm dependencies to reflect the change. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1415342669-30640-13-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | Merge tag 'arm-soc/for-3.19/cygnus-platform-v2' of ↵Arnd Bergmann2014-11-203-36/+85
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://github.com/brcm/linux into next/soc Pull "Broadcom Cygnus SoC platform support" from Florian Fainelli: This pull request contains the platform code to support the Broadcom Cygnus SoC using the iProc architecture: - add support for the Broadcom Cygnus SoC - consolidate the BCM5301X Kconfig options under the iProc menuconfig entry - remove one level of menu in menuconfig * tag 'arm-soc/for-3.19/cygnus-platform-v2' of http://github.com/brcm/linux: ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from Kconfig ARM: mach-bcm: Consolidate currently supported IPROC SoCs ARM: cygnus: Initial support for Broadcom Cygnus SoC Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from KconfigScott Branden2014-11-111-16/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | remove menu "Broadcom Mobile SoC Selection" This requires: - selecting ARCH_BCM_MOBILE based on SoC selections - fixup bcm_defconfig and multi_v7_defconfig to work with new menu levels. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | ARM: mach-bcm: Consolidate currently supported IPROC SoCsScott Branden2014-11-111-21/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move ARCH_BCM_5301X subarch under ARCH_IPROC architecture. Additional IPROC chipsets that share a lot of commonality should be added under ARCH_IPROC as well. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | ARM: cygnus: Initial support for Broadcom Cygnus SoCJonathan Richardson2014-11-113-0/+60
| |/ | | | | | | | | | | | | | | | | | | | | Adds initial support for the Cygnus SoC based on Broadcom’s iProc series. Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Desmond Liu <desmondl@broadcom.com> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com> Tested-by: Jonathan Richardson <jonathar@broadcom.com> Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | ARM: brcmstb: Kconfig: drop unneeded symbol selectionsBrian Norris2014-10-201-3/+0
| | | | | | | | | | | | | | These are either implied or not necessary. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | ARM: brcmstb: reintroduce SMP supportBrian Norris2014-10-204-0/+383
|/ | | | | | | | | | | Support for SMP bringup of the B15 CPUs on Broadcom STB chips was added in commit 4fbe66d9903425156c193ae44c81c0f7557755c4 but was reverted in commit fc3e825fa91636a5d1b992e769b2d8279877bfad to address some late review comments. This reintroduces SMP support. Signed-off-by: Marc Carino <marc.ceeeee@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* Merge tag 'bcm63138-v4' of http://github.com/brcm/linux into next/socArnd Bergmann2014-09-253-0/+47
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge "ARM: BCM: Broadcom BCM63138 support" from Florian Fainelli: This patchset adds very minimal support for the BCM63138 SoC which is a xDSL SoC using a dual Cortex A9 CPU complex. * tag 'bcm63138-v4' of http://github.com/brcm/linux: MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCs ARM: BCM63XX: add BCM963138DVT Reference platform DTS ARM: BCM63XX: add BCM63138 minimal Device Tree ARM: BCM63XX: add low-level UART debug support ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC Conflicts: arch/arm/Kconfig.debug Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoCFlorian Fainelli2014-09-173-0/+47
| | | | | | | | | | | | | | | | | | This patch adds basic support for the Broadcom BCM63138 DSL SoC which is using a dual-core Cortex A9 system. Add the very minimum required code boot Linux on this SoC. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | ARM: brcmstb: revert SMP supportBrian Norris2014-08-254-416/+0
|/ | | | | | | | | | | There were several issues (of varying degree of importance) pointed out with this code late in the review cycle, yet the code was still merged. Let's rip it out for now and look at resubmitting at a later time. This reverts most of commit 4fbe66d9903425156c193ae44c81c0f7557755c4. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* Merge tag 'soc-for-3.17' of ↵Linus Torvalds2014-08-087-3/+684
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "This is the bulk of new SoC enablement and other platform changes for 3.17: - Samsung S5PV210 has been converted to DT and multiplatform - Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms - Kirkwood, one of the popular Marvell platforms, is folded into the mvebu platform code, removing mach-kirkwood - Hwmod data for TI AM43xx and DRA7 platforms - More additions of Renesas shmobile platform support - Removal of plat-samsung contents that can be removed with S5PV210 being multiplatform/DT-enabled and the other two old platforms being removed New platforms (most with only basic support right now): - Hisilicon X5HD2 settop box chipset is introduced - Mediatek MT6589 (mobile chipset) is introduced - Broadcom BCM7xxx settop box chipset is introduced + as usual a lot other pieces all over the platform code" * tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits) ARM: hisi: remove smp from machine descriptor power: reset: move hisilicon reboot code ARM: dts: Add hix5hd2-dkb dts file. ARM: debug: Rename Hi3716 to HIX5HD2 ARM: hisi: enable hix5hd2 SoC ARM: hisi: add ARCH_HISI MAINTAINERS: add entry for Broadcom ARM STB architecture ARM: brcmstb: select GISB arbiter and interrupt drivers ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs ARM: configs: enable SMP in bcm_defconfig ARM: add SMP support for Broadcom mobile SoCs Documentation: arm: misc updates to Marvell EBU SoC status Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC ARM: mvebu: fix build without platforms selected ARM: mvebu: add cpuidle support for Armada 38x ARM: mvebu: add cpuidle support for Armada 370 cpuidle: mvebu: add Armada 38x support cpuidle: mvebu: add Armada 370 support cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7 ARM: mvebu: export the SCU address ...
| * ARM: brcmstb: select GISB arbiter and interrupt driversBrian Norris2014-07-281-0/+2
| | | | | | | | | | | | | | Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Matt Porter <mporter@linaro.org>
| * ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCsMarc Carino2014-07-286-0/+462
| | | | | | | | | | | | | | | | | | | | | | The BCM7xxx series of Broadcom SoCs are used primarily in set-top boxes. This patch adds machine support for the ARM-based Broadcom SoCs. Signed-off-by: Marc Carino <marc.ceeeee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Matt Porter <mporter@linaro.org>
| * ARM: add SMP support for Broadcom mobile SoCsAlex Elder2014-07-283-3/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SMP support for BCM281XX and BCM21664 family SoCs. This feature is controlled with a distinct config option such that an SMP-enabled multi-v7 binary can be configured to run these SoCs in uniprocessor mode. Since this SMP functionality is used for multiple Broadcom mobile chip families the config option is called ARCH_BCM_MOBILE_SMP (for lack of a better name). On SoCs of this type, the secondary core is not held in reset on power-on. Instead it loops in a ROM-based holding pen. To release it, one must write into a special register a jump address whose low-order bits have been replaced with a secondary core's id, then trigger an event with SEV. On receipt of an event, the ROM code will examine the register's contents, and if the low-order bits match its cpu id, it will clear them and write the value back to the register just prior to jumping to the address specified. The location of the special register is defined in the device tree using a "secondary-boot-reg" property in a node whose "enable-method" matches. Derived from code originally provided by Ray Jui <rjui@broadcom.com> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
* | platform: Remove most references to platform_bus devicePawel Moll2014-07-232-4/+2
|/ | | | | | | | | | | | | | | | A number of board files in arch/arm and arch/unicore32 explicitly reference platform_bus device as a parent for new platform devices. This is unnecessary, as platform device API guarantees that devices with NULL parent are going to by adopted by the mentioned "root" device. This patch removes or replaces with NULL such references. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: use menuconfig for sub-arch menusRob Herring2014-06-171-4/+3
| | | | | | | | | | | | | The System Type menu is getting quite long with platforms and is inconsistent in handling of sub-arch specific options. Tidy up the menu by making platform options a menuconfig entry containing any platform specific config items. [arnd: change OMAP part according to suggestion from Tony Lindgren <tony@atomide.com>] Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into nextLinus Torvalds2014-06-051-7/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull ARM updates from Russell King: - Major clean-up of the L2 cache support code. The existing mess was becoming rather unmaintainable through all the additions that others have done over time. This turns it into a much nicer structure, and implements a few performance improvements as well. - Clean up some of the CP15 control register tweaks for alignment support, moving some code and data into alignment.c - DMA properties for ARM, from Santosh and reviewed by DT people. This adds DT properties to specify bus translations we can't discover automatically, and to indicate whether devices are coherent. - Hibernation support for ARM - Make ftrace work with read-only text in modules - add suspend support for PJ4B CPUs - rework interrupt masking for undefined instruction handling, which allows us to enable interrupts earlier in the handling of these exceptions. - support for big endian page tables - fix stacktrace support to exclude stacktrace functions from the trace, and add save_stack_trace_regs() implementation so that kprobes can record stack traces. - Add support for the Cortex-A17 CPU. - Remove last vestiges of ARM710 support. - Removal of ARM "meminfo" structure, finally converting us solely to memblock to handle the early memory initialisation. * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits) ARM: ensure C page table setup code follows assembly code (part II) ARM: ensure C page table setup code follows assembly code ARM: consolidate last remaining open-coded alignment trap enable ARM: remove global cr_no_alignment ARM: remove CPU_CP15 conditional from alignment.c ARM: remove unused adjust_cr() function ARM: move "noalign" command line option to alignment.c ARM: provide common method to clear bits in CPU control register ARM: 8025/1: Get rid of meminfo ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type ARM: 8066/1: correction for ARM patch 8031/2 ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation ARM: 8065/1: remove last use of CONFIG_CPU_ARM710 ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction ARM: 8047/1: rwsem: use asm-generic rwsem implementation ARM: l2c: trial at enabling some Cortex-A9 optimisations ARM: l2c: add warnings for stuff modifying aux_ctrl register values ARM: l2c: print a warning with L2C-310 caches if the cache size is modified ARM: l2c: remove old .set_debug method ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this ...
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