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* ARM: imx: Use of_property_read_bool() for boolean propertiesRob Herring2023-03-141-1/+1
| | | | | | | | | | It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to to of_property_read_bool(). Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx: Remove unnecessary blank linesAnson Huang2020-03-111-1/+0
| | | | | | | Remove unnecessary blank lines for cleanup. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx: Add missing of_node_put()Anson Huang2020-02-181-0/+1
| | | | | | | | After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx: Remove unused include of linux/irqchip/arm-gic.hAnson Huang2020-02-171-1/+1
| | | | | | | linux/irqchip/arm-gic.h is NOT used at all, no need to include it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 159Thomas Gleixner2019-05-301-7/+1
| | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: imx: add L2 page power control for GPCAnson Huang2018-06-191-0/+14
| | | | | | | | | | | Some platforms like i.MX6UL/i.MX6SLL have L2 page power control in GPC, it needs to be disabled if ARM is power gated and L2 is NOT flushed, add GPC interface to control it. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: Convert to using %pOF instead of full_nameRob Herring2017-08-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Simon Horman <horms+renesas@verge.net.au> Cc: Russell King <linux@armlinux.org.uk> Cc: Kukjin Kim <kgene@kernel.org> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Cc: "Benoît Cousson" <bcousson@baylibre.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* soc: imx: move PGC handling to a new GPC driverLucas Stach2017-03-081-217/+0
| | | | | | | | | | | | | | | This is an almost complete re-write of the previous GPC power gating control code found in the IMX architecture code. It supports both the old and the new DT binding, allowing more domains to be added later and generally makes the driver easier to extend, while keeping compatibility with existing DTBs. As the result, all functionality regarding the power gating controller gets removed from the IMX architecture GPC driver. It keeps only the IRQ controller code in the architecture, as this is closely coupled to the CPU idle implementation. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge branch 'pm-domains'Rafael J. Wysocki2016-12-121-7/+10
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pm-domains: PM / Domains: Fix compatible for domain idle state PM / Domains: Do not print PM domain add error message if EPROBE_DEFER PM / Domains: Fix a warning message PM / Domains: check for negative return from of_count_phandle_with_args() PM / doc: Update device documentation for devices in IRQ-safe PM domains PM / Domains: Support IRQ safe PM domains PM / Domains: Abstract genpd locking dt/bindings / PM/Domains: Update binding for PM domain idle states PM / Domains: Save the fwnode in genpd_power_state PM / Domains: Allow domain power states to be read from DT PM / Domains: Add residency property to genpd states PM / Domains: Make genpd state allocation dynamic Conflicts: arch/arm/mach-imx/gpc.c
| * PM / Domains: Make genpd state allocation dynamicLina Iyer2016-10-211-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | Allow PM Domain states to be defined dynamically by the drivers. This removes the limitation on the maximum number of states possible for a domain. Suggested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | ARM: imx: gpc: Fix the imx_gpc_genpd_init() error pathFabio Estevam2016-10-241-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If of_genpd_add_provider_onecell() fails the following kernel crash is observed on a kernel built with multi_v7_defconfig: [ 1.739301] [00000040] *pgd=00000000 [ 1.739310] Internal error: Oops: 5 [#1] SMP ARM [ 1.739319] Modules linked in: [ 1.739328] CPU: 1 PID: 95 Comm: kworker/1:4 Not tainted 4.8.0-11897-g6b5e09a #1 [ 1.739331] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) [ 1.739352] Workqueue: pm genpd_power_off_work_fn [ 1.739356] task: ee63d400 task.stack: ee70a000 [ 1.739365] PC is at mutex_lock+0xc/0x4c [ 1.739374] LR is at regulator_disable+0x2c/0x60 [ 1.739379] pc : [<c0bc0da0>] lr : [<c06e4b10>] psr: 60000013 [ 1.739379] sp : ee70beb0 ip : 10624dd3 fp : ee6e6280 [ 1.739382] r10: eefb0900 r9 : 00000000 r8 : c1309918 [ 1.739385] r7 : 00000000 r6 : 00000040 r5 : 00000000 r4 : 00000040 [ 1.739390] r3 : 0000004c r2 : 7fffd540 r1 : 000001e4 r0 : 00000040 Instead of returning of_genpd_add_provider_onecell() directly, we should check its return value and in the case of error we should unwind the previously taken actions, which in these case are: - Call imx6q_pm_pu_power_off() - Set imx6q_pu_domain.reg back to NULL Setting imx6q_pu_domain.reg to NULL in the error case is important as it will prevent further operations in the pu_reg regulator. This kernel crash is not observed with imx_v6_v7_defconfig because it selects GPU and VPU drivers, which are consumers of the GPC block and thus change the refcount of the pu_reg regulator. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | ARM: imx: gpc: Initialize all power domainsFabio Estevam2016-10-241-1/+2
|/ | | | | | | | | | | | | | | | | | Since commit 0159ec670763dd ("PM / Domains: Verify the PM domain is present when adding a provider") the following regression is observed on imx6: imx-gpc: probe of 20dc000.gpc failed with error -22 The gpc probe fails because of_genpd_add_provider_onecell() now checks if all the domains are initialized via pm_genpd_present() function and it fails because not all the power domains are initialized. In order to fix this error, initialize all the power domains from imx_gpc_domains[], not only the imx6q_pu_domain.base one. Reported-by: Olof's autobooter <build@lixom.net> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* ARM: imx6: mark GPC node as not populated after irq init to probe pm domain ↵Philipp Zabel2016-08-091-0/+6
| | | | | | | | | | | | | driver Since IRQCHIP_DECLARE now flags the GPC node as already populated, the GPC power domain driver is never probed unless we clear the flag again. Fixes: 15cc2ed6dcf9 ("of/irq: Mark initialised interrupt controllers as populated") Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Cc: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Rob Herring <robh@kernel.org>
* ARM: imx6: pm: declare pm domain latency on power_state structAxel Haslam2016-02-151-2/+7
| | | | | | | | | | | | | | | The generic_pm_domain structure uses an array of latencies to be able to declare multiple intermediate states. Declare a single "OFF" state with the default latencies So that the power_off_latency_ns and power_on_latency_ns fields of generic_pm_domain structure can be eventually removed. [ Lina: pm_genpd_init() argument changev ] Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Axel Haslam <ahaslam+renesas@baylibre.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* ARM: imx: add platform irq type setting in gpcAnson Huang2015-11-231-0/+1
| | | | | | | | | | | | | | | | GPC irq domain is a child domain of GIC, now all of platform irqs are inside GPC domain, during the module populate, all devices irq should have correct type setting in GIC, however, there is no .irq_set_type callback setting in GPC, so the irq_set_type will be skipped and cause all irqs' type in /proc/interrupt are "edge" which mismatch with irq type setting in dtb file. Since GPC has no irq type setting, so just tell kernel to use irq_chip_set_type_parent. Signed-off-by: Anson Huang <Anson.Huang@freescale.com> Cc: <stable@vger.kernel.org> # 4.1+ Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge tag 'armsoc-cleanup' of ↵Linus Torvalds2015-11-101-6/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Olof Johansson: "Again we have a sizable (but not huge) cleanup branch with a net delta of about -3k lines. Main contents here is: - A bunch of development/cleanup of a few PXA boards - Removal of bockw platforms on shmobile, since the platform has now gone completely multiplatform. Whee! - move of the 32kHz timer on OMAP to a proper timesource - Misc cleanup of older OMAP material (incl removal of one board file) - Switch over to new common PWM lookup support for several platforms There's also a handful of other cleanups across the tree, but the above are the major pieces" * tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (103 commits) ARM: OMAP3: hwmod data: Remove legacy mailbox data and addrs ARM: DRA7: hwmod data: Remove spinlock hwmod addrs ARM: OMAP4: hwmod data: Remove spinlock hwmod addrs ARM: DRA7/AM335x/AM437x: hwmod: Remove gpmc address space from hwmod data ARM: Remove __ref on hotplug cpu die path ARM: Remove open-coded version of IRQCHIP_DECLARE arm: omap2: board-generic: use omap4_local_timer_init for AM437x ARM: DRA7/AM335x/AM437x: hwmod: Remove elm address space from hwmod data ARM: OMAP: Remove duplicated operand in OR operation clocksource: ti-32k: make it depend on GENERIC_CLOCKSOURCE ARM: pxa: remove incorrect __init annotation on pxa27x_set_pwrmode ARM: pxa: raumfeld: make some variables static ARM: OMAP: Change all cpu_is_* occurences to soc_is_* for id.c ARM: OMAP2+: Rename cpu_is macros to soc_is arm: omap2: timer: limit hwmod usage to non-DT boots arm: omap2+: select 32k clocksource driver clocksource: add TI 32.768 Hz counter driver arm: omap2: timer: rename omap_sync32k_timer_init() arm: omap2: timer: always call clocksource_of_init() when DT arm: omap2: timer: move realtime_counter_init() around ...
| * ARM: Remove open-coded version of IRQCHIP_DECLAREMarc Zyngier2015-10-221-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the IRQCHIP_DECLARE macro has been moved to linux/irqchip.h, it becomes possible to cleanup the open-coded versions of the same macro that have been added to some private irqchips implementations. Cc: Sascha Hauer <kernel@pengutronix.de> Acked-by: Kukjin Kim <kgene@kernel.org> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | irqchip: Convert all alloc/xlate users from of_node to fwnodeMarc Zyngier2015-10-131-26/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we now have a generic data structure to express an interrupt specifier, convert all hierarchical irqchips that are OF based to use a fwnode_handle as part of their alloc and xlate (which becomes translate) callbacks. As most of these drivers have dependencies (they exchange IRQ specifiers), change them all in a single, massive patch... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-and-tested-by: Hanjun Guo <hanjun.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Tomasz Nowicki <tomasz.nowicki@linaro.org> Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Cc: Graeme Gregory <graeme@xora.org.uk> Cc: Jake Oshins <jakeo@microsoft.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Link: http://lkml.kernel.org/r/1444737105-31573-6-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | irqdomain: Use irq_domain_get_of_node() instead of direct field accessMarc Zyngier2015-10-131-2/+2
|/ | | | | | | | | | | | | | | | | | | | | | | The struct irq_domain contains a "struct device_node *" field (of_node) that is almost the only link between the irqdomain and the device tree infrastructure. In order to prepare for the removal of that field, convert all users to use irq_domain_get_of_node() instead. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-and-tested-by: Hanjun Guo <hanjun.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Tomasz Nowicki <tomasz.nowicki@linaro.org> Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Cc: Graeme Gregory <graeme@xora.org.uk> Cc: Jake Oshins <jakeo@microsoft.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Link: http://lkml.kernel.org/r/1444737105-31573-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* ARM: imx6: gpc: always enable PU domain if CONFIG_PM is not setLucas Stach2015-07-081-21/+6
| | | | | | | | | | | | | | | | | | | | | If CONFIG_PM is not set the PU power domain needs to be enabled always, otherwise there are two failure scenarios which will hang the system if one of the devices in the PU domain is accessed. 1. New DTs (4.1+) drop the "always-on" property from the PU regulator, so if it isn't properly enabled by the GPC code it will be disabled at the end of boot. 2. If the bootloader already disabled the PU domain the GPC explicitly needs to enable it again, even if the kernel doesn't do any power management. This is a bit hypothetical, as it requires to boot a mainline kernel on a downstream bootloader, as no mainline bootloader disables the PM domains. Cc: <stable@vger.kernel.org> # 4.1 Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Merge tag 'armsoc-soc' of ↵Linus Torvalds2015-06-261-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform support updates from Kevin Hilman: "Our SoC branch usually contains expanded support for new SoCs and other core platform code. Some highlights from this round: - sunxi: SMP support for A23 SoC - socpga: big-endian support - pxa: conversion to common clock framework - bcm: SMP support for BCM63138 - imx: support new I.MX7D SoC - zte: basic support for ZX296702 SoC" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits) ARM: zx: Add basic defconfig support for ZX296702 ARM: dts: zx: add an initial zx296702 dts and doc clk: zx: add clock support to zx296702 dt-bindings: Add #defines for ZTE ZX296702 clocks ARM: socfpga: fix build error due to secondary_startup MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS ARM: ep93xx: simone: support for SPI-based MMC/SD cards MAINTAINERS: update Shawn's email to use kernel.org one ARM: socfpga: support suspend to ram ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10 ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5 ARM: EXYNOS: register power domain driver from core_initcall ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs ARM: SAMSUNG: Constify platform_device_id ARM: EXYNOS: Constify irq_domain_ops ARM: EXYNOS: add coupled cpuidle support for Exynos3250 ARM: EXYNOS: add exynos_get_boot_addr() helper ARM: EXYNOS: add exynos_set_boot_addr() helper ARM: EXYNOS: make exynos_core_restart() less verbose ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout ...
| * ARM: imx: Constify irq_domain_opsKrzysztof Kozlowski2015-06-031-1/+1
| | | | | | | | | | | | | | | | The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge tag 'armsoc-cleanup' of ↵Linus Torvalds2015-06-261-1/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Kevin Hilman: "A relatively small setup of cleanups this time around, and similar to last time the bulk of it is removal of legacy board support: - OMAP: removal of legacy (non-DT) booting for several platforms - i.MX: remove some legacy board files" * tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (36 commits) ARM: fix EFM32 build breakage caused by cpu_resume_arm ARM: 8389/1: Add cpu_resume_arm() for firmwares that resume in ARM state ARM: v7 setup function should invalidate L1 cache mach-omap2: Remove use of deprecated marco, PTR_RET in devices.c ARM: OMAP2+: Remove calls to deprecacted marco,PTR_RET in the files,fb.c and pmu.c ARM: OMAP2+: Constify irq_domain_ops ARM: OMAP2+: use symbolic defines for console loglevels instead of numbers ARM: at91: remove useless Makefile.boot ARM: at91: remove at91rm9200_sdramc.h ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h ARM: at91/pm: use the atmel-mc syscon defines pcmcia: at91_cf: Use syscon to configure the MC/smc ARM: at91: declare the at91rm9200 memory controller as a syscon mfd: syscon: Add Atmel MC (Memory Controller) registers definition ARM: at91: drop sam9_smc.c ata: at91: use syscon to configure the smc ARM: ux500: delete static resource defines ARM: ux500: rename ux500_map_io ARM: ux500: look up PRCMU resource from DT ARM: ux500: kill off L2CC static map ...
| * | ARM: imx: gpc: Remove .owner fieldFabio Estevam2015-05-111-1/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | This platform_driver does not need to set an owner as it will be populated by the driver core. The semantic patch that makes this change is available in scripts/coccinelle/api/platform_no_drv_owner.cocci. More information about semantic patching is available at http://coccinelle.lip6.fr/ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: imx6: gpc: don't register power domain if DT data is missingLucas Stach2015-05-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | If the devicetree is too old and does not provide the regulator and clocks for the power domain, we need to avoid registering the power domain. Otherwise runtime PM will try to control the domain, which will lead to machine hangs without the proper DT configuration data. This restores functionality to the kernel 4.0 level if an old DT is detected, where the power domain is constantly powered on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: imx6: allow booting with old DTLucas Stach2015-05-271-3/+9
|/ | | | | | | | | | | | | | | | | | | | The GPC rewrite to IRQ domains has been on the premise that it may break suspend/resume for new kernels on old DT, but otherwise keep things working from a user perspective. This was an accepted compromise to be able to move the GIC cleanup forward. What actually happened was that booting a new kernel on an old DT crashes before even the console is up, so the user does not even see the warning that the DT is too old. The warning message suggests that this has been known before, which is clearly unacceptable. Fix the early crash by mapping the GPC memory space if the IRQ controller doesn't claim it. This keeps at least CPUidle and the needed CPU wakeup workarounds working. With this fixed the system is able to boot up properly minus the expected suspend/resume breakage. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: Warn when an old DT is detectedMarc Zyngier2015-03-301-0/+10
| | | | | | | | | | | | | Now that the GPC has been converted to be a full blown irqchip (and not a mole on the side of the GIC), booting a new kernel with an old DT is likely to result in a rough ride for the user. This patch makes sure such a situation is promptly detected and the user made aware that a DT update is in order. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: Allow GPC interrupts affinity to be changedMarc Zyngier2015-03-301-6/+9
| | | | | | | | | | | | While converting the GPC code to a stacked irqchip, we lost the possibility to change the CPU affinity of an interrupt routed through the GPC. This patch restore the expected behaviour by forwarding the affinity setup to the underlying irqchip (GIC). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: convert GPC to stacked domainsMarc Zyngier2015-03-301-24/+103
| | | | | | | | | | | | | | | | | | | | IMX6 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the fact that the GPC block is actually the first interrupt controller in the chain, kernels with this patch applied wont have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. Tested-by: Stefan Agner <stefan@agner.ch> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: gpc: Add PU power domain for GPU/VPUPhilipp Zabel2015-03-111-0/+213
| | | | | | | | | | | | | | | | | When generic pm domain support is enabled, the PGC can be used to completely gate power to the PU power domain containing GPU3D, GPU2D, and VPU cores. This code triggers the PGC powerdown sequence to disable the GPU/VPU isolation cells and gate power and then disables the PU regulator. To reenable, the reverse powerup sequence is triggered after the PU regulator is enabled again. The GPU and VPU devices in the PU power domain temporarily need to be clocked during powerup, so that the reset machinery can work. [Avoid explicit regulator enabling in probe, unless !PM] Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx: support arm power off in cpuidle for i.mx6sxAnson Huang2015-01-051-2/+23
| | | | | | | | | | | | | | | | | This patch introduces an independent cpuidle driver for i.MX6SX, and supports arm power off in idle, totally 3 levels of cpuidle are supported as below: 1. ARM WFI; 2. SOC in WAIT mode; 3. SOC in WAIT mode + ARM power off. ARM power off can save at least 5mW power. This patch also replaces imx6q_enable_rbc with imx6_enable_rbc. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* ARM: imx6: fix bogus use of irq_get_irq_dataMarc Zyngier2014-12-041-12/+22
| | | | | | | | | | | | | | | | The imx6 PM code seems to be quite creative in its use of irq_data, using something that is very much a hardware interrupt number where we expect a virtual one. Yes, it worked so far, but that's only luck, and it will definitely explode in 3.19. Fix it by using a pair of helper functions that deal with the actual hardware. Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: imx: irq: fix buggy usage of irq_data irq fieldMarc Zyngier2014-12-041-9/+9
| | | | | | | | | | | | | | | | | mach-imx directly references to the irq field in struct irq_data, and uses this to directly poke hardware register. But irq is the *virtual* irq number, something that has nothing to do with the actual HW irq (stored in the hwirq field). And once we put the stacked domain code in action, the whole thing explodes, as these two values are *very* different. Just replacing all instances of irq with hwirq fixes the issue. Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: imx: add standby mode support for suspendAnson Huang2014-07-181-2/+3
| | | | | | | | | | | | | Add standby mode support for suspend, to enter standby mode: echo standby > /sys/power/state; Use UART or RTC alarm to wake up system, when system enters standby mode, SOC will enter STOP mode with ARM core kept power on and 24M XTAL on. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: ensure dsm_request signal is not asserted when setting LPMShawn Guo2013-10-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | There is a defect in imx6 LPM design. When SW tries to enter low power mode with following sequence, the chip will enter low power mode before A9 CPU execute WFI instruction: 1. Set CCM_CLPCR[1:0] to 2'b00; 2. ARM CPU enters WFI; 3. ARM CPU wakeup from an interrupt event, which is masked by GPC or not visible to GPC, such as interrupt from local timer; 4. Set CCM_CLPCR[1:0] to 2'b01 or 2'b10; 5. ARM CPU execute WFI. Before the last step, the chip will enter WAIT mode if CCM_CLPCR[1:0] is set to 2'b01, or enter STOP mode if CCM_CLPCR[1:0] is set to 2'b10. The patch implements a recommended workaround for this issue. 1. SW triggers irq #32(IOMUX) to be always pending manually by setting IOMUX_GPR1_GINT bit; 2. SW should then unmask it in GPC before setting CCM LPM; 3. SW should mask it right after CCM LPM is set (bit0-1 of CCM_CLPCR). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Merge tag 'soc-for-linus-3' of ↵Linus Torvalds2013-05-071-1/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates (part 3) from Arnd Bergmann: "This is the third and smallest of the SoC specific updates. Changes include: - SMP support for the Xilinx zynq platform - Smaller imx changes - LPAE support for mvebu - Moving the orion5x, kirkwood, dove and mvebu platforms to a common "mbus" driver for their internal devices. It would be good to get feedback on the location of the "mbus" driver. Since this is used on multiple platforms may potentially get shared with other architectures (powerpc and arm64), it was moved to drivers/bus/. We expect other similar drivers to get moved to the same place in order to avoid creating more top-level directories under drivers/ or cluttering up the messy drivers/misc/ even more." * tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits) ARM: imx: reset_controller may be disabled ARM: mvebu: Align the internal registers virtual base to support LPAE ARM: mvebu: Limit the DMA zone when LPAE is selected arm: plat-orion: remove addr-map code arm: mach-mv78xx0: convert to use the mvebu-mbus driver arm: mach-orion5x: convert to use mvebu-mbus driver arm: mach-dove: convert to use mvebu-mbus driver arm: mach-kirkwood: convert to use mvebu-mbus driver arm: mach-mvebu: convert to use mvebu-mbus driver ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock ARM i.MX53: tve_di clock is not part of the CCM, but of TVE ARM i.MX53: make tve_ext_sel propagate rate change to PLL ARM i.MX53: Remove unused tve_gate clkdev entry ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree ARM: i.MX5: Add PATA and SRTC clocks ARM: imx: do not bring up unavailable cores ARM: imx: add initial imx6dl support ARM: imx1: mm: add call to mxc_device_init ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS ...
| * ARM: imx: enable RBC to support anatop LPM modeAnson Huang2013-04-121-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RBC is to control whether some ANATOP sub modules can enter lpm mode when SOC is into STOP mode, if RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP will have below behaviors: 1. Digital LDOs(CORE, SOC and PU) are bypassed; 2. Analog LDOs(1P1, 2P5, 3P0) are disabled; As the 2P5 is necessary for DRAM IO pre-drive in STOP mode, so we need to enable weak 2P5 in STOP mode when 2P5 LDO is disabled. For RBC settings, there are some rules as below due to hardware design: 1. All interrupts must be masked during operating RBC registers; 2. At least 2 CKIL(32K) cycles is needed after the RBC setting is changed. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: mach-imx: gpc: Include "common.h"Fabio Estevam2013-04-011-0/+1
|/ | | | | | | | | | | | | Fix the following sparse warnings: arch/arm/mach-imx/gpc.c:29:6: warning: symbol 'imx_gpc_pre_suspend' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:43:6: warning: symbol 'imx_gpc_post_resume' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:71:6: warning: symbol 'imx_gpc_mask_all' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:83:6: warning: symbol 'imx_gpc_restore_all' was not declared. Should it be static? arch/arm/mach-imx/gpc.c:122:13: warning: symbol 'imx_gpc_init' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Merge tag 'imx6q-cpudile-3.9' of ↵Olof Johansson2013-02-041-0/+5
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc From Shawn Guo: imx6q cpuidle support for 3.9 - It's based on imx-cleanup-3.9 to avoid conflicts. * tag 'imx6q-cpudile-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: imx6q: support WAIT mode using cpuidle ARM: imx: move imx6q_cpuidle_driver into a separate file ARM: imx: mask gpc interrupts initially ARM: imx: return zero in case next event gets a large increment ARM: imx: Remove mx508 support ARM: imx: Remove mach-mx51_3ds board ARM: imx: use debug_ll_io_init() for imx6q ARM: imx: remove unused imx6q_clock_map_io() ARM: mach-imx: Kconfig: Do not select Babbage for MACH_IMX51_DT Signed-off-by: Olof Johansson <olof@lixom.net> Still, two delete/change conflicts caused by imx/cleanup: arch/arm/mach-imx/mach-mx50_rdp.c arch/arm/mach-imx/mach-mx51_3ds.c
| * ARM: imx: mask gpc interrupts initiallyShawn Guo2013-01-301-0/+5
| | | | | | | | | | | | Mask gpc interrupts initially to avoid suspicious interrupts. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | irqchip: Move ARM gic.h to include/linux/irqchip/arm-gic.hRob Herring2013-01-121-1/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | Now that we have GIC moved to drivers/irqchip and all GIC DT init for platforms using irqchip_init, move gic.h and update the remaining includes. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Anton Vorontsov <avorontsov@mvista.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Samuel Ortiz <sameo@linux.intel.com>
* arm/imx6q: add core drivers clock, gpc, mmdc and srcShawn Guo2011-10-311-0/+113
It adds a number of core drivers support for imx6q, including clock, General Power Controller (gpc), Multi Mode DDR Controller(mmdc) and System Reset Controller (src). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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