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* soc/tegra: Add efuse driver for TegraPeter De Schrijver2014-07-171-260/+0
| | | | | | | | | | | | | | Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This replaces functionality previously provided in arch/arm/mach-tegra, which is removed in this patch. While at it, move the only user of the global tegra_revision variable over to tegra_sku_info.revision and export tegra_fuse_readl() to allow drivers to read calibration fuses. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Use a function to get the chip IDThierry Reding2014-07-171-6/+13
| | | | | | | | | | | Instead of using a simple variable access to get at the Tegra chip ID, use a function so that we can run additional code. This can be used to determine where the chip ID is being accessed without being available. That in turn will be handy for resolving boot sequence dependencies in order to convert more code to regular initcalls rather than a sequence fixed by Tegra SoC setup code. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Sort includes alphabeticallyThierry Reding2014-07-171-4/+4
| | | | | | | | If these aren't sorted alphabetically, then the logical choice is to append new ones, however that creates a lot of potential for conflicts because every change will then add new includes in the same location. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Move includes to include/soc/tegraThierry Reding2014-07-171-1/+2
| | | | | | | In order to not clutter the include/linux directory with SoC specific headers, move the Tegra-specific headers out into a separate directory. Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'tegra-for-3.14-soc' of ↵Olof Johansson2013-12-261-1/+40
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc From Stephen Warren: ARM: tegra: SoC-specific core code changes This branch contains various miscellaneous changes to code in the mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict with anything else. * tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC ARM: tegra: use section-sized static mappings for LPAE too ARM: tegra: don't hard-code DEBUG_LL baud rate ARM: tegra: fix DEBUG_LL combined with LPAE ARM: tegra: switch FUSE clock on before usage Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: tegra: switch FUSE clock on before usageAlexandre Courbot2013-12-041-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | FUSE clock is enabled by most bootloaders, but we cannot expect it to be on in all contexts (e.g. kexec). Ensure the FUSE clock is enabled before any of its registers is touched. Since FUSE is touched very early during system boot (before the clock devices are registered), directly manipulate the clock register bit in case the clock device cannot be acquired. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: add missing break to fuse initialization codeStephen Warren2013-12-111-0/+2
| | | | | | | | | | | | | | | | | | | | Add a missing break to the switch in tegra_init_fuse() which determines which SoC the code is running on. This prevents the Tegra30+ fuse handling code from running on Tegra20. Fixes: 3bd1ae57f7bb ("ARM: tegra: add fuses as device randomness") Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds2013-11-231-10/+0
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull crypto update from Herbert Xu: - Made x86 ablk_helper generic for ARM - Phase out chainiv in favour of eseqiv (affects IPsec) - Fixed aes-cbc IV corruption on s390 - Added constant-time crypto_memneq which replaces memcmp - Fixed aes-ctr in omap-aes - Added OMAP3 ROM RNG support - Add PRNG support for MSM SoC's - Add and use Job Ring API in caam - Misc fixes [ NOTE! This pull request was sent within the merge window, but Herbert has some questionable email sending setup that makes him public enemy #1 as far as gmail is concerned. So most of his emails seem to be trapped by gmail as spam, resulting in me not seeing them. - Linus ] * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (49 commits) crypto: s390 - Fix aes-cbc IV corruption crypto: omap-aes - Fix CTR mode counter length crypto: omap-sham - Add missing modalias padata: make the sequence counter an atomic_t crypto: caam - Modify the interface layers to use JR API's crypto: caam - Add API's to allocate/free Job Rings crypto: caam - Add Platform driver for Job Ring hwrng: msm - Add PRNG support for MSM SoC's ARM: DT: msm: Add Qualcomm's PRNG driver binding document crypto: skcipher - Use eseqiv even on UP machines crypto: talitos - Simplify key parsing crypto: picoxcell - Simplify and harden key parsing crypto: ixp4xx - Simplify and harden key parsing crypto: authencesn - Simplify key parsing crypto: authenc - Export key parsing helper function crypto: mv_cesa: remove deprecated IRQF_DISABLED hwrng: OMAP3 ROM Random Number Generator support crypto: sha256_ssse3 - also test for BMI2 crypto: mv_cesa - Remove redundant of_match_ptr crypto: sahara - Remove redundant of_match_ptr ...
| * ARM: tegra: remove tegra_chip_uid()Stephen Warren2013-09-241-10/+0
| | | | | | | | | | | | | | | | | | Following commit f5b38c5 "crypto: tegra - use kernel entropy instead of ad-hoc", this function is no longer used. It's also only accurate for Tegra20 and not later SoCs. So, remove it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | ARM: tegra: add fuses as device randomnessStephen Warren2013-10-181-0/+54
| | | | | | | | | | | | | | | | | | | | Various fuses on Tegra include information that's unique to an individual chip, or a subset of chips. Call add_device_randomness() with this data to perturb the initial state of the random pool. Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: tegra: make tegra_init_fuse() __initStephen Warren2013-09-171-1/+1
|/ | | | | | It's a one-time initialization function, called early during boot. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add speedo-based process id for Tegra114Danny Huang2013-03-191-0/+4
| | | | | | | | | | Add speedo-based process identification for Tegra114. Based on the work by: Alex Frid <afrid@nvidia.com> Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren: added include of bug.h] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add function to read chipidPrashant Gaikwad2013-01-281-1/+7
| | | | | | | | | Add function to read chip id from APB MISC registers. This function will also get called from clock driver to flush write operations on apb bus. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Tegra30 speedo-based process identificationDanny Huang2012-11-151-2/+9
| | | | | | | | | This patch adds speedo-based process identification support for Tegra30. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra3/Tegra30/ in log print, s/T30/Tegra30/ in commit description] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Add speedo-based process identificationDanny Huang2012-11-151-8/+23
| | | | | | | | | Detect CPU and core process ID by checking speedo corner tables. This can provide a more accurate process ID. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra2/Tegra20/ in log print] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: flexible spare fuse read functionDanny Huang2012-11-151-7/+12
| | | | | | | | Change the spare fuse base from a definition to a variable. It provides flexibilty to read spare fuse on different chip. Signed-off-by: Danny Huang <dahuang@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: move iomap.h to mach-tegraStephen Warren2012-11-051-2/+1
| | | | | | | | | | | | | | Nothing outside mach-tegra uses this file, so there's no need for it to be in <mach/>. Since uncompress.h and debug-macro.S remain in include/mach, they need to include "../../iomap.h" becaue of this change. uncompress.h will soon be deleted in later multi-platform/single-zImage patches. debug-macro.S will need to continue to include this header using an explicit relative path, to avoid duplicating the physical->virtual address mapping that iomap.h dictates. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: use IO_ADDRESS for getting virtual addressLaxman Dewangan2012-09-061-2/+2
| | | | | | | | | | | Use macro IO_ADDRESS for getting virtual address of corresponding physical address to make the consistency with rest of Tegra code-base. This macro calls the IO_TO_VIRT() which is defined in arch/arm/mach-tegra/include/mach/iomap.h Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2012-03-281-7/+11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull "ARM: More SoC support updates" from Olof Johansson: "This branch contains a handful of updates of SoC base code that had dependencies on other external trees that have now been merged: * Support for the new EXYNOS5250 SoC from Samsung * SMP and power domain support for Tegra3 from NVIDIA * ux500 updates for exporting SoC information through sysfs" Fix up trivial merge conflicts as per Olof. * tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (30 commits) ARM: mach-shmobile: ap4evb: Reserve DMA memory for the frame buffer ARM: EXYNOS: Fix compilation error with mach-exynos4-dt board ARM: dts: add initial dts file for EXYNOS5250, SMDK5250 ARM: EXYNOS: add support device tree enabled board file for EXYNOS5 ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs ARM: EXYNOS: add support get_core_count() for EXYNOS5250 ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5 ARM: EXYNOS: add interrupt definitions for EXYNOS5250 ARM: EXYNOS: add support for EXYNOS5250 SoC ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5 ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5 ARM: EXYNOS: add clock part for EXYNOS5250 SoC ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts() ARM: EXYNOS: to declare static for mach-exynos/common.c ARM: EXYNOS: Add clkdev lookup entry for lcd clock ARM: dt: Explicitly configure all serial ports on Tegra Cardhu ARM: tegra: support for secondary cores on Tegra30 ARM: tegra: support for Tegra30 CPU powerdomains ARM: tegra: add support for Tegra30 powerdomains ARM: tegra: export tegra_powergate_is_powered() ...
| * ARM: tegra: export Tegra chipidPeter De Schrijver2012-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | The powergating and reset handling code needs to differentiate between Tegra variants. Therefore we export the chipid here. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: tegra: cleanup use of chipid registerPeter De Schrijver2012-02-261-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | The chipid register contains information about the Tegra variant and revision. We want differentiate between Tegra variants for powergating and secondary core bringup. This patch cleans up the reading and decoding of this register. In subsequent patches the variant will exported as a global variable. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds2012-03-271-34/+75
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull "ARM: driver specific updates" from Arnd Bergmann: "These are all specific to some driver. They are typically the platform side of a change in the drivers directory, such as adding a new driver or extending the interface to the platform. In cases where there is no maintainer for the driver, or the maintainer prefers to have the platform changes in the same branch as the driver changes, the patches to the drivers are included as well. A much smaller set of driver updates that depend on other branches getting merged first will be sent later. The new export of tegra_chip_uid conflicts with other changes in fuse.c. In rtc-sa1100.c, the global removal of IRQF_DISABLED conflicts with the cleanup of the interrupt handling of that driver. Signed-off-by: Arnd Bergmann <arnd@arndb.de>" Fixed up aforementioned trivial conflicts. * tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (94 commits) ARM: SAMSUNG: change the name from s3c-sdhci to exynos4-sdhci mmc: sdhci-s3c: add platform data for the second capability ARM: SAMSUNG: support the second capability for samsung-soc ARM: EXYNOS: add support DMA for EXYNOS4X12 SoC ARM: EXYNOS: Add apb_pclk clkdev entry for mdma1 ARM: EXYNOS: Enable MDMA driver regulator: Remove bq24022 regulator driver rtc: sa1100: add OF support pxa: magician/hx4700: Convert to gpio-regulator from bq24022 ARM: OMAP3+: SmartReflex: fix error handling ARM: OMAP3+: SmartReflex: fix the use of debugfs_create_* API ARM: OMAP3+: SmartReflex: micro-optimization for sanity check ARM: OMAP3+: SmartReflex: misc cleanups ARM: OMAP3+: SmartReflex: move late_initcall() closer to its argument ARM: OMAP3+: SmartReflex: add missing platform_set_drvdata() ARM: OMAP3+: hwmod: add SmartReflex IRQs ARM: OMAP3+: SmartReflex: clear ERRCONFIG_VPBOUNDINTST only on a need ARM: OMAP3+: SmartReflex: Fix status masking in ERRCONFIG register ARM: OMAP3+: SmartReflex: Add a shutdown hook ARM: OMAP3+: SmartReflex Class3: disable errorgen before disable VP ... Conflicts: arch/arm/mach-tegra/Makefile arch/arm/mach-tegra/fuse.c drivers/rtc/rtc-sa1100.c
| * ARM: tegra: fuse: add bct strapping readingOlof Johansson2012-02-061-0/+14
| | | | | | | | | | | | | | This is used by the memory setup code to pick the right memory timing table, if needed. Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: tegra: fuse: add functions to access chip revisionOlof Johansson2012-02-061-27/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add function to get chip revision, and print it out at boot time. Restructure the fuse access to just use cached variables instead of always reading the fuses, and export those variables directly instead of using accessor functions. Add a SKU ID table of currently known values. Based on code originally by Colin Cross <ccross@android.com>. Changes since v1: * Add A01 minor rev support * Don't decode for A03p on anything but T2x Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: fuse: use apbio dma for register accessOlof Johansson2012-02-061-12/+8
| | | | | | | | | | | | Use the apbio dma functions for accessing the fuse registers. Signed-off-by: Olof Johansson <olof@lixom.net>
* | arm: tegra: export tegra_chip_uidHenning Heinold2012-01-131-0/+2
|/ | | | | | | | | | | | The crypto driver will need this api to use it in the RNG calculations. In order to build the crypto driver as a module, tegra_chip_uid has to be exported. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Henning Heinold <heinold@inf.fu-berlin.de> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* [ARM] tegra: Add support for reading fusesColin Cross2010-10-211-0/+84
The Tegra SOC contains fuses to identify the CPU type and bin, and a unique id. The CPU info is required to determine the correct voltages for each cpu and core frequency. Signed-off-by: Colin Cross <ccross@android.com>
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