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* ARM: 6411/1: vexpress: set RAM latencies to 1 cycle for PL310 on ct-ca9x4 tileWill Deacon2010-09-271-1/+7
| | | | | | | | | | | | | | | The PL310 on the ct-ca9x4 tile for the Versatile Express does not need to add additional latency when accessing its cache RAMs. Unfortunately, the boot monitor sets this up for an 8-cycle delay on reads and writes, resulting in greatly reduced memory performance when the L2 cache is enabled. This patch sets the L2 RAM latencies to the correct value of 1 cycle on the ct-ca9x4 tile before enabling the L2 cache. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr ↵Catalin Marinas2010-09-171-1/+1
| | | | | | | | | | | | | | | | | | | register Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: <stable@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-08-033-1/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (291 commits) ARM: AMBA: Add pclk support to AMBA bus infrastructure ARM: 6278/2: fix regression in RealView after the introduction of pclk ARM: 6277/1: mach-shmobile: Allow users to select HZ, default to 128 ARM: 6276/1: mach-shmobile: remove duplicate NR_IRQS_LEGACY ARM: 6246/1: mmci: support larger MMCIDATALENGTH register ARM: 6245/1: mmci: enable hardware flow control on Ux500 variants ARM: 6244/1: mmci: add variant data and default MCICLOCK support ARM: 6243/1: mmci: pass power_mode to the translate_vdd callback ARM: 6274/1: add global control registers definition header file for nuc900 mx2_camera: fix type of dma buffer virtual address pointer mx2_camera: Add soc_camera support for i.MX25/i.MX27 arm/imx/gpio: add spinlock protection ARM: Add support for the LPC32XX arch ARM: LPC32XX: Arch config menu supoport and makefiles ARM: LPC32XX: Phytec 3250 platform support ARM: LPC32XX: Misc support functions ARM: LPC32XX: Serial support code ARM: LPC32XX: System suspend support ARM: LPC32XX: GPIO, timer, and IRQ drivers ARM: LPC32XX: Clock driver ...
| *---. Merge branches 'at91', 'ep93xx', 'kexec', 'iop', 'lmb', 'nomadik', 'nuc', ↵Russell King2010-07-313-1/+9
| |\ \ \ | | | | | | | | | | | | | | | 'pl', 'spear' and 'versatile' into devel
| | | | * ARM: 6218/1: Versatile Express: add support for local timers on CA9X4 ↵Will Deacon2010-07-092-0/+3
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | daughterboard This patch adds support for the Cortex-A9 local timers available when using the CA9X4 daughterboard with the Versatile Express. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: AMBA: Add pclk definition for platforms using primecellsRussell King2010-07-221-1/+6
| | |/ | |/| | | | | | | | | | | | | | | | | | | Add a dummy clk definition for the APB pclk signal on all platforms using the AMBA bus infrastructure. This ensures that these platforms continue to work when the core amba bus code controls the APB pclk. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* / | ARM: Fix Versatile/Realview/VExpress MMC card detection senseRussell King2010-07-301-1/+1
|/ / | | | | | | | | | | | | | | | | The MMC card detection sense has become really confused with negations at various levels, leading to some platforms not detecting inserted cards. Fix this by converting everything to positive logic throughout, thereby getting rid of these negations. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB sectionCatalin Marinas2010-07-011-1/+2
| | | | | | | | | | | | | | | | When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | arm: update gfp/slab.h includesTejun Heo2010-06-281-0/+1
|/ | | | | | | | | | Implicit slab.h inclusion via percpu.h is about to go away. Make sure gfp.h or slab.h is included as necessary. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
* ARM: 6057/1: Realview: register PMU IRQs during board initialisationWill Deacon2010-05-022-0/+38
| | | | | | | | | This patch updates the initialisation routines for the Realview boards and the Versatile Express board [ca9x4 tile] so that they register their PMU IRQs with the PMU framework in the Kernel. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Add Versatile Express SMP supportRussell King2010-05-025-0/+278
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Add Versatile Express CA9x4 processor supportRussell King2010-05-024-0/+264
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Add Versatile Express supportRussell King2010-05-0217-0/+816
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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