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* arm64: dts: allwinner: Remove useless phy-names from EHCI and OHCIMaxime Ripard2019-04-171-2/+0
| | | | | | | | Neither the OHCI or EHCI bindings are using the phy-names property, so we can just drop it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: dts: allwinner: h6: Add MMC1 pinsOndrej Jirman2019-04-151-0/+11
| | | | | | | | | | | MMC1 is used on some H6 boards we want to support. Typical use is 4-bit SDIO interface with a WiFi chip. Add pin definitions for this use case. As this is the only possible configration for mmc1, make it the default one, too. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: dts: allwinner: h6: move MMC pinctrl to dtsiClément Péron2019-04-091-0/+4
| | | | | | | | | There is only one pinmuxing available for each MMC controller. Move the pinctrl to the SOC Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: dts: allwinner: h6: Add device node for SIDYangtao Li2019-04-051-0/+5
| | | | | | | | The device tree binding already lists compatible strings for H6 SoC, so add a device node for it. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: dts: allwinner: Fix pinctrl node namesMaxime Ripard2019-03-251-3/+3
| | | | | | | | | | | Some pinctrl node names for the A64 and H6 do not follow the convention that we switched to and enforced, most notably by using underscores in node names, which also trigger a DTC warning. Let's change that. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: dts: allwinner: h6: Add Video Engine nodeJernej Skrabec2019-03-191-0/+11
| | | | | | | | | This adds the Video engine node for H6. It can use whole DRAM range so there is no need for reserved memory node. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* Merge tag 'sunxi-dt64-for-5.1-2' of ↵Arnd Bergmann2019-02-151-11/+25
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Allwinner arm64 DT changes for 5.1, take 2 Our usual round of DT changes for the arm64 Allwinner SoCs: - Enabling of the various power supplies on most a64 boards - H6 SRAM controller support - A64 CSI support * tag 'sunxi-dt64-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: a64: Enable PMIC power supplies on various boards arm64: dts: allwinner: a64: teres-i: enable power supplies arm64: dts: allwinner: h6: Add support for the SRAM C1 section dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1 arm64: dts: allwinner: a64: Add A64 CSI controller arm64: dts: allwinner: h6: Move GIC device node fix base address ordering Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * arm64: dts: allwinner: h6: Add support for the SRAM C1 sectionJernej Skrabec2019-01-291-0/+14
| | | | | | | | | | | | | | | | | | | | Add a node for H6 SRAM C1 section. Manual calls it VE SRAM, but for consistency with older SoCs, SRAM C1 name is used. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| * arm64: dts: allwinner: h6: Move GIC device node fix base address orderingChen-Yu Tsai2019-01-281-11/+11
| | | | | | | | | | | | | | | | | | | | The GIC device node was placed out of order in the initial device tree submission. Move it so the nodes are correctly sorted by base address again. Fixes: e54be32d0273 ("arm64: allwinner: h6: add the basical Allwinner H6 DTSI file") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* | arm64: dts: Remove inconsistent use of 'arm,armv8' compatible stringRob Herring2019-01-301-4/+4
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: dts: allwinner: h6: fix EMAC compatible string sequenceIcenowy Zheng2018-11-201-2/+2
| | | | | | | | | | | | The SoC-specific compatible should come before the fallback compatible string when multiple compatible strings are present, but the sequence is wrong currently on H6 EMAC node (A64 fallback before H6 compatible). Fix the sequence. Fixes: c8ced5516d23 ("arm64: allwinner: h6: add EMAC device nodes") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: dts: allwinner: h6: add USB2-related device nodesIcenowy Zheng2018-11-151-0/+82
| | | | | | | | | | | Allwinner H6 has two USB2 ports, one OTG and one host-only. Add device tree nodes related to them. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* arm64: dts: allwinner: h6: Add HDMI pipelineJernej Skrabec2018-11-071-0/+201
| | | | | | | | | This commit adds all entries needed for HDMI to function properly. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> [added DE3 bus] Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: allwinner: h6: add EMAC device nodesIcenowy Zheng2018-11-051-0/+28
| | | | | | | | | Allwinner H6 SoC has an EMAC like the one in A64. Add device tree nodes for the H6 DTSI file. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: dts: allwinner: h6: add system controller device tree nodeIcenowy Zheng2018-09-121-0/+23
| | | | | | | | | | | As we have already binding for the H6 system controller, add its node to the device tree. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> [fixed compatible string] Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* arm64: allwinner: h6: add device tree nodes for MMC controllersIcenowy Zheng2018-07-191-0/+59
| | | | | | | | | The Allwinner H6 SoC have 3 MMC controllers. Add device tree nodes for them. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: dts: allwinner: h6: Use macros for R_CCU clock and reset indicesChen-Yu Tsai2018-07-171-3/+5
| | | | | | | | | | | | Now that the device tree binding headers for the R_CCU have been merged, we can use the macros, instead of raw numbers. Switch to R_CCU macros for clock and reset indices. Reviewed-by: Icenowy Zheng <icenowy@aosc.io> Tested-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* arm64: allwinner: h6: add R_I2C controllerIcenowy Zheng2018-05-041-0/+18
| | | | | | | | | | Allwinner H6 SoC has a R_I2C controller wired to the PL0/PL1 pins, which are used in the reference design to connect AXP805 PMIC. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: allwinner: h6: add R_INTC interrupt controllerIcenowy Zheng2018-05-041-0/+9
| | | | | | | | | | | Allwinner H6 SoC has also a R_INTC interrupt controller like Allwinner A64 SoC, but has its base address changed due to the memory map change in H6. Add it into the device tree. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: allwinner: h6: add node for R_PIO pin controllerIcenowy Zheng2018-05-041-0/+13
| | | | | | | | | | Allwinner H6 SoC has a R_PIO pin controller which controls PL and PM GPIO banks. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: allwinner: h6: add PRCM CCU device nodeIcenowy Zheng2018-05-041-0/+10
| | | | | | | | | Allwinner H6 has also a PRCM CCU. Add its device node into the device tree. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: allwinner: h6: restore the usage of CCU slice macrosIcenowy Zheng2018-04-231-9/+11
| | | | | | | | As the definition of CCU slice macros are already merged into the source tree, restore the usage of the macros now. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm64: allwinner: h6: add the basical Allwinner H6 DTSI fileIcenowy Zheng2018-03-191-0/+175
Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its memory map fully reworked and some high-speed peripherals (PCIe, USB 3.0) introduced. This commit adds the basical DTSI file of it, including the clock support and UART support. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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