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* arm64: dts: amlogic: add missing cache propertiesKrzysztof Kozlowski2023-05-091-0/+1
| | | | | | | | | | | | As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: meson-a1-ad401.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230421223211.115612-1-krzysztof.kozlowski@linaro.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: remove CPU opps below 1GHz for G12A boardsChristian Hewitt2023-01-191-20/+0
| | | | | | | | | | | | | | Amlogic G12A devices experience CPU stalls and random board wedges when the system idles and CPU cores clock down to lower opp points. Recent vendor kernels include a change to remove 100-250MHz and other distro sources also remove the 500/667MHz points. Unless all 100-667Mhz opps are removed or the CPU governor forced to performance stalls are still observed, so let's remove them to improve stability and uptime. Fixes: b190056fa9ee ("arm64: dts: meson-g12a: add cpus OPP table") Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Link: https://lore.kernel.org/r/20230119053031.21400-1-christianshewitt@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: Add DDR PMU nodeJiucheng Xu2022-11-151-0/+4
| | | | | | | | | Add DDR PMU device node for G12 series SoC Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20221109015818.194927-4-jiucheng.xu@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: Update cache properties for amlogicPierre Gondois2022-11-071-0/+1
| | | | | | | | | | | | | | | The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20221107155825.1644604-4-pierre.gondois@arm.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* arm64: dts: meson: g12a: add cooling propertiesGuillaume La Roque2019-10-171-0/+24
| | | | | | | | | | | | Add missing #colling-cells field for G12A SoC Add cooling-map for passive and hot trip point Tested-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12: factor the power domain.Jerome Brunet2019-10-031-13/+0
| | | | | | | | The power domain declared in the g12a and g12b dtsi are the same. Move the declaration of these power domains in the g12 common dtsi. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12: add a g12 layerJerome Brunet2019-10-031-1/+1
| | | | | | | | | While the sm1 is very close to the g12a/b family, somethings apply differently on the g12a/b and not the sm1. This introduce a new layer of dtsi for part which apply to the g12a and g12b but not the sm1. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-g12: add Everything-Else power domain controllerNeil Armstrong2019-08-291-0/+9
| | | | | | | | | | | | Replace the VPU-centric power domain controller by the generic system-wide Everything-Else power domain controller and setup the right power-domains properties on the VPU, Ethernet & USB nodes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> [khilman: minor subject edit: add dts] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-g12a: add cpus OPP tableNeil Armstrong2019-08-091-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the OPP table taken from the vendor u200 and u211 DTS. The Amlogic G12A SoC seems to available in 3 types : - low-speed: up to 1,8GHz - mid-speed: up to 1,908GHz - high-speed: up to 2.1GHz And the S905X2 opp voltages are slightly higher than the S905D2 OPP voltages for the low-speed table. This adds the conservative OPP table with the S905X2 higher voltages and the maximum low-speed OPP frequency. The values were tested to be stable on an Amlogic U200 Reference Board, SeiRobotics SEI510 and X96 Max Set-Top-Boxes running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsiNeil Armstrong2019-08-091-2402/+4
| | | | | | | | | | | | | | | | To simplify the representation of differences betweem the G12A and G12B SoCs, move the common nodes into a meson-g12-common.dtsi file and express the CPU nodes and differences in meson-g12a.dtsi and meson-g12b.dtsi. This separation will help for DVFS and future Amlogic SM1 Family support. The sd_emmc_a quirk is added in the g12a/g12b since since it's already known the sd_emmc_a controller is fixed in the next SM1 SoC family. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-g12a: add missing dwc2 phy-namesNeil Armstrong2019-08-051-0/+1
| | | | | | | | | | | | | | | | | The G12A USB2 OTG capable PHY uses a 8bit large UTMI bus, and the OTG controller gets the PHY but width by probing the associated phy. By default it will use 16bit wide settings if a phy is not specified, in our case we specified the phy, but not the phy-names. The dwc2 bindings specifies that if phys is present, phy-names shall be "usb2-phy". Adding phy-names = "usb2-phy" solves the OTG PHY bus configuration. Fixes: 9baf7d6be730 ("arm64: dts: meson: g12a: Add G12A USB nodes") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: sort sdio nodes correctlyJerome Brunet2019-06-191-37/+36
| | | | | | | | | Fix sdio node order in the soc device tree Fixes: a1737347250e ("arm64: dts: meson: g12a: add SDIO controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add the GPIO interrupt controllerMartin Blumenstingl2019-06-111-0/+9
| | | | | | | | | | | GPIO interrupts are used for the external Ethernet RGMII PHY interrupt line. Add the GPIO interrupt controller so we can describe that connection in the dts files. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add SDIO controllerJerome Brunet2019-06-111-0/+37
| | | | | | | | | | The Amlogic G12A SDIO Controller has a bug preventing direct DDR access, add the port A (SDIO) pinctrl and controller nodes and mark this specific controller with the amlogic,dram-access-quirk property. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: Add hwrng nodeNeil Armstrong2019-06-111-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Amlogic G12A has the hwrng module at the end of an unknown "EFUSE" bus. The hwrng is not enabled on the vendor G12A DTs, but is enabled on next generation SM1 SoC family sharing the exact same memory mapping. Let's add the "EFUSE" bus and the hwrng node. This hwrng has been checked with the rng-tools rngtest FIPS tool : rngtest: starting FIPS tests... rngtest: bits received from input: 1630240032 rngtest: FIPS 140-2 successes: 81436 rngtest: FIPS 140-2 failures: 76 rngtest: FIPS 140-2(2001-10-10) Monobit: 10 rngtest: FIPS 140-2(2001-10-10) Poker: 6 rngtest: FIPS 140-2(2001-10-10) Runs: 26 rngtest: FIPS 140-2(2001-10-10) Long run: 34 rngtest: FIPS 140-2(2001-10-10) Continuous run: 0 rngtest: input channel speed: (min=3.784; avg=5687.521; max=19073.486)Mibits/s rngtest: FIPS tests speed: (min=47.684; avg=52.348; max=52.835)Mibits/s rngtest: Program run time: 30000987 microseconds Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add drive strength for eth pinsNeil Armstrong2019-06-111-0/+2
| | | | | | | | | | With the X96 Max board using an external Gigabit Ethernet PHY, add the same driver strength to the Ethernet pins as the vendor tree. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add drive-strength hdmi ddc pinsNeil Armstrong2019-06-111-0/+1
| | | | | | | | | With the default boot settings, the DDC drive strength is too weak, set the driver-strengh to 4mA to avoid errors on the DDC line. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add mdio multiplexerJerome Brunet2019-06-111-0/+32
| | | | | | | | | Add the g12a mdio multiplexer which allows to connect to either an external phy through the SoC pins or the internal 10/100 phy Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add ethernet pinctrl definitionsJerome Brunet2019-06-111-0/+37
| | | | | | | | Add the ethernet pinctrl settings for RMII, RGMII and internal phy leds Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add ethernet mac controllerJerome Brunet2019-05-231-0/+21
| | | | | | | | Add the synopsys ethernet mac controller embedded in the g12a SoC family. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add tohdmitxJerome Brunet2019-05-211-0/+8
| | | | | | | | Add the hdmitx glue device linking the SoC audio interfaces to the embedded Synopsys hdmi controller. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: enable hdmi_tx sound dai providerJerome Brunet2019-05-211-0/+1
| | | | | | | | At the moment the sysnopsys hdmi i2s driver provides a single playback DAI. Add the corresponding sound-dai-cell to the hdmi device node. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add spdifinJerome Brunet2019-05-211-0/+37
| | | | | | | | Add the spdif input device node and the pinctrl definition for this capture interface g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add pdmJerome Brunet2019-05-211-0/+177
| | | | | | | | Add the pdm device node and the pinctrl definition for this capture interface g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add spdifoutsJerome Brunet2019-05-211-0/+60
| | | | | | | | Add the devices nodes and pinctrl definitions for the spdif outputs of the g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add tdmJerome Brunet2019-05-211-0/+658
| | | | | | | | Add the devices and pinctrl definitions for the tdm interfaces of the g12a SoC family. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add audio fifosJerome Brunet2019-05-211-0/+73
| | | | | | | Add the playback and capture memory interfaces of the g12a SoC family. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add audio memory arbitrerJerome Brunet2019-05-211-0/+9
| | | | | | | Add the audio DDR memory arbitrer of the g12a SoC family. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add audio clock controllerJerome Brunet2019-05-211-0/+36
| | | | | | | Add the g12a clock controller dedicated to audio. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add i2c nodesGuillaume La Roque2019-05-211-0/+268
| | | | | | | | Add pinctrl and nodes for i2c support on amlogic g12a Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: set uart_ao clocksJerome Brunet2019-05-211-2/+2
| | | | | | | | | | Now that the AO clock controller is available, make the uarts of the always-on domain claim the appropriate peripheral clock. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add mmc nodesJerome Brunet2019-05-211-0/+124
| | | | | | | | | | Add port B (sdcard) and port C (eMMC) pinctrl and controllers nodes to the g12a DT. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-g12a: Add IR nodesNeil Armstrong2019-05-211-0/+14
| | | | | | | | | Amlogic G12A SoCs uses the exact same IR decoder as previous families, add the IR node and the pintctrl setting. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-g12a: Add PWM nodesNeil Armstrong2019-05-211-0/+179
| | | | | | | | This adds the EE and AO PWM nodes and the possible pinctrl settings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-g12a: Add AO-CEC nodesNeil Armstrong2019-04-161-0/+34
| | | | | | | | | | | | | | Amlogic G12A embeds 2 CEC controllers : - AO-CEC-A the same controller as in GXBB, GXL & GXM SoCs - AO-CEC-B is a new controller Note, the two controller can work simultanously since 2 Pads can handle CEC, thus this SoC can handle 2 distinct CEC busses. This patch adds the nodes for the AO-CEC-A and AO-CEC-B controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-g12a: Add VPU and HDMI related nodesNeil Armstrong2019-04-161-0/+131
| | | | | | | Add VPU and HDMI display support. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: Add mali-g31 gpu nodeNeil Armstrong2019-04-151-0/+27
| | | | | | | This patch adds the ARM Mali G31 GPU node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: Add G12A USB nodesNeil Armstrong2019-04-151-0/+75
| | | | | | | | | | | | | | This patch adds the nodes for the USB Complex found in the Amlogic G12A SoC. It includes the : - 2 USB2 PHYs - 1 USB3 + PCIE Combo PHY - the USB Glue with it's DWC2 and DWC3 sub-nodes Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: Add SAR ADC nodeNeil Armstrong2019-04-151-0/+15
| | | | | | | | This patch adds the SAR ADC controller node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-g12a: Add CMA reserved memoryNeil Armstrong2019-03-291-0/+8
| | | | | | | | In order to handle Video Output and later on Video decoding, add a reserved CMA pool with a similar 256MiB size as other SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: Add UART A, B & C nodes and pinsNeil Armstrong2019-03-221-0/+72
| | | | | | | | | This patch adds the 3 UART nodes in the EE power domain with the corresponding pinctrl nodes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add reset controllerJerome Brunet2019-03-221-0/+7
| | | | | | | | | Add the reset controller device of g12a SoC family Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add uart_ao_a pinctrlJerome Brunet2019-03-221-0/+18
| | | | | | | | | Add the always on UART pinctrl setting to the g12a soc DT. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add pinctrl support controllersJerome Brunet2019-03-221-0/+42
| | | | | | | | Add the peripheral and always-on pinctrl controllers to the g12a soc. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: Add AO Clock + Reset Controller supportNeil Armstrong2019-03-221-0/+17
| | | | | | | | Add nodes and properties for the AO Clocks and Resets. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add efuseJerome Brunet2019-03-181-0/+9
| | | | | | | Add the g12a SoC efuse device Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson: g12a: add secure monitorJerome Brunet2019-03-181-0/+4
| | | | | | | Add the interface to the secure monitor on g12a Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* arm64: dts: meson-g12a: Add AO Secure nodeNeil Armstrong2019-03-181-0/+6
| | | | | | | | This adds the Always-On ao-secure system control registers node, which is used by the meson-gx-socinfo driver to detect the SoC IDs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* Merge tag 'amlogic-dt64' of ↵Arnd Bergmann2019-02-151-21/+41
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.1 - new board: G12a-based x96 max - G12a: add peripheral clock controller and clock measure support - s400: fix SD/eMMC max rate issues - s400: audio: add sp/dif in support - GX: support simplefb * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson: add g12a x96 max board dt-bindings: arm: amlogic: add amediatech x96-max bindings arm64: dts: meson: g12a: add peripheral clock controller arm64: dts: meson: g12a: add clk measure support arm64: dts: meson: axg: add clk measure support arm64: dts: meson: fix g12a buses arm64: dts: meson-axg: add efuse device arm64: dts: meson: s400: fix emmc maximum rate arm64: dts: meson: s400: enable sdr104 on sdio arm64: dts: meson-gx: add support for simplefb dt-bindings: meson: add specific simplefb bindings arm64: dts: meson-gx: Add canvas provider node to the vpu arm64: dts: meson-axg: s400: add spdifin to the sound card arm64: dts: meson-axg: s400: add spdif-dir codec arm64: dts: meson-axg: add spdifin Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * arm64: dts: meson: g12a: add peripheral clock controllerJerome Brunet2019-02-081-0/+13
| | | | | | | | | | | | | | Add the peripheral clock controller to the g12a SoC DT Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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