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* arm64: dts: qcom: sc7280: assign DSI clock source parentsRajeev Nandan2022-10-171-0/+3
| | | | | | | | | Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662550553-28933-1-git-send-email-quic_rajeevny@quicinc.com
* arm64: dts: qcom: sm8250: Drop redundant phy-names from DSI controllerBryan O'Donoghue2022-10-171-2/+0
| | | | | | | | | | phy-names has been marked deprecated. Remove it from the sm8250 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-12-bryan.odonoghue@linaro.org
* arm64: dts: qcom: sdm845: Drop redundant phy-names from DSI controllerBryan O'Donoghue2022-10-171-2/+0
| | | | | | | | | | | phy-names has been marked deprecated. Remove it from the sdm845 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-11-bryan.odonoghue@linaro.org
* arm64: dts: qcom: sdm630: Drop redundant phy-names from DSI controllerBryan O'Donoghue2022-10-171-1/+0
| | | | | | | | | | phy-names has been marked deprecated. Remove it from the sdm630 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-10-bryan.odonoghue@linaro.org
* arm64: dts: qcom: sdm660: Drop redundant phy-names from DSI controllerBryan O'Donoghue2022-10-171-1/+0
| | | | | | | | | | phy-names has been marked deprecated. Remove it from the sdm660 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-9-bryan.odonoghue@linaro.org
* arm64: dts: qcom: sc7280: Drop redundant phy-names from DSI controllerBryan O'Donoghue2022-10-171-1/+0
| | | | | | | | | | phy-names has been marked deprecated. Remove it from the sc7280 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-8-bryan.odonoghue@linaro.org
* arm64: dts: qcom: sc7180: Drop redundant phy-names from DSI controllerBryan O'Donoghue2022-10-171-1/+0
| | | | | | | | | | phy-names has been marked deprecated. Remove it from the sc7180 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-7-bryan.odonoghue@linaro.org
* arm64: dts: qcom: msm8996: Drop redundant phy-names from DSI controllerBryan O'Donoghue2022-10-171-2/+0
| | | | | | | | | | phy-names has been marked deprecated. Remove it from the msm8996 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-6-bryan.odonoghue@linaro.org
* arm64: dts: qcom: msm8916: Drop redundant phy-names from DSI controllerBryan O'Donoghue2022-10-171-1/+0
| | | | | | | | | | phy-names has been marked deprecated. Remove it from the msm8916 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-5-bryan.odonoghue@linaro.org
* arm64: dts: qcom: sc7280: Update SNPS Phy params for SC7280 IDP deviceKrishna Kurapati2022-10-171-0/+6
| | | | | | | | | Overriding the SNPS Phy tuning parameters for SC7280 IDP device. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662480933-12326-4-git-send-email-quic_kriskura@quicinc.com
* arm64: dts: qcom: sc7180: Configure USB as wakeup sourceMatthias Kaehlcke2022-10-171-0/+2
| | | | | | | | | | The dwc3 USB controller of the sc7180 supports USB remote wakeup, configure it as a wakeup source. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220901102946.v2.1.I347ea409ee3134bd32a29e33fecd1a6ef32085a0@changeid
* arm64: dts: qcom: sm8450: Add description of camera control interfacesVladimir Zapolskiy2022-10-171-0/+142
| | | | | | | | | Add description of two CCI controllers found on QCOM SM8450. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220901073504.3077363-1-vladimir.zapolskiy@linaro.org
* arm64: dts: qcom: Add sc7180-pazquel360Yunlong Jia2022-10-174-0/+91
| | | | | | | | | | | | | Create first version device tree for pazquel360 pazquel360 is convertible and the pazquel it is based on is clamshell. sku 20 for lte & wifi sku 21 for wifi only sku 22 for lte w/o esim & wifi Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220901024827.v3.2.Iea2d2918adfff2825b87d428b5732717425c196f@changeid
* arm64: dts: qcom: sdm845: add displayport nodeDmitry Baryshkov2022-10-171-2/+80
| | | | | | | | | | Add displayport controller device node, describing DisplayPort hardware block on SDM845. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220810035424.2796777-3-bjorn.andersson@linaro.org
* arm64: dts: qcom: sdm845: switch usb_1 phy to use combo usb+dp phyDmitry Baryshkov2022-10-171-7/+18
| | | | | | | | | | Change sdm845's usb_1_qmpphy to use combo usb+dp phy bindings, rather than just usb phy. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220810035424.2796777-2-bjorn.andersson@linaro.org
* arm64: dts: qcom: msm8916: Drop MSS fallback compatibleStephan Gerhold2022-10-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | MSM8916 was originally using the "qcom,q6v5-pil" compatible for the MSS remoteproc. Later it was decided to use SoC-specific compatibles instead, so "qcom,msm8916-mss-pil" is now the preferred compatible. Commit 60a05ed059a0 ("arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS") updated the MSM8916 device tree to make use of the new compatible but still kept the old "qcom,q6v5-pil" as fallback. This is inconsistent with other SoCs and conflicts with the description in the binding documentation (which says that only one compatible should be present). Also, it has no functional advantage since older kernels could not handle this DT anyway (e.g. "power-domains" in the MSS node is only supported by kernels that also support "qcom,msm8916-mss-pil"). Make this consistent with other SoCs by using only the "qcom,msm8916-mss-pil" compatible. Fixes: 60a05ed059a0 ("arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS") Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220718140344.1831731-2-stephan.gerhold@kernkonzept.com
* arm64: dts: qcom: correct white-space before {Krzysztof Kozlowski2022-10-1710-25/+25
| | | | | | | | | Add missing space or remove redundant one before opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220919163333.129989-1-krzysztof.kozlowski@linaro.org
* arm64: dts: qcom: sm8250-edo: Add NXP PN553 NFCKonrad Dybcio2022-10-171-1/+10
| | | | | | | | | | Add a node for NXP PN553 NFC, using the nxp-nci driver. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221008181714.253634-1-konrad.dybcio@somainline.org
* arm64: dts: qcom: sdm845-cheza: fix AP suspend pin biasKrzysztof Kozlowski2022-10-171-2/+2
| | | | | | | | | | | There is no "bias-no-pull" property. Assume intentions were disabling bias. Fixes: 79e7739f7b87 ("arm64: dts: qcom: sdm845-cheza: add initial cheza dt") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221010114417.29859-3-krzysztof.kozlowski@linaro.org
* arm64: dts: qcom: sdm845-db845c: correct SPI2 pins drive strengthKrzysztof Kozlowski2022-10-171-1/+4
| | | | | | | | | | | | | | | | | | | The pin configuration (done with generic pin controller helpers and as expressed by bindings) requires children nodes with either: 1. "pins" property and the actual configuration, 2. another set of nodes with above point. The qup_spi2_default pin configuration uses alreaady the second method with a "pinmux" child, so configure drive-strength similarly in "pinconf". Otherwise the PIN drive strength would not be applied. Fixes: 8d23a0040475 ("arm64: dts: qcom: db845c: add Low speed expansion i2c and spi nodes") Cc: <stable@vger.kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221010114417.29859-2-krzysztof.kozlowski@linaro.org
* arm64: dts: qcom: sdm630: fix UART1 pin biasKrzysztof Kozlowski2022-10-171-1/+1
| | | | | | | | | | | There is no "bias-no-pull" property. Assume intentions were disabling bias. Fixes: b190fb010664 ("arm64: dts: qcom: sdm630: Add sdm630 dts file") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221010114417.29859-1-krzysztof.kozlowski@linaro.org
* arm64: dts: qcom: ipq8074-hk01: add VQMMC supplyRobert Marko2022-10-171-0/+2
| | | | | | | | | | | | | Since now we have control over the PMP8074 PMIC providing various system voltages including L11 which provides the SDIO/eMMC I/O voltage set it as the SDHCI VQMMC supply. This allows SDHCI controller to switch to 1.8V I/O mode and support high speed modes like HS200 and HS400. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com
* arm64: dts: qcom: add PMP8074 DTSIRobert Marko2022-10-171-0/+125
| | | | | | | | | | | | | | PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is controlled via SPMI. Add DTSI for it providing GPIO, regulator, RTC and VADC support. RTC is disabled by default as there is no built-in battery so it will loose time unless board vendor added a battery, so make it optional. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
* arm64: dts: qcom: ipq8074: add clocks to APCSRobert Marko2022-10-171-0/+2
| | | | | | | | | | | | APCS now has support for providing the APSS clocks as the child device for IPQ8074. So, add the A53 PLL and XO clocks in order to use APCS as the CPU clocksource for APSS scaling. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
* Merge branch '20220818220628.339366-8-robimarko@gmail.com' into HEADBjorn Andersson2022-10-171-1/+1
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| * arm64: dts: qcom: ipq8074: correct APCS register space sizeRobert Marko2022-10-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | APCS DTS addition that was merged, was not supposed to get merged as it was part of patch series that was superseded by 2 more patch series that resolved issues with this one and greatly simplified things. Since it already got merged, start by correcting the register space size as APCS will not be providing regmap for PLL and it will conflict with the standalone A53 PLL node. Fixes: 50ed9fffec3a ("arm64: dts: qcom: ipq8074: add APCS node") Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-8-robimarko@gmail.com
* | arm64: dts: qcom: ipq8074: add thermal nodesRobert Marko2022-10-171-0/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | IPQ8074 has a tsens v2.3.0 peripheral which monitors temperatures around the various subsystems on the die. So lets add the tsens and thermal zone nodes, passive CPU cooling will come in later patches after CPU frequency scaling is supported. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
* | arm64: dts: qcom: msm8996pro: expand Adreno OPP tableDmitry Baryshkov2022-10-171-0/+25
| | | | | | | | | | | | | | | | | | | | | | There are minor differeces between msm8996 and msm8996pro in terms of GPU frequencies support. For example msm8996pro supports 652.8 MHz frequency for the Adreno. Reclect these differences in msm8996pro.dtsi. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-8-dmitry.baryshkov@linaro.org
* | arm64: dts: qcom: msm8996: fix GPU OPP tableDmitry Baryshkov2022-10-171-5/+5
| | | | | | | | | | | | | | | | | | | | | | Fix Adreno OPP table according to the msm-3.18. Enable 624 MHz for the speed bin 3 and 560 MHz for bins 2 and 3. Fixes: 69cc3114ab0f ("arm64: dts: Add Adreno GPU definitions") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-7-dmitry.baryshkov@linaro.org
* | arm64: dts: qcom: msm8996: add support for speed bin 3Dmitry Baryshkov2022-10-171-37/+37
| | | | | | | | | | | | | | | | | | | | | | Add support for msm8996, speed bin 3. It supports full range of frequencies on the power cluster, but is limited to 1.8 GHz on performance cluster. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-6-dmitry.baryshkov@linaro.org
* | arm64: dts: qcom: msm8996: fix supported-hw in cpufreq OPP tablesDmitry Baryshkov2022-10-171-9/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | Adjust MSM8996 cpufreq tables according to tables in msm-3.18. Some of the frequencies are not supported on speed bins other than 0. Also other speed bins support intermediate topmost frequencies, not supported on speed bin 0. Implement all these differencies. Fixes: 90173a954a22 ("arm64: dts: qcom: msm8996: Add CPU opps") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-5-dmitry.baryshkov@linaro.org
* | arm64: dts: qcom: msm8996-xiaomi-scorpio, natrium: Use MSM8996 ProYassine Oudjana2022-10-175-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Xiaomi Mi Note 2 has the MSM8996 Pro SoC. Rename the dts to match, include msm8996pro.dtsi, and add the qcom,msm8996pro compatible. To do that, the msm8996.dtsi include in msm8996-xiaomi-common has to be moved to msm8996-xiaomi-gemini, the only device that needs it included after this change. Since MSM8996Pro is largely compatible with MSM8996, keep old compatible too rather than insiting on qcom,msm8996pro only. This allows the code that doesn't yet know about msm8996pro to continue supporting these devices. [DB: Dropped msm-id changes.] Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> [DB: Applied the same change to Xiaomi Mi 5s Plus (natrium).] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-4-dmitry.baryshkov@linaro.org
* | arm64: dts: qcom: msm8996: Add MSM8996 Pro supportYassine Oudjana2022-10-172-41/+307
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Qualcomm MSM8996 Pro is a variant of MSM8996 with higher frequencies supported both on CPU and GPU. There are other minor hardware differencies in the CPU and GPU regulators and bus fabrics. However this results in significant differences between 8996 and 8996 Pro CPU OPP tables. Judging from msm-3.18 there are only few common frequencies supported by both msm8996 and msm8996pro. Rather than hacking the tables for msm8996, split msm8996pro support into a separate file. Later this would allow having additional customizations for the CBF, CPR, retulators, etc. [DB: dropped all non-CPU-OPP changes] Fixes: 90173a954a22 ("arm64: dts: qcom: msm8996: Add CPU opps") Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> [DB: Realigned supported-hw to keep compat with current cpufreq driver] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-3-dmitry.baryshkov@linaro.org
* | arm64: dts: qcom: sc7280: Include sc7280-herobrine-audio-rt5682.dtsi in ↵Judy Hsiao2022-10-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | herobrine-r1 Include sc7280-herobrine-audio-rt5682.dtsi in herobrine-r1 as it uses rt5682 codec. Signed-off-by: Judy Hsiao <judyhsiao@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220721083849.1571744-4-judyhsiao@chromium.org
* | arm64: dts: qcom: sc7280: Add sc7280-herobrine-audio-rt5682.dtsiJudy Hsiao2022-10-171-0/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | Audio dtsi for sc7280 boards that using rt5682 headset codec: 1. Add dt nodes for sound card which use I2S playback and record through rt5682s and I2S playback through max98357a. 2. Enable lpass cpu node and add pin control and dai-links. Signed-off-by: Judy Hsiao <judyhsiao@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220721083849.1571744-3-judyhsiao@chromium.org
* | arm64: dts: qcom: sc7280: herobrine: Add pinconf settings for mi2s1Judy Hsiao2022-10-171-0/+15
| | | | | | | | | | | | | | | | | | | | | | 1. Add drive strength property for mi2s1 on sc7280 based platforms. 2. Disable the pull-up for mi2s1 lines. Signed-off-by: Judy Hsiao <judyhsiao@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220721083849.1571744-2-judyhsiao@chromium.org
* | arm64: dts: qcom: sc7280: Add required-opps for i2cRajendra Nayak2022-10-171-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qup-i2c devices on sc7280 are clocked with a fixed clock (19.2 MHz) Though qup-i2c does not support DVFS, it still needs to vote for a performance state on 'CX' to satisfy the 19.2 Mhz clock frequency requirement. Use 'required-opps' to pass this information from device tree, and also add the power-domains property to specify the CX power-domain. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220927104233.29376-1-quic_rjendra@quicinc.com
* | arm64: dts: qcom: sc7180: Add required-opps for USBRajendra Nayak2022-10-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB has a requirement to put a performance state vote on 'cx' while active. Use 'required-opps' to pass this information from device tree, and since all the GDSCs in GCC (including USB) are sub-domains of cx, we also add cx as a power-domain for GCC. Now when any of the consumers of the GDSCs (in this case USB) votes on a perforamance state, genpd framework can identify that the GDSC itself does not support a performance state and it then propogates the vote to the parent, which in this case is cx. This change would also mean that any GDSC in GCC thats left enabled during low power state (perhaps because its marked with a ALWAYS_ON flag) can prevent the system from entering low power since that would prevent cx from transitioning to low power. Ideally any consumers that would need to have their devices (partially) powered to support wakeups should look at making the resp. GDSCs transtion to a Retention (PWRSTS_RET) state instead of leaving them ALWAYS_ON. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220927102646.14785-1-quic_rjendra@quicinc.com
* | arm64: dts: qcom: sc7280: Update SNPS Phy params for SC7280Krishna Kurapati2022-10-171-0/+7
| | | | | | | | | | | | | | | | | | | | Add SNPS HS Phy tuning parameters for herobrine variant of SC7280 devices. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1664462290-29869-1-git-send-email-quic_kriskura@quicinc.com
* | arm64: dts: qcom: sdm845-xiaomi-polaris: fix codec pin conf nameKrzysztof Kozlowski2022-10-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix typo in the codec's pin name to be configured. Mismatched name caused the pin configuration to be ignored. Fixes: be497abe19bf ("arm64: dts: qcom: Add support for Xiaomi Mi Mix2s") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Molly Sophia <mollysophia379@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192039.240486-3-krzysztof.kozlowski@linaro.org
* | arm64: dts: qcom: sdm850-samsung-w737: correct I2C12 pins drive strengthKrzysztof Kozlowski2022-10-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin configuration (done with generic pin controller helpers and as expressed by bindings) requires children nodes with either: 1. "pins" property and the actual configuration, 2. another set of nodes with above point. The qup_i2c12_default pin configuration used second method - with a "pinmux" child. Fixes: d4b341269efb ("arm64: dts: qcom: Add support for Samsung Galaxy Book2") Cc: <stable@vger.kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192039.240486-2-krzysztof.kozlowski@linaro.org
* | arm64: dts: qcom: sdm850-lenovo-yoga-c630: correct I2C12 pins drive strengthKrzysztof Kozlowski2022-10-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pin configuration (done with generic pin controller helpers and as expressed by bindings) requires children nodes with either: 1. "pins" property and the actual configuration, 2. another set of nodes with above point. The qup_i2c12_default pin configuration used second method - with a "pinmux" child. Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Cc: <stable@vger.kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192039.240486-1-krzysztof.kozlowski@linaro.org
* | arm64: dts: qcom: sm6125: align TLMM pin configuration with DT schemaKrzysztof Kozlowski2022-10-171-2/+2
| | | | | | | | | | | | | | | | | | | | DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192954.242546-11-krzysztof.kozlowski@linaro.org
* | arm64: dts: qcom: sm6125-sony-xperia: add missing SD CD GPIO functionsKrzysztof Kozlowski2022-10-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add default GPIO function to SD card detect pins on SM6125 Sony Xperia, as required by bindings: qcom/sm6125-sony-xperia-seine-pdx201.dtb: pinctrl@500000: sdc2-off-state: 'oneOf' conditional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'clk-pins', 'cmd-pins', 'data-pins', 'sd-cd-pins' do not match any of the regexes: 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192954.242546-10-krzysztof.kozlowski@linaro.org
* | arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schemaKrzysztof Kozlowski2022-10-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sdm845-lg-judyln.dtb: gpios@c000: 'vol-up-active-pins' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192954.242546-9-krzysztof.kozlowski@linaro.org
* | arm64: dts: qcom: msm8953: align TLMM pin configuration with DT schemaKrzysztof Kozlowski2022-10-171-35/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sdm632-fairphone-fp3.dtb: pinctrl@1000000: 'cd-off-pins', 'cd-on-pins', 'gpio-key-default-pins', .... do not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192954.242546-8-krzysztof.kozlowski@linaro.org
* | arm64: dts: qcom: sc7280-idp-ec-h1: add missing QUP GPIO functionsKrzysztof Kozlowski2022-10-171-0/+2
| | | | | | | | | | | | | | | | | | | | Add default GPIO function to SPI10 and SPI14 chip-select pins on SC7280 IDP, as required by bindings. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192954.242546-7-krzysztof.kozlowski@linaro.org
* | arm64: dts: qcom: sc7280-herobrine: correct number of gpio-line-namesKrzysztof Kozlowski2022-10-174-3/+1
| | | | | | | | | | | | | | | | | | There are 175 GPIOs (gpio0-174). Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192954.242546-6-krzysztof.kozlowski@linaro.org
* | arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schema (really)Krzysztof Kozlowski2022-10-176-211/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. I already tried to do this in commit d801357a0573 ("arm64: dts: qcom: sc7280: align TLMM pin configuration with DT schema") and I missed the fact that these nodes were not part of "state" node. Bindings did not catch these errors due to its own issues. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192954.242546-5-krzysztof.kozlowski@linaro.org
* | arm64: dts: qcom: sc8280xp: align TLMM pin configuration with DT schemaKrzysztof Kozlowski2022-10-172-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. qcom/sc8280xp-crd.dtb: pinctrl@f100000: kybd-default-state: 'oneOf' conditional failed, one must be fixed: 'pins' is a required property 'function' is a required property 'disable', 'int-n', 'reset' do not match any of the regexes: 'pinctrl-[0-9]+' 'disable', 'int-n', 'reset' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+' Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220930192954.242546-4-krzysztof.kozlowski@linaro.org
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-19 17:53:27 +0000