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* Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2023-05-012-0/+5
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| * arm64: Add HAS_ECV_CNTPOFF capabilityMarc Zyngier2023-03-301-0/+1
| * arm64: Add CNTPOFF_EL2 register definitionMarc Zyngier2023-03-301-0/+4
* | arm64/sysreg: Convert HFGITR_EL2 to automatic generationMark Brown2023-04-171-0/+65
* | arm64/sysreg: Update ID_AA64PFR1_EL1 for DDI0601 2022-12Mark Brown2023-04-061-1/+24
* | arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generationMark Brown2023-04-061-0/+75
* | arm64/sysreg: allow *Enum blocks in SysregFields blocksMark Rutland2023-04-061-37/+58
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* Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds2023-02-253-1/+37
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| * Merge branch kvm-arm64/nv-prefix into kvmarm/nextOliver Upton2023-02-131-0/+1
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| | * arm64: Add ARM64_HAS_NESTED_VIRT cpufeatureJintack Lim2023-02-111-0/+1
| * | Merge branch kvm-arm64/virtual-cache-geometry into kvmarm/nextOliver Upton2023-02-132-1/+36
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| | * | arm64/sysreg: Add CCSIDR2_EL1Akihiko Odaki2023-01-121-0/+5
| | * | arm64/sysreg: Convert CCSIDR_EL1 to automatic generationAkihiko Odaki2023-01-121-0/+10
| | * | arm64: Allow the definition of UNKNOWN system register fieldsMarc Zyngier2023-01-122-1/+21
| * | | Merge branch arm64/for-next/sme2 into kvmarm/nextOliver Upton2023-02-132-4/+24
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* | | | Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds2023-02-213-195/+400
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| * | | Merge branch 'for-next/sysreg-hwcaps' into for-next/coreCatalin Marinas2023-02-102-190/+220
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| | * | | arm64/sysreg: Initial unsigned annotations for ID registersMark Brown2023-02-011-188/+189
| | * | | arm64/sysreg: Initial annotation of signed ID registersMark Brown2023-02-011-2/+2
| | * | | arm64/sysreg: Allow enumerations to be declared as signed or unsignedMark Brown2023-02-011-0/+29
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| | *-. | | Merge branches 'for-next/sysreg', 'for-next/compat-hwcap' and 'for-next/sme2'...Catalin Marinas2023-02-012-4/+24
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| *-----. \ \ \ Merge branches 'for-next/sysreg', 'for-next/sme', 'for-next/kselftest', 'for-...Catalin Marinas2023-02-102-10/+46
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| | | | | * arm64: add ARM64_HAS_GIC_PRIO_RELAXED_SYNC cpucapMark Rutland2023-01-311-0/+1
| | | | | * arm64: rename ARM64_HAS_IRQ_PRIO_MASKING to ARM64_HAS_GIC_PRIO_MASKINGMark Rutland2023-01-311-1/+1
| | | | | * arm64: rename ARM64_HAS_SYSREG_GIC_CPUIF to ARM64_HAS_GIC_CPUIF_SYSREGSMark Rutland2023-01-311-1/+1
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| | | | * arm64/sme: Add basic enumeration for SME2Mark Brown2023-01-201-0/+1
| | | | * arm64/sysreg: Update system registers for SME 2 and 2.1Mark Brown2023-01-201-4/+23
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| | * | arm64/sysreg: Add definition of ISR_EL1Mark Brown2023-01-121-0/+10
| | * | arm64/sysreg: Add definition for ICC_NMIAR1_EL1Mark Brown2023-01-121-0/+5
| | * | arm64/sysreg: Fix errors in 32 bit enumeration valuesMark Brown2023-01-121-4/+4
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| * / arm64/sysreg: Convert SPE registers to automatic generationRob Herring2023-01-191-0/+139
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* / arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruptionAnshuman Khandual2023-01-061-0/+1
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* Revert "arm64: errata: Workaround possible Cortex-A715 [ESR|FAR]_ELx corruption"Will Deacon2022-12-151-1/+0
* Merge branch 'for-next/sysregs' into for-next/coreWill Deacon2022-12-062-1/+755
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| * arm64/sysreg: Convert ID_DFR1_EL1 to automatic generationJames Morse2022-12-011-0/+13
| * arm64/sysreg: Convert ID_DFR0_EL1 to automatic generationJames Morse2022-12-011-0/+50
| * arm64/sysreg: Convert ID_AFR0_EL1 to automatic generationJames Morse2022-12-011-0/+8
| * arm64/sysreg: Convert ID_MMFR5_EL1 to automatic generationJames Morse2022-12-011-0/+12
| * arm64/sysreg: Convert MVFR2_EL1 to automatic generationJames Morse2022-12-011-0/+17
| * arm64/sysreg: Convert MVFR1_EL1 to automatic generationJames Morse2022-12-011-0/+39
| * arm64/sysreg: Convert MVFR0_EL1 to automatic generationJames Morse2022-12-011-0/+39
| * arm64/sysreg: Convert ID_PFR2_EL1 to automatic generationJames Morse2022-12-011-0/+16
| * arm64/sysreg: Convert ID_PFR1_EL1 to automatic generationJames Morse2022-12-011-0/+40
| * arm64/sysreg: Convert ID_PFR0_EL1 to automatic generationJames Morse2022-12-011-0/+41
| * arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generationJames Morse2022-12-011-0/+32
| * arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generationJames Morse2022-12-011-0/+34
| * arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generationJames Morse2022-12-011-0/+39
| * arm64/sysreg: Convert ID_ISAR3_EL1 to automatic generationJames Morse2022-12-011-0/+38
| * arm64/sysreg: Convert ID_ISAR2_EL1 to automatic generationJames Morse2022-12-011-0/+46
| * arm64/sysreg: Convert ID_ISAR1_EL1 to automatic generationJames Morse2022-12-011-0/+39
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