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* Merge tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds2019-07-171-0/+11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Paul Burton: "A light batch this time around but significant improvements for certain systems: - Removal of readq & writeq for MIPS32 kernels where they would simply BUG() anyway, allowing drivers or other code that #ifdefs on their presence to work properly. - Improvements for Ingenic JZ4740 systems, including support for the external memory controller & pinmuxing fixes for qi_lb60/NanoNote systems. - Improvements for Lantiq systems, in particular around SMP & IPIs. - DT updates for ralink/MediaTek MT7628a systems to probe & configure a bunch more devices. - Miscellaneous cleanups & build fixes" * tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MIPS: fix some more fall through errors in arch/mips MIPS: perf events: handle switch statement falling through warnings mips/kprobes: Export kprobe_fault_handler() MAINTAINERS: Add myself as Ingenic SoCs maintainer MIPS: ralink: mt7628a.dtsi: Add watchdog controller DT node MIPS: ralink: mt7628a.dtsi: Add SPI controller DT node MIPS: ralink: mt7628a.dtsi: Add GPIO controller DT node MIPS: ralink: mt7628a.dtsi: Add pinctrl DT properties to the UART nodes MIPS: ralink: mt7628a.dtsi: Add pinmux DT node MIPS: ralink: mt7628a.dtsi: Add SPDX GPL-2.0 license identifier MIPS: lantiq: Add SMP support for lantiq interrupt controller MIPS: lantiq: Shorten register names, remove unused macros MIPS: lantiq: Fix bitfield masking MIPS: lantiq: Remove unused macros MIPS: lantiq: Fix attributes of of_device_id structure MIPS: lantiq: Change variables to the same type as the source MIPS: lantiq: Move macro directly to iomem function mips: Remove q-accessors from non-64bit platforms FDDI: defza: Include linux/io-64-nonatomic-lo-hi.h MIPS: configs: Remove useless UEVENT_HELPER_PATH ...
| * mips: Remove q-accessors from non-64bit platformsSerge Semin2019-06-241-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are some generic drivers in the kernel, which make use of the q-accessors or their derivatives. While at current asm/io.h the accessors are defined, their implementation is only applicable either for 64bit systems, or for systems with cpu_has_64bits flag set. Obviously there are MIPS systems which are neither of these, but still need to have those drivers supported. In this case the solution is to define some generic versions of the q-accessors, but with a limitation to be non-atomic. Such accessors are defined in the io-64-nonatomic-{hi-lo,lo-hi}.h file. The drivers which utilize the q-suffixed IO-methods are supposed to include the header file, so in case if these accessors aren't defined for the platform, the generic non-atomic versions are utilized. Currently the MIPS-specific asm/io.h file provides the q-accessors for any MIPS system even for ones, which in fact don't support them and raise BUG() in case if any of them is called. Due to this the generic versions of the accessors are never used while an attempt to call the IO-methods causes the kernel BUG(). In order to fix this we need to define the q-accessors only for the MIPS systems, which actually support them, and don't define them otherwise, so to let the corresponding drivers to use the non-atomic q-suffixed accessors. Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Suggested-by: Arnd Bergmann <arnd@arndb.de> Cc: Vadim V. Vlasov <vadim.vlasov@t-platforms.ru> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Serge Semin <Sergey.Semin@t-platforms.ru> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
* | arch/*: remove unused isa_page_to_bus()Stephen Kitt2019-07-161-2/+0
|/ | | | | | | | | | | isa_page_to_bus() is deprecated and is no longer used anywhere. Remove it entirely. Link: http://lkml.kernel.org/r/20190613161155.16946-1-steve@sk2.org Signed-off-by: Stephen Kitt <steve@sk2.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* mips/mmiowb: Add unconditional mmiowb() to arch_spin_unlock()Will Deacon2019-04-081-3/+0
| | | | | | | | | | | | | | | The mmiowb() macro is horribly difficult to use and drivers will continue to work most of the time if they omit a call when it is required. Rather than rely on driver authors getting this right, push mmiowb() into arch_spin_unlock() for mips. If this is deemed to be a performance issue, a subsequent optimisation could make use of ARCH_HAS_MMIOWB to elide the barrier in cases where no I/O writes were performed inside the critical section. Acked-by: Paul Burton <paul.burton@mips.com> Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* MIPS: Avoid using .set mips0 to restore ISAPaul Burton2018-11-091-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently have 2 commonly used methods for switching ISA within assembly code, then restoring the original ISA. 1) Using a pair of .set push & .set pop directives. For example: .set push .set mips32r2 <some_insn> .set pop 2) Using .set mips0 to restore the ISA originally specified on the command line. For example: .set mips32r2 <some_insn> .set mips0 Unfortunately method 2 does not work with nanoMIPS toolchains, where the assembler rejects the .set mips0 directive like so: Error: cannot change ISA from nanoMIPS to mips0 In preparation for supporting nanoMIPS builds, switch all instances of method 2 in generic non-platform-specific code to use push & pop as in method 1 instead. The .set push & .set pop is arguably cleaner anyway, and if nothing else it's good to consistently use one method. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21037/ Cc: linux-mips@linux-mips.org
* MIPS: Enable IOREMAP_PROT config option for MIPS cpusHassan Naveed2018-11-051-0/+12
| | | | | | | | | | | | Allows the users of ptrace to access memory mapped by the ptraced process using the same cache coherency attributes as the original process. For example while using gdb with ioremap_prot() incorporated, both gdb and the process being traced will have same cache coherency attributes. Signed-off-by: Hassan Naveed <hnaveed@wavecomp.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20955/ Cc: <linux-mips@linux-mips.org>
* MIPS: Provide actually relaxed MMIO accessorsMaciej W. Rozycki2018-10-091-20/+28
| | | | | | | | | | | | | | | | | | Improve performance for the relevant systems and remove the DMA ordering barrier from `readX_relaxed' and `writeX_relaxed' MMIO accessors, where it is not needed according to our requirements[1]. For consistency make the same arrangement with low-level port I/O accessors, but do not actually provide any accessors making use of it. References: [1] "LINUX KERNEL MEMORY BARRIERS", Documentation/memory-barriers.txt, Section "KERNEL I/O BARRIER EFFECTS" Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20865/ Cc: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Enforce strong ordering for MMIO accessorsMaciej W. Rozycki2018-10-091-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Architecturally the MIPS ISA does not specify ordering requirements for uncached bus accesses such as MMIO operations normally use and therefore explicit barriers have to be inserted between MMIO accesses where unspecified ordering of operations would cause unpredictable results. For example the R2020 write buffer implements write gathering and combining[1] and as used with the DECstation models 2100 and 3100 for MMIO accesses it bypasses the read buffer entirely, because conflicts are resolved by the memory controller for DRAM accesses only[2] (NB the R2020 and R3020 buffers are the same except for the maximum clock rate). Consequently if a device has say a 16-bit control register at offset 0, a 16-bit event mask register at offset 2 and a 16-bit reset register at offset 4, and the initial value of the control register is 0x1111, then in the absence of barriers a hypothetical code sequence like this: u16 init_dev(u16 __iomem *dev); u16 x; write16(dev + 2, 0xffff); write16(dev + 0, 0x2222); x = read16(dev + 0); write16(dev + 1, 0x3333); write16(dev + 0, 0x4444); return x; } will return 0x1111 and issue a single 32-bit write of 0x33334444 (in the little-endian bus configuration) to offset 0 on the system bus. This is because the read to set `x' from offset 0 bypasses the write of 0x2222 that is still in the write buffer pending the completion of the write of 0xffff to the reset register. Then the write of 0x3333 to the event mask register is merged with the preceding write to the control register as they share the same word address, making it a 32-bit write of 0x33332222 to offset 0. Finally the write of 0x4444 to the control register is combined with the outstanding 32-bit write of 0x33332222 to offset 0, because, again, it shares the same address. This is an example from a legacy system, given here because it is well documented and affects a machine we actually support. But likewise modern MIPS systems may implement weak MMIO ordering, possibly even without having it clearly documented except for being compliant with the architecture specification with respect to the currently defined SYNC instruction variants[3]. Considering the above and that we are required to implement MMIO accessors such that individual accesses made with them are strongly ordered with respect to each other[4], add the necessary barriers to our `inX', `outX', `readX' and `writeX' handlers, as well the associated special use variants. It's up to platforms then to possibly define the respective barriers so as to expand to nil if no ordering enforcement is actually needed for a given system; SYNC is supposed to be as cheap as a NOP on strongly ordered MIPS implementations though. Retain the option to generate weakly-ordered accessors, so that the arrangement for `war_io_reorder_wmb' is not lost in case we need it for fully raw accessors in the future. The reason for this is that it is unclear from commit 1e820da3c9af ("MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT") and especially commit 8faca49a6731 ("MIPS: Modify core io.h macros to account for the Octeon Errata Core-301.") why they are needed there under the previous assumption that these accessors can be weakly ordered. References: [1] "LR3020 Write Buffer", LSI Logic Corporation, September 1988, Section "Byte Gathering", pp. 6-7 [2] "DECstation 3100 Desktop Workstation Functional Specification", Digital Equipment Corporation, Revision 1.3, August 28, 1990, Section 6.1 "Processor", p. 4 [3] "MIPS Architecture For Programmers, Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies LTD, Document Number: MD00086, Revision 6.06, December 15, 2016, Table 5.5 "Encodings of the Bits[10:6] of the SYNC instruction; the SType Field", p. 409 [4] "LINUX KERNEL MEMORY BARRIERS", Documentation/memory-barriers.txt, Section "KERNEL I/O BARRIER EFFECTS" Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> References: 8faca49a6731 ("MIPS: Modify core io.h macros to account for the Octeon Errata Core-301.") References: 1e820da3c9af ("MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT") Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20864/ Cc: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Correct `mmiowb' barrier for `wbflush' platformsMaciej W. Rozycki2018-10-091-8/+3
| | | | | | | | | | | | | | | | | | Redefine `mmiowb' in terms of `iobarrier_w' so that it works correctly for MIPS I platforms, which have no SYNC machine instruction and use a call to `wbflush' instead. This doesn't change the semantics for CONFIG_CPU_CAVIUM_OCTEON, because `iobarrier_w' expands to `wmb', which is ultimately the same as the current arrangement. For MIPS I platforms this not only makes any code that would happen to use `mmiowb' build and run, but it actually enforces the ordering required as well, as `iobarrier_w' has it already covered with the use of `wmb'. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20863/ Cc: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Define MMIO ordering barriersMaciej W. Rozycki2018-10-091-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Define MMIO ordering barriers as separate operations so as to allow making places where such a barrier is required distinct from places where a memory or a DMA barrier is needed. Architecturally MIPS does not specify ordering requirements for uncached bus accesses such as MMIO operations normally use and therefore explicit barriers have to be inserted between MMIO accesses where unspecified ordering of operations would cause unpredictable results. MIPS MMIO ordering barriers are implemented using the same underlying mechanism that memory or a DMA barrier ordering barriers use, that is either a suitable SYNC instruction or a platform-specific `wbflush' call. However platforms may implement different ordering rules for different kinds of bus activity, so having a separate API makes it possible to remove unnecessary barriers and avoid a performance hit they may cause due to unrelated bus activity by making their implementation expand to nil while keeping the necessary ones. Also having distinct barriers for each kind of use makes it easier for the reader to understand what code has been intended to do. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20862/ Cc: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Enable Store Fill Buffer at runtimeHuacai Chen2018-09-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | New Loongson-3 (Loongson-3A R2, Loongson-3A R3, and newer) has SFB (Store Fill Buffer) which can improve the performance of memory access. Now, SFB enablement is controlled by CONFIG_LOONGSON3_ENHANCEMENT, and the generic kernel has no benefit from SFB (even it is running on a new Loongson-3 machine). With this patch, we can enable SFB at runtime by detecting the CPU type (the expense is war_io_reorder_wmb() will always be a 'sync', which will hurt the performance of old Loongson-3). [paul.burton@mips.com: Further info from Huacai: In practise, I found that sometimes there are boot failures if I enable SFB/LPA in cpu_probe(). I don't know why because processor designers also haven't give me an explaination, but I think this may have some relationships to speculative execution.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20426/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
* MIPS: Remove SLOW_DOWN_IOPaul Burton2018-08-301-37/+3
| | | | | | | | | | | | | | | arch/mips appears to have inherited SLOW_DOWN_IO from arch/x86 in antiquity, but we never define CONF_SLOWDOWN_IO so this is unused code. Perhaps it was once useful to keep the MIPS header close to the x86 version to ease comparisons or porting changes, but they've diverged significantly at this point & x86 does this differently now anyway. Delete the dead code. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20343/ Cc: linux-mips@linux-mips.org
* MIPS: Use GENERIC_IOMAPPaul Burton2018-08-301-5/+10
| | | | | | | | | | | | | | | | | | | | MIPS has a copy of lib/iomap.c with minor alterations, none of which are necessary given appropriate definitions of PIO_OFFSET, PIO_MASK & PIO_RESERVED. Provide such definitions, select GENERIC_IOMAP & remove arch/mips/lib/iomap.c to cut back on the needless duplication. The one change this does make is to our mmio_{in,out}s[bwl] functions, which began to deviate from their generic counterparts with commit 0845bb721ebb ("MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO"). I suspect that this commit was incorrect, and that the SEAD-3 platform should have instead selected CONFIG_SWAP_IO_SPACE. Since the SEAD-3 platform code is now gone & the board is instead supported by the generic platform (CONFIG_MIPS_GENERIC) which selects CONFIG_SWAP_IO_SPACE anyway, this shouldn't be a problem any more. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20342/ Cc: linux-mips@linux-mips.org
* MIPS: Fix ISA virt/bus conversion for non-zero PHYS_OFFSETPaul Burton2018-07-301-4/+4
| | | | | | | | | | | | | | | | | isa_virt_to_bus() & isa_bus_to_virt() claim to treat ISA bus addresses as being identical to physical addresses, but they fail to do so in the presence of a non-zero PHYS_OFFSET. Correct this by having them use virt_to_phys() & phys_to_virt(), which consolidates the calculations to one place & ensures that ISA bus addresses do indeed match physical addresses. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20047/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
* mips: mm: Discard ioremap_cacheable_cow() methodSerge Semin2018-07-201-7/+0
| | | | | | | | | | | | | | | | | | | This macro substitution is the shortcut to map cacheable IO memory with coherent and write-back attributes. Since it is entirely unused by kernel, lets just remove it. Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Suggested-by: Christoph Hellwig <hch@infradead.org> Patchwork: https://patchwork.linux-mips.org/patch/19937/ CC: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Sinan Kaya <okaya@codeaurora.org> Cc: Huacai Chen <chenhc@lemote.com> Cc: Sergey.Semin@t-platforms.ru Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
* mips: mm: Discard ioremap_uncached_accelerated() methodSerge Semin2018-07-101-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Adaptive ioremap_wc() method is now available as of commit 9748e33e26c6 ("mips: mm: Create UCA-based ioremap_wc() method"). We can use it to obtain UnCached Accelerated (UCA) mappings safely on all MIPS systems, and so we don't need the MIPS-specific ioremap_uncached_accelerated() any longer. This macro hard-coded the UCA Cache Coherency Attribute (CCA) in a manner that isn't safe for kernels that may run on different CPUs, and it is also entirely unused so we can trivially remove it. [paul.burton@mips.com: - Reword the commit message a little. - Remove CC stable.] Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19790/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: okaya@codeaurora.org Cc: chenhc@lemote.com Cc: Sergey.Semin@t-platforms.ru Cc: linux-kernel@vger.kernel.org
* mips: mm: Create UCA-based ioremap_wc() methodSerge Semin2018-07-101-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modern MIPS cores (like P5600/6600, M5150/6520, end so on) which got L2-cache on chip also can enable a special type Cache-Coherency attribute (CCA) named UnCached Accelerated attribute (UCA). In this way uncached accelerated accesses are treated the same way as non-accelerated uncached accesses, but uncached stores are gathered together for more efficient bus utilization. So to speak this CCA enables uncached transactions to better utilize bus bandwidth via burst transactions. This is exactly why ioremap_wc() method has been introduced in Linux. Alas MIPS-platform code hasn't implemented it so far, instead default one has been used which was an alias to ioremap_nocache. In order to fix this we added MIPS-specific ioremap_wc() macro substituted by generic __ioremap_mode() method call with writecombine CPU-info field passed. It shall create real ioremap_wc() method if CPU-cache supports UCA feature and fall-back to _CACHE_UNCACHED attribute if one doesn't. Additionally platform-specific io.h shall declare ARCH_HAS_IOREMAP_WC macro as indication of architectural definition of ioremap_wc() (similar to x86/powerpc). [paul.burton@mips.com: - Remove CC stable, this is new functionality.] Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19789/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: okaya@codeaurora.org Cc: chenhc@lemote.com Cc: Sergey.Semin@t-platforms.ru Cc: linux-kernel@vger.kernel.org
* MIPS: simplify CONFIG_DMA_NONCOHERENT ifdefsChristoph Hellwig2018-06-241-2/+2
| | | | | | | | | | | | | | | | | | CONFIG_DMA_MAYBE_COHERENT already selects CONFIG_DMA_NONCOHERENT, so we can remove the extra conditions. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19529/ Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: David Daney <david.daney@cavium.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Tom Bogendoerfer <tsbogend@alpha.franken.de> Cc: Huacai Chen <chenhc@lemote.com> Cc: iommu@lists.linux-foundation.org Cc: linux-mips@linux-mips.org
* MIPS: io: Add barrier after register read in inX()Huacai Chen2018-06-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | While a barrier is present in the outX() functions before the register write, a similar barrier is missing in the inX() functions after the register read. This could allow memory accesses following inX() to observe stale data. This patch is very similar to commit a1cc7034e33d12dc1 ("MIPS: io: Add barrier after register read in readX()"). Because war_io_reorder_wmb() is both used by writeX() and outX(), if readX() need a barrier then so does inX(). Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen <chenhc@lemote.com> Patchwork: https://patchwork.linux-mips.org/patch/19516/ Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: James Hogan <james.hogan@mips.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
* MIPS: io: Add barrier after register read in readX()Sinan Kaya2018-04-141-0/+2
| | | | | | | | | | | | | | | | While a barrier is present in the writeX() functions before the register write, a similar barrier is missing in the readX() functions after the register read. This could allow memory accesses following readX() to observe stale data. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Reported-by: Arnd Bergmann <arnd@arndb.de> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/19069/ [jhogan@kernel.org: Tidy commit message] Signed-off-by: James Hogan <jhogan@kernel.org>
* MIPS: io: Prevent compiler reordering writeX()Sinan Kaya2018-04-121-1/+1
| | | | | | | | | | | | | | | | writeX() has strong ordering semantics with respect to memory updates. In the absence of a write barrier or a compiler barrier, the compiler can reorder register and memory update instructions. This breaks the writeX() API. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18997/ [jhogan@kernel.org: Tidy commit message] Signed-off-by: James Hogan <jhogan@kernel.org>
* MIPS: Add __ioread64_copyPaul Burton2017-09-041-0/+2
| | | | | | | | | | | | | | | | | We currently have __ioread32_copy, __iowrite32_copy & __iowrite64_copy helpers in lib/iomap_copy.c. This patch adds __ioread64_copy to round out the set, allowing copies from I/O memory using 32 or 64 bit reads. [ralf@linux-mips.org: Changed to move all the code of this patch to be applied to arch/mips temporarily.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17025/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENTHuacai Chen2016-05-131-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), Fast TLB refill support, etc. This patch introduce a config option, CONFIG_LOONGSON3_ENHANCEMENT, to enable those enhancements which are not probed at run time. If you want a generic kernel to run on all Loongson 3 machines, please say 'N' here. If you want a high-performance kernel to run on new Loongson 3 machines only, please say 'Y' here. Some additional explanations: 1) SFB locates between core and L1 cache, it causes memory access out of order, so writel/outl (and other similar functions) need a I/O reorder barrier. 2) Loongson 3 has a bug that di instruction can not save the irqflag, so arch_local_irq_save() is modified. Since CPU_MIPSR2 is selected by CONFIG_LOONGSON3_ENHANCEMENT, generic kernel doesn't use ei/di at all. 3) CPU_HAS_PREFETCH is selected by CONFIG_LOONGSON3_ENHANCEMENT, so MIPS_CPU_PREFETCH (used by uasm) probing is also put in this patch. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: io.h: Define `ioremap_cache'Maciej W. Rozycki2016-01-241-0/+1
| | | | | | | | | | Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12040/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Define ioremap_ucBen Hutchings2015-10-061-0/+1
| | | | | | | | | | | | All architectures must now define ioremap_uc(), but MIPS currently only has ioremap_nocache(). Fixes: 4c73e8926623 ("arch/*/io.h: Add ioremap_uc() to all architectures") Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Cc: Luis R. Rodriguez <mcgrof@suse.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11263/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Replace use of phys_t with phys_addr_t.Ralf Baechle2014-11-241-4/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix gigaton of warning building with microMIPS.Ralf Baechle2014-03-311-2/+2
| | | | | | | | | | | | | | | | With binutils 2.24 the attempt to switch with microMIPS mode to MIPS III mode through .set mips3 results in *lots* of warnings like {standard input}: Assembler messages: {standard input}:397: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension during a kernel build. Fixed by using .set arch=r4000 instead. This breaks support for building the kernel with binutils 2.13 which was supported for 32 bit kernels only anyway and 2.14 which was a bad vintage for MIPS anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Extend DMA_MAYBE_COHERENT logic to DMA_NONCOHERENT useManuel Lauss2014-03-261-2/+2
| | | | | | | | | | Setting DMA_MAYBE_COHERENT gives a platform the opportunity to select use of cache ops at boot. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6575/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: define write{b,w,l,q}_relaxedFlorian Fainelli2013-07-011-0/+5
| | | | | | | | | | | | | | MIPS does define read{b,w,l,q}_relaxed but does not define their write counterparts: write{b,w,l,q}_relaxed. This patch adds the missing definitions for the write*_relaxed I/O accessors. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: jogo@openwrt.org Patchwork: https://patchwork.linux-mips.org/patch/5352/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Expose missing pci_io{map,unmap} declarationsMarkos Chandras2013-07-011-0/+5
| | | | | | | | | | | | | | | | | | | | | | The GENERIC_PCI_IOMAP does not depend on CONFIG_PCI so move it to the CONFIG_MIPS symbol so it's always selected for MIPS. This fixes the missing pci_iomap declaration for MIPS. Moreover, the pci_iounmap function was not defined in the io.h header file if the CONFIG_PCI symbol is not set, but it should since MIPS is not using CONFIG_GENERIC_IOMAP. This fixes the following problem on a allyesconfig: drivers/net/ethernet/3com/3c59x.c:1031:2: error: implicit declaration of function 'pci_iomap' [-Werror=implicit-function-declaration] drivers/net/ethernet/3com/3c59x.c:1044:3: error: implicit declaration of function 'pci_iounmap' [-Werror=implicit-function-declaration] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5478/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Make virt_to_phys() work for all unmapped addresses.David Daney2013-05-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported: This problem was discovered when doing BGP traffic with the TCP MD5 option activated, where the following call chain caused a crash: * tcp_v4_rcv * tcp_v4_timewait_ack * tcp_v4_send_ack -> follow stack variable rep.th * tcp_v4_md5_hash_hdr * tcp_md5_hash_header * sg_init_one * sg_set_buf * virt_to_page I noticed that tcp_v4_send_reset uses a similar stack variable and also calls tcp_v4_md5_hash_hdr, so it has the same problem. The networking core can indirectly call virt_to_phys() on stack addresses, if this is done from PID 0, the stack will usually be in CKSEG0, so virt_to_phys() needs to work there as well Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Jiang Liu <liuj97@gmail.com> Cc: eunb.song@samsung.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5220/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-15/+15
| | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove irqflags.h dependency from bitops.hJim Quinlan2012-11-091-0/+1
| | | | | | | | | | | | | | | The "else clause" of most functions in bitops.h invoked raw_local_irq_{save,restore}() and in doing so had a dependency on irqflags.h. This fix moves said code to bitops.c, removing the dependency. Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: Kevin Cernekee cernekee@gmail.com Cc: Jim Quinlan <jim2101024@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: fix bug.h build regressionYoichi Yuasa2012-07-181-0/+1
| | | | | | | | | | | | | | | | | | | Commit 377780887 ("bug.h: need linux/kernel.h for TAINT_WARN.") broke all MIPS builds: CC arch/mips/kernel/machine_kexec.o include/linux/log2.h: In function '__ilog2_u32': include/linux/log2.h:34:2: error: implicit declaration of function 'fls' [-Werror=implicit-function-declaration] include/linux/log2.h: In function '__ilog2_u64': include/linux/log2.h:42:2: error: implicit declaration of function 'fls64' [-Werror=implicit-function-declaration] ... Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Tested-by: John Crispin <blogic@openwrt.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Revert "MIPS: LD/SD o32 macro GAS fix update"Ralf Baechle2011-10-201-10/+2
| | | | | | | | | | | | | | This reverts commit 97475f8b42e83be2966aa2d70ab9c98477701c53 (lmo) / 82b89152f00f7ad17844d5614d5011e8d7944ac9 (kernel.org) [MIPS: LD/SD o32 macro GAS fix update]. Turns out this patch is producing many build errors with gcc 4.2. Based on further testing with a test case extracted from the build errors found further build errors and suboptimal generation even in violation of the "R" constraint. To make matters worse, the binutils changes also don't work quite as intended so revert this patch for now.
* Fix common misspellingsLucas De Marchi2011-03-311-1/+1
| | | | | | Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
* MIPS: LD/SD o32 macro GAS fix updateMaciej W. Rozycki2010-12-161-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I am about to commit: http://sourceware.org/ml/binutils/2010-10/msg00033.html that fixes a problem with the LD/SD macro currently implemented by GAS for the o32 ABI in an inconsistent way. This is best illustrated with a simple program, which I'm copying here from the message above for easier reference: $ cat ld.s ld $5,32767($4) ld $5,32768($4) This gets assebled into the following output: $ mips-linux-as -32 -mips3 -o ld.o ld.s $ mips-linux-objdump -d ld.o ld.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <.text>: 0: dc857fff ld a1,32767(a0) 4: 3c010001 lui at,0x1 8: 00810821 addu at,a0,at c: 8c258000 lw a1,-32768(at) 10: 8c268004 lw a2,-32764(at) ... Oops! The GAS fix makes the macro behave in a consistent way and pairs of LW/SW instructions to be output as appropriate regardless of the size of the offset associated with the address used. The machine instruction is still available, but to reach it macros have to be disabled first. This has a side effect of requiring the use of a machine-addressable memory operand. As some platforms require 64-bit operations for accesses to some I/O registers LD/SD instructions are used in a couple of places in Linux regardless of the ABI selected. Here's a fix for some pieces of code affected I've been able to track down. The fix should be backwards compatible with all supported binutils releases in existence and can be used as a reference for any other places or off-tree code. The use of the "R" constraint guarantees a machine-addressable operand. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1680/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: add readl/write_be accessorsFlorian Fainelli2010-02-271-0/+18
| | | | | | | | | | | | | | | MIPS currently lacks the readl_be and writel_be accessors which are required by BCM63xx for OHCI and EHCI support. Let's define them globally for MIPS. This also fixes the compilation of the bcm63xx defconfig against USB. Signed-off-by: Florian Fainelli <ffainelli@freebox.fr> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Patchwork: http://patchwork.linux-mips.org/patch/793/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Modify core io.h macros to account for the Octeon Errata Core-301.David Daney2009-01-111-0/+14
| | | | | | Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-111-0/+589
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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