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* MIPS: BCM63XX: fix BCM6345 clocks bitsFlorian Fainelli2012-11-201-7/+12
| | | | | | | | | | | | | BCM6345 has an intermediate 16-bits wide test control register between the peripheral identifier register, and its clock control register is only 16-bits wide contrary to other platforms where it is 32-bits wide. By shifting all clocks bits by 16-bits to the left we ensure they get written to the proper clock control register, without adding specific BCM6345 handling in the clock code. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4555/ Signed-off-by: John Crispin <blogic@openwrt.org>
* MIPS: BCM63XX: add softreset register description for BCM6358Jonas Gorski2012-11-091-0/+10
| | | | | | | | The softreset register description for BCM6358 was missing, so add it. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4454 Signed-off-by: John Crispin <blogic@openwrt.org>
* Merge branch 'master' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2012-10-051-0/+1
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| * MIPS: BCM63XX: add external irq support for BCM6345Maxime Bizon2012-08-241-0/+1
| | | | | | | | | | | | | | | | | | Add the missing definitions for BCM6345. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4091/ Signed-off-by: John Crispin <blogic@openwrt.org>
* | Merge branch 'broadcom' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2012-09-271-2/+165
|\ \ | | | | | | | | | mips-for-linux-next
| * | MIPS: BCM63XX: Add register and IRQ definitions for USB 2.0 deviceKevin Cernekee2012-08-301-0/+147
| | | | | | | | | | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4084/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | MIPS: BCM63XX: Add register definitions for USBD dependenciesKevin Cernekee2012-08-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | The USB 2.0 device depends on some functionality in other blocks, such as GPIO and USBH. Add those register definitions here. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4025/ Signed-off-by: John Crispin <blogic@openwrt.org>
| * | MIPS: BCM63XX: Add new IUDMA definitions needed for USBDKevin Cernekee2012-08-301-2/+10
| |/ | | | | | | | | | | Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4083/ Signed-off-by: John Crispin <blogic@openwrt.org>
* / MIPS: BCM63xx: Fix SPI message control register handling for BCM6338/6348.Florian Fainelli2012-08-171-3/+10
|/ | | | | | | | | | | | | | | | | | | | | BCM6338 and BCM6348 have a message control register width of 8 bits, instead of 16-bits like what the SPI driver assumes right now. Also the SPI message type shift value of 14 is actually 6 for these SoCs. This resulted in transmit FIFO corruption because we were writing 16-bits to an 8-bits wide register, thus spanning on the first byte of the transmit FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo(). Fix this by passing the message control register width and message type shift through platform data back to the SPI driver so that it can use it properly. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: grant.likely@secretlab.ca Cc: spi-devel-general@lists.sourceforge.net Cc: jonas.gorski@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/3983/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63XX: Add PCIe Support for BCM6328Jonas Gorski2012-07-241-0/+54
| | | | | | | | | | | | | Add support for the PCIe port found on BCM6328. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3956/ Reviewed-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63XX: Add basic BCM6328 supportJonas Gorski2012-07-241-0/+54
| | | | | | | | | | | | | | This includes CPU speed, memory size detection and working UART, but lacking the appropriate drivers, no support for attached flash. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3951/ Reviewed-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63XX: Add flash type detectionJonas Gorski2012-07-241-0/+9
| | | | | | | | | | | | | | | On BCM6358 and BCM6368 the attached flash type is exposed through a bootstrapping register. Use it for auto detecting the flash type on those and default to parallel flash for earlier SoCs. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3954/ Reviewed-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63XX: add RNG peripheral definitionsFlorian Fainelli2012-07-241-0/+14
| | | | | | | | | Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: mpm@selenic.com Cc: herbert@gondor.apana.org.au Patchwork: https://patchwork.linux-mips.org/patch/3326/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Define internal registers offsets of the SPI controllerFlorian Fainelli2012-07-231-0/+119
| | | | | | | | | | | | | BCM6338, BCM6348, BCM6358 and BCM6368 basically use the same SPI controller though the internal registers are shuffled, which still allows a common driver to drive that IP block. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: grant.likely@secretlab.ca Cc: spi-devel-general@lists.sourceforge.net Patchwork: https://patchwork.linux-mips.org/patch/3318/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63XX: Be consistent in clock bits enable namingFlorian Fainelli2012-07-231-18/+18
| | | | | | | | | | Remove the _CLK suffix from the BCM6368 clock bits definitions to be consistent with what is already present. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3312/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63XX: Fix BCM6368 IPSec clock bitFlorian Fainelli2012-07-191-1/+1
| | | | | | | | | | | The IPsec clock bit is 18 and not 17. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Cc: mpm@selenic.com Cc: herbert@gondor.apana.org.au Patchwork: https://patchwork.linux-mips.org/patch/3323/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Fix GPIO set/get for BCM6345Florian Fainelli2011-12-071-0/+1
| | | | | | | | | | | | On BCM6345, the register offsets for the set/get GPIO registers is wrong. Use the same logic as the one present in arch/mips/bcm63xx/irq.c to define the correct gpio_out_low_reg value when support for BCM6345 is compiled in. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3010/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Fix SDRAM size computation for BCM6345Florian Fainelli2011-12-071-0/+2
| | | | | | | | | | Instead of hardcoding the amount of available RAM, read the number of effective multiples of 8MB from SDRAM_MBASE_REG. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3008/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63XX: Add support for bcm6368 CPU.Maxime Bizon2011-12-071-2/+107
| | | | | | | Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2892/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63XX: Add external irq support for non 6348 CPUs.Maxime Bizon2011-12-071-9/+22
| | | | | | | Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2899/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63XX: Change irq code to prepare for per-cpu peculiarity.Maxime Bizon2011-12-071-2/+8
| | | | | | | | | No functionnal change is introduced by this patch. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63XX: Add more register sets & missing register definitions.Maxime Bizon2011-12-071-0/+78
| | | | | | | | | Needed for upcoming 6368 CPU support. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2893/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Remove duplicate PERF_IRQSTAT_REG definitionJonas Gorski2011-07-201-1/+0
| | | | | | | | Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Acked-by: Florian Fainelli <florian@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/2461/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Nuke trailing blank linesRalf Baechle2010-02-271-1/+0
| | | | | | | Recent git versions now warn about those and they've always been a bit of an annoyance. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM63xx: Add support for the Broadcom BCM63xx family of SOCs.Maxime Bizon2009-09-171-0/+773
Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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