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path: root/arch/mips/kernel/cpu-probe.c
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* MIPS: Sort out CPU type to name translation.Ralf Baechle2008-10-301-127/+98
* MIPS: Probe for watch registers on cores of all vendors, not just MTI.Ralf Baechle2008-10-301-10/+12
* MIPS: Probe watch registers and report configuration.David Daney2008-10-111-0/+2
* [MIPS] SMTC: Fix SMTC dyntick support.Kevin D. Kissell2008-10-031-3/+7
* [MIPS] Fix potential latency problem due to non-atomic cpu_wait.Atsushi Nemoto2008-09-211-14/+2
* [MIPS] Move arch/mips/philips to arch/mips/nxpDaniel Laird2008-04-281-4/+4
* [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-281-0/+5
* [MIPS] Basic SPRAM supportChris Dearman2008-04-281-0/+8
* [MIPS] Fix loads of section missmatchesRalf Baechle2008-03-121-5/+5
* [MIPS] Alchemy: Au1210/Au1250 CPU supportManuel Lauss2008-01-291-0/+9
* [MIPS] Fix shadow register support.Ralf Baechle2007-11-151-0/+5
* [MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type.Franck Bui-Huu2007-10-111-0/+8
* [MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle2007-10-111-2/+91
* [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.Ralf Baechle2007-10-111-8/+0
* [MIPS] Add support for BCM47XX CPUs.Aurelien Jarno2007-10-111-0/+20
* [MIPS] 20Kc: Disable use of WAIT instruction.Ralf Baechle2007-09-141-1/+8
* [MIPS] Workaround for RM7000 WAIT instruction aka erratum 38Ralf Baechle2007-07-201-1/+25
* [MIPS] PMC MSP71xx mips commonMarc St-Jean2007-07-101-0/+20
* [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2Fuxin Zhang2007-07-101-0/+8
* [MIPS] Enable support for the userlocal hardware registerRalf Baechle2007-07-101-0/+2
* [MIPS] Fix scheduling latency issue on 24K, 34K and 74K coresRalf Baechle2007-07-061-2/+13
* [MIPS] 20K: Handle WAIT related bugs according to errata informationRalf Baechle2007-06-261-1/+11
* [MIPS] Make some __setup functions staticAtsushi Nemoto2007-02-201-1/+1
* [MIPS] Include <asm/bugs> to for declaration of check_bugs32.Ralf Baechle2007-02-181-0/+1
* [MIPS] Whitespace cleanups.Ralf Baechle2007-02-061-1/+1
* [MIPS] Don't print presence of WAIT instruction on bootup.Ralf Baechle2006-11-301-16/+3
* [MIPS] Fix RM9000 wait instruction detection.Ralf Baechle2006-10-091-1/+8
* [MIPS] Reduce race between cpu_wait() and need_resched() checkingAtsushi Nemoto2006-09-271-17/+45
* [MIPS] Save 2k text size in cpu-probeThiemo Seufer2006-07-131-1/+1
* [MIPS] Uses MIPS_CONF_AR instead of magic constants.Thiemo Seufer2006-07-131-2/+2
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-301-1/+0
* [MIPS] MIPS32/MIPS64 secondary cache managementChris Dearman2006-06-291-2/+0
* [MIPS] SB1: Only pass1 FPUs are broken beyond recovery.Ralf Baechle2006-06-061-1/+1
* [MIPS] Treat R14000 like R10000.Kumba2006-06-011-0/+9
* [MIPS] Fix detection and handling of the 74K processor.Chris Dearman2006-06-011-0/+4
* [MIPS] War on whitespace: cleanup initial spaces followed by tabs.Ralf Baechle2006-03-211-3/+3
* [MIPS] Get rid of CONFIG_SB1_PASS_1_WORKAROUNDS #ifdef crapola.Ralf Baechle2006-02-071-4/+3
* MIPS: Introduce machinery for testing for MIPSxxR1/2.Ralf Baechle2006-01-101-5/+30
* MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.Ralf Baechle2006-01-101-6/+6
* [MIPS] R10000 and R12000 need to set MIPS_CPU_4K_CACHE ...Ralf Baechle2005-12-011-2/+2
* Add support for SB1A CPU.Andrew Isaacson2005-10-291-0/+3
* Sibyte fixesAndrew Isaacson2005-10-291-1/+1
* Detect 4KSD and treat it like 4KSc.Ralf Baechle2005-10-291-0/+1
* Cleanup the mess in cpu_cache_init.Ralf Baechle2005-10-291-7/+18
* R4600 has 32 FPRs.Thiemo Seufer2005-10-291-1/+2
* Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.Pete Popov2005-10-291-0/+19
* Detect the MIPS R2 vectored interrupt, external interrupt controllerRalf Baechle2005-10-291-0/+6
* New kernel option nowait allows disabling the use of the wait instruction.Ralf Baechle2005-10-291-0/+16
* Detect the 34K.Ralf Baechle2005-10-291-0/+5
* For MIPS32/MIPS64 cp0.config.mt == 1 implies a standard (R4k-style)Maciej W. Rozycki2005-10-291-5/+1
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