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* MIPS: Tracing: Add IRQENTRY_EXIT section for MIPSWu Zhangjin2009-12-171-7/+14
| | | | | | | | | | | | | | | | | | | | | | | This patch add a new section for MIPS to record the block of the hardirq handling for function graph tracer(print_graph_irq) via adding the __irq_entry annotation to the the entrypoints of the hardirqs(the block with irq_enter()...irq_exit()). Thanks goes to Steven & Frederic Weisbecker for their feedbacks. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Nicholas Mc Guire <der.herr@hofr.at> Cc: zhangfx@lemote.com Cc: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Reviewed-by: Frederic Weisbecker <fweisbec@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/676/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* tree-wide: fix assorted typos all over the placeAndré Goddard Rosa2009-12-041-1/+1
| | | | | | | | | | That is "success", "unknown", "through", "performance", "[re|un]mapping" , "access", "default", "reasonable", "[con]currently", "temperature" , "channel", "[un]used", "application", "example","hierarchy", "therefore" , "[over|under]flow", "contiguous", "threshold", "enough" and others. Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* MIPS: SMTC: Avoid queing multiple reschedule IPIsJaidev Patwardhan2009-11-021-4/+30
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SMTC: Remove duplicate structure field initializationJulia Lawall2009-09-301-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The definition of the irq_ipi structure has two initializations of the flags field. This combines them. [Ralf: The issue was originally introduced by commit be4894196d79455f420dd7bb78be7dc73bec115c (linux-mips.org) rsp. 033890b084adfa367c544864451d7730552ce8bf (kernel.org). The original intention of the code was to initialize .flags with both flags ored together. The broken C code as actually implemented will be compiled by an equally broken gcc to use only the last initialization, that is IRQF_PERCPU which means this turned into an SMTC bug for 2.6.23 and newer.] The semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @r@ identifier I, s, fld; position p0,p; expression E; @@ struct I s =@p0 { ... .fld@p = E, ...}; @s@ identifier I, s, r.fld; position r.p0,p; expression E; @@ struct I s =@p0 { ... .fld@p = E, ...}; @script:python@ p0 << r.p0; fld << r.fld; ps << s.p; pr << r.p; @@ if int(ps[0].line)!=int(pr[0].line) or int(ps[0].column)!=int(pr[0].column): cocci.print_main(fld,p0) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* cpumask: Use accessors for cpu_*_mask: mipsRusty Russell2009-09-241-3/+3
| | | | | | | | Use the accessors rather than frobbing bits directly (the new versions are const). Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Mike Travis <travis@sgi.com>
* MIPS: Remove useless zero initializations.Ralf Baechle2009-09-171-5/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SMTC: Move cross VPE writes to after a TC is assigned to VPE.Kurt Martin2009-08-031-5/+8
| | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Raghu Gandham <raghu@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.Ralf Baechle2009-06-241-0/+1
| | | | | | | | | Some of the were relying into smp.h being dragged in by another header which of course is fragile. <asm/cpu-info.h> uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: SMTC: Fix formatting difference to linux-mips.org codeRalf Baechle2009-06-171-0/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irq: update all arches for new irq_desc, fixMike Travis2009-01-151-1/+3
| | | | | | | | | | | | | | | | Impact: fix build errors Since the SPARSE IRQS changes redefined how the kstat irqs are organized, arch's must use the new accessor function: kstat_incr_irqs_this_cpu(irq, DESC); If CONFIG_SPARSE_IRQS is set, then DESC is a pointer to the irq_desc which has a pointer to the kstat_irqs. If not, then the .irqs field of struct kernel_stat is used instead. Signed-off-by: Mike Travis <travis@sgi.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* irq: update all arches for new irq_descMike Travis2009-01-121-1/+1
| | | | | | | | | Impact: cleanup, update to new cpumask API Irq_desc.affinity and irq_desc.pending_mask are now cpumask_var_t's so access to them should be using the new cpumask API. Signed-off-by: Mike Travis <travis@sgi.com>
* cpumask: centralize cpu_online_map and cpu_possible_mapRusty Russell2008-12-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: cleanup Each SMP arch defines these themselves. Move them to a central location. Twists: 1) Some archs (m32, parisc, s390) set possible_map to all 1, so we add a CONFIG_INIT_ALL_POSSIBLE for this rather than break them. 2) mips and sparc32 '#define cpu_possible_map phys_cpu_present_map'. Those archs simply have phys_cpu_present_map replaced everywhere. 3) Alpha defined cpu_possible_map to cpu_present_map; this is tricky so I just manipulate them both in sync. 4) IA64, cris and m32r have gratuitous 'extern cpumask_t cpu_possible_map' declarations. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Reviewed-by: Grant Grundler <grundler@parisc-linux.org> Tested-by: Tony Luck <tony.luck@intel.com> Acked-by: Ingo Molnar <mingo@elte.hu> Cc: Mike Travis <travis@sgi.com> Cc: ink@jurassic.park.msu.ru Cc: rmk@arm.linux.org.uk Cc: starvik@axis.com Cc: tony.luck@intel.com Cc: takata@linux-m32r.org Cc: ralf@linux-mips.org Cc: grundler@parisc-linux.org Cc: paulus@samba.org Cc: schwidefsky@de.ibm.com Cc: lethal@linux-sh.org Cc: wli@holomorphy.com Cc: davem@davemloft.net Cc: jdike@addtoit.com Cc: mingo@redhat.com
* [MIPS] SMTC: Fix SMTC dyntick support.Kevin D. Kissell2008-10-031-119/+133
| | | | | | | | | | | Rework of SMTC support to make it work with the new clock event system, allowing "tickless" operation, and to make it compatible with the use of the "wait_irqoff" idle loop. The new clocking scheme means that the previously optional IPI instant replay mechanism is now required, and has been made more robust. Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Close tiny holes in the SMTC IPI replay system.Kevin D. Kissell2008-10-031-1/+1
| | | | | Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Build fix: Fix irq flags typeRalf Baechle2008-10-031-3/+3
| | | | | | | | Though from a hardware perspective it would be sensible to use only a 32-bit unsigned int type Linux defines interrupt flags to be stored in an unsigned long and nothing else. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: convert to generic helpers for IPI function callsJens Axboe2008-06-261-1/+0
| | | | | | | | | | | | | This converts mips to use the new helpers for smp_call_function() and friends, and adds support for smp_call_function_single(). Not tested, but it compiles. mips shares the same IPI for smp_call_function() and smp_call_function_single(), since not all mips platforms have enough available IPIs to support seperate setups. Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
* [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-281-1/+2
| | | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Remove TLB sanitation codeChris Dearman2008-04-281-8/+0
| | | | | | | It is not being used by Malta and shouldn't be needed for MIPSsim. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* arch/mips/: Spelling fixesJoe Perches2008-02-031-3/+3
| | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Adrian Bunk <bunk@kernel.org>
* [MIPS] SMP: Call platform methods via ops structure.Ralf Baechle2008-01-291-1/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Allow control over TC assignment to vpe0.Kevin D. Kissell2007-10-291-13/+44
| | | | | | | | | | | | | | | | | Modify the SMTC initialization code to allow boot-time specification not only of how many VPEs and TCs to use, but also how many TCs out of the allowed pool are to be bound to VPE 0. The new boot option is "vpe0tcs=N", where N is an integer. Using it in combination with the existing options allows arbitrary assignments across the 2 VPEs of a 34K. e.g. "maxtcs=3 vpe0tcs=1" forces VPE0 to have 1 TC, while VPE1 has 2, and "maxtcs=4 vpe0tcs=3" forces VPE0 to have 3 TCs, while VPE1 gets 1. If no vpe0tcs option is specified, the traditional algorithm of evenly dividing TCs between available VPEs, with the odd "slop" going to VPE0, is retained. The reason for doing this is to allow a finer balancing of TCs which can handle I/O interrupts on Malta (those on VPE 0) and those which cannot. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Kill num_online_cpus() loops.Ralf Baechle2007-10-111-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] checkfiles: Fix "need space after that ','" errors.Ralf Baechle2007-10-111-3/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle2007-10-111-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Dyntick support for SMTC:Ralf Baechle2007-10-111-35/+32
| | | | | | | | | The kernel currently only supports broadcasting of the timer interrupt from a single timer, not multicasting into two multicast groups of processors. So the implemented mechanism for SMTC works by broadcasting the cp0 compare interrupt on VPE 0 and ignoring it on any additional VPEs. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Implement clockevents for R4000-style cp0 count/compare interruptRalf Baechle2007-10-111-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.Ralf Baechle2007-10-111-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency.Ralf Baechle2007-10-111-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] IRQ Affinity Support for SMTC on Malta PlatformKevin D. Kissell2007-10-111-0/+63
| | | | | Signed-off-by: Kevin D. Kissell <kevink@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Make ack_bad_irq() safe with no IM backstop.Ralf Baechle2007-09-241-1/+4
| | | | | | | Issue reported and original patch by Kevin Kissel, cleaner (imho) implementation by me. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Move MIPS_CPU_IPI_IRQ definition into header.Ralf Baechle2007-08-271-2/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Fix modpost warning.Ralf Baechle2007-07-311-1/+1
| | | | | | WARNING: vmlinux.o(.text+0xcf54): Section mismatch: reference to .init.text:smp_bootstrap (between 'smtc_boot_secondary' and 'ipi_interrupt') Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] MT: Enable coexistence of AP/SP with VSMP and SMTC.Ralf Baechle2007-07-311-16/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: smtc_timer_broadcast ignores its arguments, make it void.Ralf Baechle2007-07-311-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Declare static what should be static.Ralf Baechle2007-07-311-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Statically initialize irq_ipi[].Ralf Baechle2007-07-311-6/+6
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Use current_cpu_data instead of cpu_data[smp_processor_id]Ralf Baechle2007-07-101-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Count timer interrupts correctly.Chris Dearman2007-06-261-1/+1
| | | | | Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Don't drag a platform specific header into generic arch code.Ralf Baechle2007-06-201-3/+3
| | | | | | | | For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Fix warning.Ralf Baechle2007-06-111-2/+2
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* wrap access to thread_infoRoman Zippel2007-05-091-1/+1
| | | | | | | | | Recently a few direct accesses to the thread_info in the task structure snuck back, so this wraps them with the appropriate wrapper. Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* [MIPS] SMTC: Fix recursion in instant IPI replay code.Ralf Baechle2007-03-291-7/+33
| | | | | | | | | | | | local_irq_restore -> raw_local_irq_restore -> irq_restore_epilog -> smtc_ipi_replay -> smtc_ipi_dq -> spin_unlock_irqrestore -> _spin_unlock_irqrestore -> local_irq_restore The recursion does abort when there is no more IPI queued for a CPU, so this isn't usually fatal which is why we got away with this for so long until this was discovered by code inspection. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Fix false trigger of debug code on single VPE.Ralf Baechle2007-03-291-5/+15
| | | | | | | | Make smtc_setup_irq() update the list of interrupts which need to be watched by the debug code itself. Also there is no need to initialize the IPI swint when running with a single VPE, so don't initialize it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: irq_{enter,leave} and kstats keeping for relayed timer ints.Ralf Baechle2007-03-291-0/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Make SMTC_IDLE_HOOK_DEBUG a proper option in Kconfig.debug.Ralf Baechle2007-02-261-11/+8
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Make a bunch of functions and variables static.Ralf Baechle2007-02-061-9/+9
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Whitespace cleanups.Ralf Baechle2007-02-061-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: remove unused atomic_postclearRalf Baechle2007-02-061-22/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] Define MIPS_CPU_IRQ_BASE in generic headerAtsushi Nemoto2007-02-061-11/+1
| | | | | | | | | | | | | | | | | | | | | | The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* [MIPS] SMTC: Fix module build by exporting symbolRalf Baechle2007-01-241-0/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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