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* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2013-03-0210-49/+158
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: o Add basic support for the Mediatek/Ralink Wireless SoC family. o The Qualcomm Atheros platform is extended by support for the new QCA955X SoC series as well as a bunch of patches that get the code ready for OF support. o Lantiq and BCM47XX platform have a few improvements and bug fixes. o MIPS has sent a few patches that get the kernel ready for the upcoming microMIPS support. o The rest of the series is made up of small bug fixes and cleanups that relate to various parts of the MIPS code. The biggy in there is a whitespace cleanup. After I was sent another set of whitespace cleanup patches I decided it was the time to clean the whitespace "issues" for once and and that touches many files below arch/mips/. Fix up silly conflicts, mostly due to whitespace cleanups. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits) MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h MIPS: remove broken conditional inside vpe loader code MIPS: SMTC: fix implicit declaration of set_vi_handler MIPS: early_printk: drop __init annotations MIPS: Probe for and report hardware virtualization support. MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board MIPS: ath79: add USB controller registration code for the QCA955X SoCs MIPS: ath79: add PCI controller registration code for the QCA955X SoCs MIPS: ath79: add WMAC registration code for the QCA955X SoCs MIPS: ath79: register UART for the QCA955X SoCs MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear} MIPS: ath79: add GPIO setup code for the QCA955X SoCs MIPS: ath79: add IRQ handling code for the QCA955X SoCs MIPS: ath79: add clock setup code for the QCA955X SoCs MIPS: ath79: add SoC detection code for the QCA955X SoCs MIPS: ath79: add early printk support for the QCA955X SoCs MIPS: ath79: fix WMAC IRQ resource assignment mips: reserve elfcorehdr mips: Make sure kernel memory is in iomem MIPS: ath79: use dynamically allocated USB platform devices ...
| * Merge branch 'mips-next-3.9' of ↵Ralf Baechle2013-02-217-43/+152
| |\ | | | | | | | | | git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
| | * MIPS: lantiq: rework external irq codeJohn Crispin2013-02-171-32/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | This code makes the irqs used by the EIU loadable from the DT. Additionally we add a helper that allows the pinctrl layer to map external irqs to real irq numbers. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4818/
| | * MIPS: lantiq: add GPHY clock gate bitsJohn Crispin2013-02-172-0/+10
| | | | | | | | | | | | | | | | | | | | | Explicitly enable the clock gate of the internal GPHYs found on xrx200. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4816/
| | * MIPS: lantiq: adds static clock for PP32John Crispin2013-02-175-10/+68
| | | | | | | | | | | | | | | | | | | | | | | | The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4815/
| | * MIPS: lantiq: trivial typo fixJohn Crispin2013-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | "nodes" is written with a single "s" Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4814/
| * | MIPS: Whitespace cleanup.Ralf Baechle2013-02-015-7/+7
| |/ | | | | | | | | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge tag 'driver-core-3.9-rc1' of ↵Linus Torvalds2013-02-212-7/+6
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core patches from Greg Kroah-Hartman: "Here is the big driver core merge for 3.9-rc1 There are two major series here, both of which touch lots of drivers all over the kernel, and will cause you some merge conflicts: - add a new function called devm_ioremap_resource() to properly be able to check return values. - remove CONFIG_EXPERIMENTAL Other than those patches, there's not much here, some minor fixes and updates" Fix up trivial conflicts * tag 'driver-core-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (221 commits) base: memory: fix soft/hard_offline_page permissions drivercore: Fix ordering between deferred_probe and exiting initcalls backlight: fix class_find_device() arguments TTY: mark tty_get_device call with the proper const values driver-core: constify data for class_find_device() firmware: Ignore abort check when no user-helper is used firmware: Reduce ifdef CONFIG_FW_LOADER_USER_HELPER firmware: Make user-mode helper optional firmware: Refactoring for splitting user-mode helper code Driver core: treat unregistered bus_types as having no devices watchdog: Convert to devm_ioremap_resource() thermal: Convert to devm_ioremap_resource() spi: Convert to devm_ioremap_resource() power: Convert to devm_ioremap_resource() mtd: Convert to devm_ioremap_resource() mmc: Convert to devm_ioremap_resource() mfd: Convert to devm_ioremap_resource() media: Convert to devm_ioremap_resource() iommu: Convert to devm_ioremap_resource() drm: Convert to devm_ioremap_resource() ...
| * MIPS: Convert to devm_ioremap_resource()Thierry Reding2013-01-252-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | Convert all uses of devm_request_and_ioremap() to the newly introduced devm_ioremap_resource() which provides more consistent error handling. devm_ioremap_resource() provides its own error messages so all explicit error messages can be removed from the failure code paths. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | MIPS: Lantiq: Fix cp0_perfcount_irq mappingJohn Crispin2013-01-301-1/+1
|/ | | | | | | | | | | | | | | | | | | The introduction of the OF support broke the cp0_perfcount_irq mapping. This resulted in oprofile not working anymore. Offending commit is : commit 3645da0276ae9f6938ff29b13904b803ecb68424 Author: John Crispin <blogic@openwrt.org> Date: Tue Apr 17 10:18:32 2012 +0200 OF: MIPS: lantiq: implement irq_domain support Signed-off-by: Conor O'Gorman <i@conorogorman.net> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4875/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: drivers: remove __dev* attributes.Greg Kroah-Hartman2013-01-033-3/+3
| | | | | | | | | | | | | | CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2012-12-147-15/+170
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "The MIPS bits for 3.8. This also includes a bunch fixes that were sitting in the linux-mips.org git tree for a long time. This pull request contains updates to several OCTEON drivers and the board support code for BCM47XX, BCM63XX, XLP, XLR, XLS, lantiq, Loongson1B, updates to the SSB bus support, MIPS kexec code and adds support for kdump. When pulling this, there are two expected merge conflicts in include/linux/bcma/bcma_driver_chipcommon.h which are trivial to resolve, just remove the conflict markers and keep both alternatives." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (90 commits) MIPS: PMC-Sierra Yosemite: Remove support. VIDEO: Newport Fix console crashes MIPS: wrppmc: Fix build of PCI code. MIPS: IP22/IP28: Fix build of EISA code. MIPS: RB532: Fix build of prom code. MIPS: PowerTV: Fix build. MIPS: IP27: Correct fucked grammar in ops-bridge.c MIPS: Highmem: Fix build error if CONFIG_DEBUG_HIGHMEM is disabled MIPS: Fix potencial corruption MIPS: Fix for warning from FPU emulation code MIPS: Handle COP3 Unusable exception as COP1X for FP emulation MIPS: Fix poweroff failure when HOTPLUG_CPU configured. MIPS: MT: Fix build with CONFIG_UIDGID_STRICT_TYPE_CHECKS=y MIPS: Remove unused smvp.h MIPS/EDAC: Improve OCTEON EDAC support. MIPS: OCTEON: Add definitions for OCTEON memory contoller registers. MIPS: OCTEON: Add OCTEON family definitions to octeon-model.h ata: pata_octeon_cf: Use correct byte order for DMA in when built little-endian. MIPS/OCTEON/ata: Convert pata_octeon_cf.c to use device tree. MIPS: Remove usage of CEVT_R4K_LIB config option. ...
| * Merge branch 'mips-next' of http://dev.phrozen.org/githttp/mips-next into ↵Ralf Baechle2012-12-137-12/+167
| |\ | | | | | | | | | mips-for-linux-next
| | * MIPS: lantiq: adds GPHY firmware loaderJohn Crispin2012-11-113-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | The internal GPHYs need a firmware blob to function properly. This patch adds the code needed to request the blob and load it to the PHY. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4523
| | * MIPS: lantiq: adds code for booting GPHYJohn Crispin2012-11-111-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to boot them up. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4522
| | * MIPS: lantiq: adds xrx200 ethernet clock definitionJohn Crispin2012-11-111-0/+4
| | | | | | | | | | | | | | | Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4521
| | * MIPS: lantiq: verbose init of dma coreJohn Crispin2012-11-111-1/+8
| | | | | | | | | | | | | | | | | | | | | Print the hardware revision and port/channel info when starting the dma core. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4520
| | * MIPS: lantiq: fix bootselect bits on XRX200 SoCJohn Crispin2012-11-111-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | The XRX200 SoC family has a different register layout for reading the boot selection bits. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4519
| | * MIPS: lantiq: unbreak devicetree initJohn Crispin2012-11-111-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The bootmem was incorrectly freed resulting in lots of dangling pointers. Additionally we should use of_platform_populate() as the Documentaion tells us to do so. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4518
| * | MIPS: Lantiq: Fix typo in "endianness" in dma.cMasanari Iida2012-12-131-3/+3
| |/ | | | | | | | | | | | | | | | | | | Correct spelling typo ENDIANESS to ENDIANNESS in arc/mips/lantiq/xway/dma.c Signed-off-by: Masanari Iida <standby24x7@gmail.com> Cc: trivial@kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4613/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* / kbuild: centralize .dts->.dtb ruleStephen Warren2012-11-301-3/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All architectures that use cmd_dtc do so in almost the same way. Create a central build rule to avoid duplication. The one difference is that most current uses of dtc build $(obj)/%.dtb from $(src)/dts/%.dts rather than building the .dtb in the same directory as the .dts file. This difference will be eliminated arch-by-arch in future patches. MIPS is the exception here; it already uses the exact same rule as the new common rule, so the duplicate is removed in this patch to avoid any conflict. arch/mips changes courtesy of Ralf Baechle. Update Documentation/kbuild to remove the explicit call to cmd_dtc from the example, now that the rule exists in a centralized location. Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-arm-kernel@lists.infradead.org Cc: Olof Johansson <olof@lixom.net> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Jonas Bonn <jonas@southpole.se> Cc: linux@lists.openrisc.net Cc: Aurelien Jacquiot <a-jacquiot@ti.com> Cc: linux-c6x-dev@linux-c6x.org Cc: Mark Salter <msalter@redhat.com> Cc: Michal Simek <monstr@monstr.eu> Cc: microblaze-uclinux@itee.uq.edu.au Cc: Chris Zankel <chris@zankel.net> Cc: linux-xtensa@linux-xtensa.org Cc: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* Merge branch 'master' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2012-10-051-0/+2
|\ | | | | | | mips-for-linux-next
| * MIPS: lantiq: explicitly enable clkout generationJohn Crispin2012-08-221-0/+2
| | | | | | | | | | | | | | | | Previously we relied on the bootloader to have enabled this bit. However some bootloaders seem to not enable this for us. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4120/
* | OF: pinctrl: MIPS: lantiq: adds support for FALCON SoCJohn Crispin2012-09-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
* | OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl supportJohn Crispin2012-09-133-184/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement support for pinctrl on lantiq/xway socs. The IO core found on these socs has the registers for pinctrl, pinconf and gpio mixed up in the same register range. As the gpio_chip handling is only a few lines, the driver also implements the gpio functionality. This obseletes the old gpio driver that was located in the arch/ folder. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org
* | MIPS: lantiq: adds support for gptu timersJohn Crispin2012-08-232-1/+215
| | | | | | | | | | | | | | | | Lantiq socs have a General Purpose Timer Unit (GPTU). This driver allows us to initialize the timers. The voice firmware needs these timers as a reference. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4236/
* | MIPS: lantiq: enable pci clk conditional for xrx200 SoCJohn Crispin2012-08-231-1/+2
| | | | | | | | | | | | | | | | The xrx200 SoC family has the same PCI clock register layout as the AR9. Enable the same quirk as for AR9 Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4235/
* | MIPS: lantiq: falcon clocks were not enabled properlyJohn Crispin2012-08-231-0/+1
| | | | | | | | | | | | | | | | | | As a result of a non populated ->bits field inside the clock struct, the clock domains were never powered on the Falcon. Until now we only used domains that were also used and powered by the bootloader. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4234/
* | MIPS: lantiq: adds support for nmi and ejtag bootrom vectorsJohn Crispin2012-08-231-0/+5
| | | | | | | | | | | | | | | | Register nmi and ejtag bootrom vectors for FALC-ON SoC. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4238/
* | MIPS: lantiq: external irq sources are not loaded properlyJohn Crispin2012-08-231-1/+1
| | | | | | | | | | | | | | | | Support for the external interrupt unit was broken when the code was converted to devicetree support. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4231/
* | MIPS: lantiq: dont register irq_chip for the irq cascadeJohn Crispin2012-08-231-0/+3
| | | | | | | | | | | | | | We dont want to register the irq_chip for the MIPS IRQ cascade. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4230/
* | MIPS: lantiq: timer irq can be different to 7John Crispin2012-08-231-3/+16
| | | | | | | | | | | | | | | | The SVIP SoC has its timer IRQ on a different IRQ than 7. Fix up the irq code to be able to handle this. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4229/
* | MIPS: lantiq: split up IRQ IM rangesJohn Crispin2012-08-231-28/+32
|/ | | | | | | | Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate the SVIP we need to support IM ranges that are scattered inside the register range. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4237/
* MIPS: Lantiq: Platform specific CLK fixupJohn Crispin2012-08-011-0/+5
| | | | | | | | | | As we use CLKDEV_LOOKUP but dont have support for COMMON_CLK yet, we need to provide our own version of of_clk_get_from_provider(). Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4117/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add device_tree_init functionJohn Crispin2012-08-011-0/+22
| | | | | | | | | | | | | | | | Add a lantiq specific version of device_tree_init. The generic MIPS version was removed by. commit 594e966bc412d64eec9282d28ce511bdd62fea39 Author: David Daney <david.daney@cavium.com> Date: Thu Jul 5 18:12:38 2012 +0200 MIPS: Prune some target specific code out of prom.c Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4116/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Fix interface clock and PCI control register offsetJohn Crispin2012-08-011-21/+28
| | | | | | | | | | | The XRX200 based SoC have a different register offset for the interface clock and PCI control registers. This patch detects the SoC and sets the register offset at runtime. This make PCI work on the VR9 SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4113/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2012-05-2942-1583/+1791
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "The whole series has been sitting in -next for quite a while with no complaints. The last change to the series was before the weekend the removal of an SPI patch which Grant - even though previously acked by himself - appeared to raise objections. So I removed it until the situation is clarified. Other than that all the patches have the acks from their respective maintainers, all MIPS and x86 defconfigs are building fine and I'm not aware of any problems introduced by this series. Among the key features for this patch series is a sizable patchset for Lantiq which among other things introduces support for Lantiq's flagship product, the FALCON SOC. It also means that the opensource developers behind this patchset have overtaken Lantiq's competing inhouse development team that was working behind closed doors. Less noteworthy the ath79 patchset which adds support for a few more chip variants, cleanups and fixes. Finally the usual dose of tweaking of generic code." Fix up trivial conflicts in arch/mips/lantiq/xway/gpio_{ebu,stp}.c where printk spelling fixes clashed with file move and eventual removal of the printk. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (81 commits) MIPS: lantiq: remove orphaned code MIPS: Remove all -Wall and almost all -Werror usage from arch/mips. MIPS: lantiq: implement support for FALCON soc MTD: MIPS: lantiq: verify that the NOR interface is available on falcon soc MTD: MIPS: lantiq: implement OF support watchdog: MIPS: lantiq: implement OF support and minor fixes SERIAL: MIPS: lantiq: implement OF support GPIO: MIPS: lantiq: convert gpio-stp-xway to OF GPIO: MIPS: lantiq: convert gpio-mm-lantiq to OF and of_mm_gpio GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder MIPS: pci: convert lantiq driver to OF MIPS: lantiq: convert dma to platform driver MIPS: lantiq: implement support for clkdev api MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq() OF: MIPS: lantiq: implement irq_domain support OF: MIPS: lantiq: implement OF support MIPS: lantiq: drop mips_machine support OF: PCI: const usage needed by MIPS MIPS: Cavium: Remove smp_reserve_lock. MIPS: Move cache setup to setup_arch(). ...
| * MIPS: lantiq: remove orphaned codeJohn Crispin2012-05-262-6/+4
| | | | | | | | | | | | | | | | | | | | Now that all drivers are converted to OF we are able to remove some remaining pieces of orphaned code. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3841/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: lantiq: implement support for FALCON socJohn Crispin2012-05-217-0/+444
| | | | | | | | | | | | | | | | | | | | Adds support for the FALCON SoC. This SoC is from the FTTH/GPON SoC family. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3814/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folderJohn Crispin2012-05-213-279/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the 2 drivers from arch/mips/lantiq/xway/ to the subsystem and make them buildable. The following 2 patches will convert the drivers to OF. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Acked-by: Grant Likely <grant.likely@secretlab.ca> Patchwork: https://patchwork.linux-mips.org/patch/3838/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: pci: convert lantiq driver to OFJohn Crispin2012-05-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | Implement support for OF inside the lantiq PCI driver. The patch also splits pcibios_plat_dev_init and pcibios_map_irq out into their own file to accomodate coexistance with the upcoming pcie driver. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3806/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: lantiq: convert dma to platform driverJohn Crispin2012-05-211-22/+39
| | | | | | | | | | | | | | | | | | Add code to make the dma driver load as a platform device from the devicetree. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3824/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: lantiq: implement support for clkdev apiJohn Crispin2012-05-219-463/+662
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch unifies all clock generation and gating code into one file. All drivers will now be able to request their clocks via their device. This patch also adds support for the clockout feature, which allows clock generation on external pins. Support for COMMON_CLK will be provided in the next series. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq()John Crispin2012-05-212-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of the conversion to OF we also implement pinctrl drivers. Previously we used ltq_gpio_request() to set pinmuxing. This is now obselete and we can hence drop the function. Additionally we remove gpio_to_irq() from the gpio driver and move it to a header file. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3801/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * OF: MIPS: lantiq: implement irq_domain supportJohn Crispin2012-05-211-76/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for irq_domain on lantiq socs. The conversion is straight forward as the ICU found inside the socs allows the usage of irq_domain_add_linear. Harware IRQ 0->7 are the generic MIPS IRQs. 8->199 are the Lantiq IRQ Modules. Our irq_chip callbacks need to substract 8 (MIPS_CPU_IRQ_CASCADE) from d->hwirq to find out the correct offset into the Interrupt Modules register range. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: Grant Likely <grant.likely@secretlab.ca> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3802/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * OF: MIPS: lantiq: implement OF supportJohn Crispin2012-05-2110-77/+293
| | | | | | | | | | | | | | | | | | | | | | Activate USE_OF, add a sample DTS file and convert the core soc code to OF. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3803/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: lantiq: drop mips_machine supportJohn Crispin2012-05-2115-528/+4
| | | | | | | | | | | | | | | | | | | | Before we are able to add OF support, we really want to drop all the bloat needed to register all the platform devices. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3800/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: lantiq: cleanup reset codeJohn Crispin2012-05-151-12/+36
| | | | | | | | | | | | | | | | | | Add 2 new soc specifc handlers and remove superflous pr_notice calls. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: lantiq: add xway soc idsJohn Crispin2012-05-155-96/+123
| | | | | | | | | | | | | | | | | | | | Add the soc ids for additional xway socs. The patch also merges the amazon_se code with the other socs. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: lantiq: fix cmdline parsingThomas Langer2012-05-151-2/+4
| | | | | | | | | | | | | | | | | | | | | | The code tested if the KSEG1 mapped address of argv was != 0. We need to use CPHYSADDR instead to make the conditional actually work. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3722/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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