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* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2012-07-208-32/+73
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull late MIPS fixes from Ralf Baechle: "This fixes a number of lose ends in the MIPS code and various bug fixes. Aside of dropping some patch that should not be in this pull request everything has sat in -next for quite a while and there are no known issues. The biggest patch in this patch set moves the allocation of an array that is aliased to a function (for runtime generated code) to assembler code. This avoids an issue with certain toolchains when building for microMIPS." * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (35 commits) MIPS: PCI: Move fixups from __init to __devinit. MIPS: Fix bug.h MIPS build regression MIPS: sync-r4k: remove redundant irq operation MIPS: smp: Warn on too early irq enable MIPS: call set_cpu_online() on cpu being brought up with irq disabled MIPS: call ->smp_finish() a little late MIPS: Yosemite: delay irq enable to ->smp_finish() MIPS: SMTC: delay irq enable to ->smp_finish() MIPS: BMIPS: delay irq enable to ->smp_finish() MIPS: Octeon: delay enable irq to ->smp_finish() MIPS: Oprofile: Fix build as a module. MIPS: BCM63XX: Fix BCM6368 IPSec clock bit MIPS: perf: Fix build error caused by unused counters_per_cpu_to_total() MIPS: Fix Magic SysRq L kernel crash. MIPS: BMIPS: Fix duplicate header inclusion. mips: mark const init data with __initconst instead of __initdata MIPS: cmpxchg.h: Add missing include MIPS: Malta may also be equipped with MIPS64 R2 processors. MIPS: Fix typo multipy -> multiply MIPS: Cavium: Fix duplicate ARCH_SPARSEMEM_ENABLE in kconfig. ...
| * MIPS: PCI: Move fixups from __init to __devinit.Sebastian Andrzej Siewior2012-07-196-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixups are executed once the pci-device is found which is during boot process so __init seems fine as long as the platform does not support hotplug. However it is possible to remove the PCI bus at run time and have it rediscovered again via "echo 1 > /sys/bus/pci/rescan" and this will call the fixups again. [ralf@linux-mips.org: Made piixirqmap[] in malta_piix_func0_fixup() __initdata.] Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * mips: mark const init data with __initconst instead of __initdataUwe Kleine-König2012-07-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As long as there is no other non-const variable marked __initdata in the same compilation unit it doesn't hurt. If there were one however compilation would fail with error: $variablename causes a section type conflict because a section containing const variables is marked read only and so cannot contain non-const variables. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: linux-mips@linux-mips.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: kernel@pengutronix.de Patchwork: https://patchwork.linux-mips.org/patch/3565/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Netlogic: MSI enable fix for XLSGanesan Ramalingam2012-07-031-9/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MSI interrupts do not work on XLS after commit a776c49 ( "PCI: msi: Disable msi interrupts when we initialize a pci device" ) because the change disables MSI interrupts on the XLS PCIe bridges during the PCI enumeration. Fix this by enabling MSI interrupts on the bridge in the arch_setup_msi_irq() function. A new function xls_get_pcie_link() has been introduced to get the PCI device corresponding to the top level PCIe bridge on which MSI has to be enabled. Also, update get_irq_vector() to use the new xls_get_pcie_link() function and PCI_SLOT() macro for determining the IRQ of PCI devices. Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3753/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * MIPS: Netlogic: Fix PCIX irq on XLR chipsJayachandran C2012-07-031-1/+1
| | | | | | | | | | | | | | | | | | The correct irq is PIC_PCIX_IRQ Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3750/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | mips: pci-lantiq: Fix check for valid gpioRoland Stigge2012-07-051-2/+2
|/ | | | | | | | This patch fixes two checks for valid gpio number, formerly (wrongly) considering zero as invalid, now using gpio_is_valid(). Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
*---. Merge branches 'fixes-for-linus', 'generic', 'cavium', 'module.h-fixes', ↵Ralf Baechle2012-05-267-310/+851
|\ \ \ | | | | | | | | | | | | 'next/ath79' and 'next/lantiq' into mips-for-linux-next
| | | * MIPS: pci: convert lantiq driver to OFJohn Crispin2012-05-213-93/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement support for OF inside the lantiq PCI driver. The patch also splits pcibios_plat_dev_init and pcibios_map_irq out into their own file to accomodate coexistance with the upcoming pcie driver. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3806/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | * MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq()John Crispin2012-05-211-43/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of the conversion to OF we also implement pinctrl drivers. Previously we used ltq_gpio_request() to set pinmuxing. This is now obselete and we can hence drop the function. Additionally we remove gpio_to_irq() from the gpio driver and move it to a header file. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3801/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | * MIPS: pci: parse memory ranges from devicetreeJohn Crispin2012-05-151-0/+55
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit bus width is supported. This function is based on pci_process_bridge_OF_ranges from powerpc. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3729/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: add PCI_AR724X Kconfig symbolGabor Juhos2012-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AR724X specific PCI code can be used for the AR934X SoCs, however it can be selected only if SOC_AR724X is set. Introduce a new Kconfig symbol in order to be able to use the code for AR934X as well. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com> Cc: linux-mips@linux-mips.org Cc: mcgrof@infradead.org Patchwork: https://patchwork.linux-mips.org/patch/3514/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: update copyright headers of PCI related filesGabor Juhos2012-05-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add copyright records according to the recent changes in the PCI code. Also fix up the descriptions. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3503/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: add support for the PCI host controller of the AR71XX SoCsGabor Juhos2012-05-152-0/+376
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Atheros AR71XX SoCs have a built-in PCI Host Controller. This patch adds a driver for that, and modifies the relevant files in order to allow to register the PCI controller from board specific setup. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3498/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: add PCI IRQ handling code for AR724X SoCsGabor Juhos2012-05-151-2/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI Host Controller of the AR724x SoC has a built-in IRQ controller. The current code does not supports that, so the IRQ lines wired to this controller are not usable. This leads to failed 'request_irq' calls: ath9k 0000:00:00.0: request_irq failed ath9k: probe of 0000:00:00.0 failed with error -89 This patch adds support for the IRQ controller in order to make PCI IRQs work. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3496/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: add a workaround for a PCI controller bug in AR7240 SoCsGabor Juhos2012-05-151-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI controller of the AR724X SoCs has a hardware bag. If the BAR0 register of the PCI device is set to the proper base address, the memory address space of the device is not accessible. When the device driver tries to access the memory address space of the PCI device, it leads to data bus error, similiar to this: Data bus error, epc == 801f69a0, ra == 801f698c Oops[#1]: Cpu 0 $ 0 : 00000000 00000061 deadbeef 000000ff $ 4 : 00000000 000000ff 00000014 00000000 $ 8 : ff000000 fffffffc 00000000 00000000 $12 : 000001f5 00000006 00000000 6e637920 $16 : 81ca4000 81ca0260 81ca4000 804d70f0 $20 : fffffff4 0000002b 803ad4c4 00000000 $24 : 00000003 00000000 $28 : 81c20000 81c21c60 00000000 801f698c Hi : 00000000 Lo : 00000000 epc : 801f69a0 ath9k_hw_init+0xd0/0xa70 Not tainted ra : 801f698c ath9k_hw_init+0xbc/0xa70 Status: 1000c103 KERNEL EXL IE Cause : 1080001c PrId : 00019374 (MIPS 24Kc) Modules linked in: Process swapper (pid: 1, threadinfo=81c20000, task=81c18000, tls=00000000) Stack : 00000000 00000000 00000000 00000000 81c21c78 81ca0260 00000000 804d70f0 81ca0260 81c21cc0 81ca0e80 81ca0260 81ca4000 804d70f0 fffffff4 0000002b 803ad4c4 00000000 00000000 801e3ae8 81c9d080 81ca0e80 b0000000 800b9b9c 00000008 81c9d000 8031aeb0 802d38a0 00000000 81c14c00 81c14c60 00000000 81ca0e80 81ca0260 b0000000 801f08a4 81c9c820 81c21d48 81c9c820 80144320 ... Call Trace: [<801f69a0>] ath9k_hw_init+0xd0/0xa70 [<801e3ae8>] ath9k_init_device+0x174/0x680 [<801f08a4>] ath_pci_probe+0x27c/0x380 [<8019e490>] pci_device_probe+0x74/0x9c [<801bfadc>] driver_probe_device+0x9c/0x1b4 [<801bfcb0>] __driver_attach+0xbc/0xc4 [<801bea0c>] bus_for_each_dev+0x5c/0x98 [<801bf394>] bus_add_driver+0x1d0/0x2a4 [<801c0364>] driver_register+0x8c/0x16c [<8019e72c>] __pci_register_driver+0x4c/0xe4 [<803d3d40>] ath9k_init+0x3c/0x88 [<80060930>] do_one_initcall+0x3c/0x1cc [<803c297c>] kernel_init+0xa4/0x138 [<80063c04>] kernel_thread_helper+0x10/0x18 Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3494/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: fix broken ar724x_pci_{read,write} functionsGabor Juhos2012-05-151-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ar724x_pci_{read,write} functions are broken. Due to that, pci_read_config_byte returns with bogus values, and pci_write_config_{byte,word} unconditionally clears the accessed PCI configuration registers instead of changing the value of them. The patch fixes the broken functions, thus the PCI configuration space can be accessed correctly. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3493/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: remove superfluous alignment checks from pci-ar724x.cGabor Juhos2012-05-151-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The alignment of the 'where' parameters are checked in the core PCI code already. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3492/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: use io-accessor macros in pci-ar724x.cGabor Juhos2012-05-151-14/+24
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: René Bolldorf <xsecute@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3491/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: replace ath724x to ar724xGabor Juhos2012-05-151-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the 'ath724x' to 'ar724x' in function, variable and structure names to reflect the name of the real SoC. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: René Bolldorf <xsecute@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3490/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC nameGabor Juhos2012-05-152-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: René Bolldorf <xsecute@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3489/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: add a common PCI registration functionGabor Juhos2012-05-151-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code unconditionally registers the AR724X specific PCI controller, even if the kernel is running on a different SoC. Add a common function for PCI controller registration, and only register the AR724X PCI controller if the kernel is running on an AR724X SoC. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3488/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: make ath724x_pcibios_init visible for external codeGabor Juhos2012-05-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: René Bolldorf <xsecute@googlemail.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3487/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * MIPS: ath79: separate common PCI codeGabor Juhos2012-05-151-34/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'pcibios_map_irq' and 'pcibios_plat_dev_init' are common functions and only instance one of them can be present in a single kernel. Currently these functions can be built only if the CONFIG_SOC_AR724X option is selected. However the ath79 platform contain support for the AR71XX SoCs,. The AR71XX SoCs have a differnet PCI controller, and those will require a different code. Move the common PCI code into a separeate file in order to be able to use that with other SoCs as well. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Acked-by: René Bolldorf <xsecute@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3485/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* / MIPS: Include export.h in for EXPORT_SYMBOL in ops-loongson2.cMatt Turner2012-05-151-0/+1
|/ | | | | | | | | | | | Fixes warning: data definition has no type or storage class [enabled by default] warning: type defaults to 'int' in declaration of 'EXPORT_SYMBOL' [-Wimplicit-int] warning: parameter names (without types) in function declaration [enabled by default] Signed-off-by: Matt Turner <mattst88@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3746/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'linux-next' of ↵Linus Torvalds2012-03-237-143/+15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci Pull PCI changes (including maintainer change) from Jesse Barnes: "This pull has some good cleanups from Bjorn and Yinghai, as well as some more code from Yinghai to better handle resource re-allocation when enabled. There's also a new initcall_debug feature from Arjan which will print out quirk timing information to help identify slow quirks for fixing or refinement (Yinghai sent in a few patches to do just that once the new debug code landed). Beyond that, I'm handing off PCI maintainership to Bjorn Helgaas. He's been a core PCI and Linux contributor for some time now, and has kindly volunteered to take over. I just don't feel I have the time for PCI review and work that it deserves lately (I've taken on some other projects), and haven't been as responsive lately as I'd like, so I approached Bjorn asking if he'd like to manage things. He's going to give it a try, and I'm confident he'll do at least as well as I have in keeping the tree managed, patches flowing, and keeping things stable." Fix up some fairly trivial conflicts due to other cleanups (mips device resource fixup cleanups clashing with list handling cleanup, ppc iseries removal clashing with pci_probe_only cleanup etc) * 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci: (112 commits) PCI: Bjorn gets PCI hotplug too PCI: hand PCI maintenance over to Bjorn Helgaas unicore32/PCI: move <asm-generic/pci-bridge.h> include to asm/pci.h sparc/PCI: convert devtree and arch-probed bus addresses to resource powerpc/PCI: allow reallocation on PA Semi powerpc/PCI: convert devtree bus addresses to resource powerpc/PCI: compute I/O space bus-to-resource offset consistently arm/PCI: don't export pci_flags PCI: fix bridge I/O window bus-to-resource conversion x86/PCI: add spinlock held check to 'pcibios_fwaddrmap_lookup()' PCI / PCIe: Introduce command line option to disable ARI PCI: make acpihp use __pci_remove_bus_device instead PCI: export __pci_remove_bus_device PCI: Rename pci_remove_behind_bridge to pci_stop_and_remove_behind_bridge PCI: Rename pci_remove_bus_device to pci_stop_and_remove_bus_device PCI: print out PCI device info along with duration PCI: Move "pci reassigndev resource alignment" out of quirks.c PCI: Use class for quirk for usb host controller fixup PCI: Use class for quirk for ti816x class fixup PCI: Use class for quirk for intel e100 interrupt fixup ...
| * mips/PCI: get rid of device resource fixupsBjorn Helgaas2012-02-232-128/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tell the PCI core about host bridge address translation so it can take care of bus-to-resource conversion for us. Here's the wrinkle on Cobalt: we can't generate normal I/O port addresses on PCI because the GT-64111 doesn't do any address translation, so we have this: CPU I/O port addresses [io 0x0000-0xffffff] PCI bus I/O port addresses [io 0x10000000-0x10ffffff] Legacy-mode IDE controllers start out with the legacy bus addresses, e.g., 0x1f0, assigned by pci_setup_device(). These are outside the range of addresses GT-64111 can generate on PCI, but pcibios_fixup_device_resources() converted them to CPU addresses anyway by adding io_offset. Therefore, we had to pre-adjust them in cobalt_legacy_ide_fixup(). With io_offset = 0xf0000000, we had this: res->start = 0x1f0 initialized in pci_setup_device() res->start = 0x100001f0 -= io_offset in cobalt_legacy_ide_fixup() res->start = 0x1f0 += io_offset in pcibios_fixup_device_resources() The difference after this patch is that the generic pci_bus_to_resource() only adds the offset if the bus address is inside a host bridge window. Since 0x1f0 is not a valid bus address and is not inside any windows, it is unaffected, so we now have this: region->start = 0x1f0 initialized in pci_setup_device() res->start = 0x1f0 no offset by pci_bus_to_resource() That means we can remove both pcibios_fixup_device_resources() and cobalt_legacy_ide_fixup(). I would *rather* set the host bridge offset to zero (which corresponds to what the GT-64111 actually does), and have both CPU and PCI addresses of [io 0x10000000-0x10ffffff]. However, that would require changes to generic code that assumes legacy I/O addresses, such as pic1_io_resource ([io 0x0020-0x00021]), and we'd have to keep a Cobalt IDE fixup. Of course, none of this changes the fact that references to I/O port 0x1f0 actually go to port 0x100001f0, not 0x1f0, on the Cobalt PCI bus. Fortunately the VT82C586 IDE controller only decodes the low 24 address bits, so it does work. CC: Ralf Baechle <ralf@linux-mips.org> CC: Yoichi Yuasa <yuasa@linux-mips.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * mips/PCI: removed unused pci_probe configurabilityBjorn Helgaas2012-02-231-5/+1
| | | | | | | | | | | | | | | | | | | | | | We never assign anything other than PCI_ASSIGN_ALL_BUSSES to pci_probe, so just remove the indirection. If configurability is required in the future, please use the pci_flags/PCI_REASSIGN_ALL_BUS functionality as is done for powerpc. CC: Ralf Baechle <ralf@linux-mips.org> CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * mips/PCI: replace pci_probe_only with pci_flagsBjorn Helgaas2012-02-236-13/+11
| | | | | | | | | | | | | | | | | | | | | | Some architectures (alpha, mips, powerpc) have an arch-specific "pci_probe_only" flag. Others use PCI_PROBE_ONLY in pci_flags for the same purpose. This moves mips to the pci_flags approach so generic code can use the same test across all architectures. CC: Ralf Baechle <ralf@linux-mips.org> CC: linux-mips@linux-mips.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2012-03-051-4/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/net/vmxnet3/vmxnet3_drv.c Small vmxnet3 conflict with header size bug fix in 'net'. Signed-off-by: David S. Miller <davem@davemloft.net>
| * | MIPS: PCI: use list_for_each_entry() for bus->devices traversalBjorn Helgaas2012-02-201-4/+1
| |/ | | | | | | | | | | | | | | | | | | Replace open-coded list traversal with list_for_each_entry(). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3200/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | Merge branch 'master' of ↵John W. Linville2012-02-1514-417/+1436
|\| | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless Conflicts: net/mac80211/debugfs_sta.c net/mac80211/sta_info.h
| * Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2012-01-1414-417/+1436
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (119 commits) MIPS: Delete unused function add_temporary_entry. MIPS: Set default pci cache line size. MIPS: Flush huge TLB MIPS: Octeon: Remove SYS_SUPPORTS_HIGHMEM. MIPS: Octeon: Add support for OCTEON II PCIe MIPS: Octeon: Update PCI Latency timer and enable more error reporting. MIPS: Alchemy: Update cpu-feature-overrides MIPS: Alchemy: db1200: Improve PB1200 detection. MIPS: Alchemy: merge Au1000 and Au1300-style IRQ controller code. MIPS: Alchemy: chain IRQ controllers to MIPS IRQ controller MIPS: Alchemy: irq: register pm at irq init time MIPS: Alchemy: Touchscreen support on DB1100 MIPS: Alchemy: Hook up IrDA on DB1000/DB1100 net/irda: convert au1k_ir to platform driver. MIPS: Alchemy: remove unused board headers MTD: nand: make au1550nd.c a platform_driver MIPS: Netlogic: Mark Netlogic chips as SMT capable MIPS: Netlogic: Add support for XLP 3XX cores MIPS: Netlogic: Merge some of XLR/XLP wakup code MIPS: Netlogic: Add default XLP config. ... Fix up trivial conflicts in arch/mips/kernel/{perf_event_mipsxx.c, traps.c} and drivers/tty/serial/Makefile
| | *---------. Merge branches 'next/ar7', 'next/ath79', 'next/bcm63xx', 'next/bmips', ↵Ralf Baechle2012-01-116-340/+1334
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | 'next/cavium', 'next/generic', 'next/kprobes', 'next/lantiq', 'next/perf' and 'next/raza' into mips-for-linux-next
| | | | | | | | * MIPS: Netlogic: Move code common with XLP to common/Jayachandran C2011-12-071-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move code that can be shared with XLP (irq.c, smp.c, time.c and xlr_console.c) to arch/mips/netlogic/common - Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and io functions shared with XLP - remove type 'nlm_reg_t *' and use uint64_t for mmio offsets - Move XLR specific code in smp.c to xlr/wakeup.c - Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c - Provide API for pic functions called from common/irq.c Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2964/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | * MIPS: Netlogic: Use CPU_XLR instead of NLM_XLRJayachandran C2011-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU_XLR config variable is sufficient for XLR compilation, the variable NLM_XLR can be removed. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | | | * MIPS: Netlogic: Add basic MSI support for XLR/XLSGanesan Ramalingam2011-12-071-1/+50
| | | | |_|_|_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic support for MSI. Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2730/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | MIPS: Octeon: Add support for OCTEON II PCIeDavid Daney2011-12-081-326/+1023
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OCTEON II SOCs have a different PCIe implementation than is present in OCTEON Plus. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2985/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | | * | MIPS: Octeon: Update PCI Latency timer and enable more error reporting.David Daney2011-12-081-10/+6
| | | | |_|/ / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2987/ Patchwork: https://patchwork.linux-mips.org/patch/3161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | | * | MIPS: BCM63XX: Add support for bcm6368 CPU.Maxime Bizon2011-12-071-2/+2
| | | | |/ / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2892/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | | | * | MIPS: Initial PCI support for Atheros 724x SoCs.Rene Bolldorf2011-12-072-0/+175
| | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ralf@linux-mips.org: Fixed the odd formatting of all break statements.] Signed-off-by: Rene Bolldorf <xsecute@googlemail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/3019/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | | Merge branch 'next/generic' into mips-for-linux-nextRalf Baechle2012-01-116-6/+33
| | |\ \ \ | | | | |/ | | | |/|
| | | * | MIPS: Set default pci cache line size.Ralf Baechle2012-01-111-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On MIPS the generic PCI code has always defaulted to L1_CACHE_BYTES because the architecutre PCI code did not provide a better default. In particular on systems with S-caches or T-caches this was suboptimal. Provide a better default by setting pci_dfl_cache_line_size based on the size of the line size of the lowest level of the cache hierarchy. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2982/
| | | * | MIPS: irq: Remove IRQF_DISABLEDYong Zhang2011-12-075-5/+5
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit [e58aa3d2: genirq: Run irq handlers with interrupts disabled], We run all interrupt handlers with interrupts disabled and we even check and yell when an interrupt handler returns with interrupts enabled (see commit [b738a50a: genirq: Warn when handler enables interrupts]). So now this flag is a NOOP and can be removed. [ralf@linux-mips.org: Fixed up conflicts in arch/mips/alchemy/common/dbdma.c, arch/mips/cavium-octeon/smp.c and arch/mips/kernel/perf_event.c.] Signed-off-by: Yong Zhang <yong.zhang0@gmail.com> To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2835/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Fix Jazz 64-bit build error.Ralf Baechle2011-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move add_wired_entry to its own header file from where it will be always included. Patch up other users of add_wired_entry to also include the header as needed. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Fix up inconsistency in panic() string argument.Ralf Baechle2011-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Panic() invokes printk() to add a \n internally, so panic arguments should not themselves end in \n. Panic invocations in arch/mips and elsewhere are inconsistently sometimes terminating in \n, sometimes not. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| | * | MIPS: Alchemy: Fix PCI PMManuel Lauss2011-12-071-70/+67
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move PCI Controller PM to syscore_ops since the platform_driver PM methods are called way too late on resume and far too early on suspend (after and before PCI device resume/suspend). This also allows to simplify wired entry management a bit. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | / bcma: add PCIe host controllerHauke Mehrtens2012-02-061-5/+44
|/ / | | | | | | | | | | | | | | | | | | Some SoCs have a PCIe host controller to make it possible to attach some other devices to it, like an other Wifi card. This code was tested with an Netgear WNDR3400 (bcm4716 based), but should work with all bcma based SoCs. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* | mips/PCI: convert to pci_scan_root_bus() for correct root bus resourcesBjorn Helgaas2012-01-061-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert from pci_scan_bus() to pci_scan_root_bus() and remove root bus resource fixups. This fixes the problem of "early" and "header" quirks seeing incorrect root bus resources. Based on original patch by Deng-Cheng Zhu. Reference: https://lkml.org/lkml/2011/8/26/89 CC: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Deng-Cheng Zhu <dczhu@mips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | PCI: MIPS: use generic pcibios_set_master()Myron Stowe2012-01-061-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | This patch removes MIPS' architecture-specific 'pcibios_set_master()' routine and lets the default PCI core based implementation handle PCI device 'latency timer' setup. No functional change. Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | PCI: Pull PCI 'latency timer' setup up into the coreMyron Stowe2012-01-061-6/+0
|/ | | | | | | | | | | | | | | | | | | | The 'latency timer' of PCI devices, both Type 0 and Type 1, is setup in architecture-specific code [see: 'pcibios_set_master()']. There are two approaches being taken by all the architectures - check if the 'latency timer' is currently set between 16 and 255 and if not bring it within bounds, or, do nothing (and then there is the gratuitously different PA-RISC implementation). There is nothing architecture-specific about PCI's 'latency timer' so this patch pulls its setup functionality up into the PCI core by creating a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over-ridden by architecture-specific code. No functional change. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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