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| * MIPS: Kill CONFIG_MTD_PARTITIONSEunbong Song2014-01-2411-11/+0
| * MIPS: replace open-coded init_dspPaul Burton2014-01-241-2/+1
| * MIPS: clean up resume declarationPaul Burton2014-01-241-4/+12
| * MIPS: qi_lb60: add defconfig for Ben NanoNoteApelete Seketeli2014-01-241-0/+188
| * MIPS: include linux/types.hQais Yousef2014-01-231-0/+1
| * MIPS: sead3: use unflatten_and_copy_device_tree()Qais Yousef2014-01-231-10/+1
| * MIPS: sead3: populate platform devices from device treeQais Yousef2014-01-231-0/+7
| * MIPS: sead3: remove chosen nodeQais Yousef2014-01-231-4/+0
| * MIPS: sead3: allow cmdline/env to change memory size using memsize paramQais Yousef2014-01-233-0/+71
| * MIPS: BCM63XX: use linux/serial_bcm63xx.hFlorian Fainelli2014-01-232-8/+1
| * MIPS: BCM63XX: move UART register definitionsFlorian Fainelli2014-01-231-114/+1
| * MIPS: microMIPS: Remove unsupported compiler flag.Steven J. Hill2014-01-231-1/+1
| * MIPS: OCTEON: Supply OCTEON+ USB nodes in internal device trees.David Daney2014-01-234-0/+87
| * MIPS: Malta: use generic 8250 early consolePaul Burton2014-01-234-75/+33
| * MIPS: Malta: mux & enable SERIRQ interruptPaul Burton2014-01-232-0/+18
| * MIPS: Malta: initialise the RTC at bootPaul Burton2014-01-231-0/+13
| * MIPS: sead3: remove unused cpu_khz variablePaul Burton2014-01-231-4/+0
| * MIPS: Malta: remove unused cpu_khz variablePaul Burton2014-01-231-3/+0
| * MIPS: cavium-octeon: export symbols needed by octeon-ethernetAaro Koskinen2014-01-235-1/+16
| * MIPS: Fix build error seen in some configurationsGuenter Roeck2014-01-231-1/+1
| * MIPS: cavium-octeon: fix early boot hang on EBH5600 boardAaro Koskinen2014-01-231-3/+3
| * MIPS: cavium-octeon: fix out-of-bounds array accessAaro Koskinen2014-01-231-1/+1
| * MIPS: JZ4740: reuse UART0 address macro for vmlinuz debug portAntony Pavlov2014-01-231-2/+2
| * MIPS: improve checks for noncoherent DMAFelix Fietkau2014-01-224-5/+16
| * MIPS: APRP: Code formatting clean-ups.Steven J. Hill2014-01-229-320/+248
| * MIPS: APRP: Add support for Malta CMP platform.Deng-Cheng Zhu2014-01-223-5/+35
| * MIPS: APRP: Add RTLX API support for CMP platforms.Deng-Cheng Zhu2014-01-224-0/+123
| * MIPS: APRP: Split RTLX support into separate files.Deng-Cheng Zhu2014-01-225-144/+195
| * MIPS: APRP: Add VPE loader support for CMP platforms.Deng-Cheng Zhu2014-01-223-0/+186
| * MIPS: APRP: Split VPE loader into separate files.Deng-Cheng Zhu2014-01-225-633/+660
| * MIPS: Clean up MIPS MT and CMP configuration options.Steven J. Hill2014-01-222-40/+24
| * MIPS: kernel: cpu-probe: Add support for probing interAptiv coresLeonid Yegoshin2014-01-221-0/+8
| * MIPS: Add support for interAptiv coresLeonid Yegoshin2014-01-229-1/+12
| * MIPS: Add processor identifiers for the interAptiv processorsLeonid Yegoshin2014-01-221-0/+2
| * MIPS: Add debugfs file to print the segmentation control registersSteven J. Hill2014-01-222-0/+111
| * MIPS: Add support for FTLBsLeonid Yegoshin2014-01-227-14/+155
| * MIPS: mm: Use the TLBINVF instruction to flush the VTLBLeonid Yegoshin2014-01-221-6/+12
| * MIPS: Add function for flushing the TLB using the TLBINV instructionLeonid Yegoshin2014-01-221-0/+13
| * MIPS: kernel: cpu-probe: Add support for probing proAptiv coresLeonid Yegoshin2014-01-221-0/+8
| * MIPS: Add support for the proAptiv coresLeonid Yegoshin2014-01-2210-1/+13
| * MIPS: Add processor identifiers for the proAptiv processorsLeonid Yegoshin2014-01-221-0/+2
| * MIPS: tlb: Set the EHINV bit for TLBINVF cores when invalidating the TLBLeonid Yegoshin2014-01-221-1/+3
| * MIPS: features: Add initial support for Segmentation Control registersSteven J. Hill2014-01-224-0/+36
| * MIPS: features: Add initial support for TLBINVF capable coresLeonid Yegoshin2014-01-223-0/+9
| * MIPS: mm: Move UNIQUE_ENTRYHI macro to a header fileMarkos Chandras2014-01-223-8/+3
| * MIPS: Add missing bits for Config registersLeonid Yegoshin2014-01-221-2/+38
| * MIPS: MT: proc: Add support for printing VPE and TC idsMarkos Chandras2014-01-221-1/+8
| * MIPS: Malta: Remove ttyS2 serial for CMP platformsLeonid Yegoshin2014-01-221-0/+2
| * MIPS: Add printing of ES bit for Imgtec cores when cache error occurs.Leonid Yegoshin2014-01-221-8/+21
| * MIPS: GIC: Send IPIs using the GICSteven J. Hill2014-01-221-0/+27
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