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path: root/arch/nios2/mm/tlb.c
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* nios2: Fix update_mmu_cache preload the TLB with the new PTENicholas Piggin2019-03-071-1/+2
| | | | | | | | | There is a bug in the TLB preload caused by the pid not being shifted to the correct location in tlbmisc register. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Tested-by: Guenter Roeck <linux@roeck-us.net>
* nios2: update_mmu_cache preload the TLB with the new PTENicholas Piggin2019-03-071-6/+26
| | | | | | | | | Rather than flush the TLB entry when installing a new PTE to allow the fast TLB reload to re-fill the TLB, just refill the TLB entry when removing the old one. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* nios2: User address TLB flush break after finding the matching entryNicholas Piggin2019-03-071-0/+5
| | | | | Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* nios2: flush_tlb_all use TLBMISC way auto-increment featureNicholas Piggin2019-03-071-6/+5
| | | | | | | | | Writes to TLBACC cause TLBMISC way to be incremented, which can be used to iterate over ways in a set, then wrap back to zero ready for the next set. This reduces register writes significantly. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* nios2: improve readability of tlb functionsNicholas Piggin2019-03-071-27/+33
| | | | | Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* nios2: flush_tlb_mm flush only the pidNicholas Piggin2019-03-071-12/+14
| | | | | | | | Currently flush_tlb_mm flushes the entire TLB. Switch it to doing a PID aware flush. This also improves the readibility of flush_tlb_pid. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* nios2: flush_tlb_pid can just restore TLBMISC onceNicholas Piggin2019-03-071-2/+2
| | | | | | | This matches the other functions in this file that use TLBMISC. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* nios2: TLBMISC writes do not require PID bits to be setNicholas Piggin2019-03-071-12/+7
| | | | | | | | | | TLBMISC_RD does not use PID bits, and when setting invalid TLBs, the PID is not required because the address will not match. This is just a tidy up. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* nios2: Use an invalid TLB entry address helper functionNicholas Piggin2019-03-071-35/+33
| | | | | | | | | | | | | There is no need for complicated calculation for an invalid address that maps to the same TLB index as the entry to be invalidated. Using the TLB address plus the two top bits set puts the address into the kernel TLB bypass range and still maps to the same cache line. This is also a bug fix for flush_tlb_pid, which is currently unused, but does not set PTEADDR to invalid. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* nios2: flush_tlb_page use PID based flushNicholas Piggin2019-03-071-9/+9
| | | | | | | | | | | | | | | | flush_tlb_page is for flushing user pages, so it should not be using flush_tlb_one (which flushes all pages). This patch implements it with the flush_tlb_range, which is a user flush that does the right thing. flush_tlb_one is made static to mm/tlb.c because it's a bit confusing. It is used in do_page_fault to flush the kernel non-linear mappings, so that is replaced with flush_tlb_kernel_page. The end result is that functionality is identical. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* nios2: TLB handlingLey Foon Tan2014-12-081-0/+275
This patch adds the TLB maintenance functions. Signed-off-by: Ley Foon Tan <lftan@altera.com>
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