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* powerpc/44x: Adjust indentation in ibm4xx_denali_fixup_memsizeNathan Chancellor2020-01-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Clang warns: ../arch/powerpc/boot/4xx.c:231:3: warning: misleading indentation; statement is not part of the previous 'else' [-Wmisleading-indentation] val = SDRAM0_READ(DDR0_42); ^ ../arch/powerpc/boot/4xx.c:227:2: note: previous statement is here else ^ This is because there is a space at the beginning of this line; remove it so that the indentation is consistent according to the Linux kernel coding style and clang no longer warns. Fixes: d23f5099297c ("[POWERPC] 4xx: Adds decoding of 440SPE memory size to boot wrapper library") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://github.com/ClangBuiltLinux/linux/issues/780 Link: https://lore.kernel.org/r/20191209200338.12546-1-natechancellor@gmail.com
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner2019-05-301-5/+1
| | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* powerpc/44x: Fix mask and shift to zero bugDan Carpenter2017-08-311-1/+1
| | | | | | | | | | | My static checker complains that 0x00001800 >> 13 is zero. Looking at the context, it seems like a copy and paste bug from the line below and probably 0x3 << 13 or 0x00006000 was intended. Fixes: 2af59f7d5c3e ("[POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapper") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* powerpc/44x: Fix UART clocks on 440SPeBenjamin Herrenschmidt2010-05-121-6/+6
| | | | | | | | | The code to fixup the serial ports on 440SPe uses the incorrect addresses for these. This fixes it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/405ex: provide necessary fixup function to support cuImageTiejun Chen2009-08-311-0/+142
| | | | | | | | | | For cuImage format it's necessary to provide clock fixups since u-boot will not pass necessary clock frequency into the dtb included into cuImage so we implement the clock fixups as defined in the technical documentation for the board and update header file with the basic register definitions. Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/44x: Correct memory size calculation for denali-based boardsValentine Barshak2009-04-241-13/+43
| | | | | | | | | | | | | | | | | | | Some U-Boot versions incorrectly set the number of chipselects to two for Sequoia/Rainier boards while they only have one chipselect hardwired. This patch adds a workaround for this, hardcoding the number of chipselects to one for sequioa/rainer board models and reading the actual value from the memory controller register DDR0_10 otherwise. It also fixes another error in the way ibm4xx_denali_fixup_memsize calculates memory size. When testing the DDR_REDUC bit, the polarity is backwards. A "1" implies 32-bit wide memory while a "0" implies 64-bit wide memory. Signed-off-by: Mikhail Zolotaryov <lebon@lebon.org.ua> Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Steven A. Falco <sfalco@harris.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Workaround for CHIP_11 ErrataJosh Boyer2008-05-191-0/+21
| | | | | | | | | | | | | | | | | The PowerPC 440EP, 440GR, 440EPx, and 440GRx chips have an issue that causes the PLB3-to-PLB4 bridge to wait indefinitely for transaction requests that cross the end-of-memory-range boundary. Since the DDR controller only returns the valid portion of a read request, the bridge will prevent other PLB masters from completing their transactions. This implements the recommended workaround for this errata for chips that use older versions of firmware that do not already handle it. The last 4KiB of memory are hidden from the kernel to prevent the problem transactions from occurring. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: logical/bitand typo in powerpc/boot/4xx.cRoel Kluin2008-01-251-1/+1
| | | | | | | logical/bitand typo Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapperMatthias Fuchs2008-01-081-7/+74
| | | | | | | | | | | | | | | This patch adds support for 405GPr processors with optional new mode strapping. ibm405gp_fixup_clocks() can now be used for 405GP and 405GPr CPUs. This is in preparation of porting the cpci405 platform support from arch/ppc to arch/powerpc. This patch also adds ibm405ep_fixup_clocks() to support 405EP CPUs from the boot wrapper. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Minor coding style cleanups for 4xx bootwrapperJosh Boyer2007-12-241-7/+6
| | | | | | Remove some unneeded braces and make a busy loop more obvious. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Rework clock probing in boot wrapperBenjamin Herrenschmidt2007-12-231-68/+204
| | | | | | | | | | | | | | | | This reworks the boot wrapper library function that probes the chip clocks. Better separate the base function that is used on 440GX,SPe,EP,... from the uart fixups as those need different device-tree path on different processors. Also, rework the function itself based on the arch/ppc code from Eugene Surovegin which I find more readable, and which handles one more bypass case. Also handle the subtle difference between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived from the PLB clock while on the later, it's derived from the OPB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Adds decoding of 440SPE memory size to boot wrapper libraryBenjamin Herrenschmidt2007-12-231-15/+70
| | | | | | | | This adds a function to the bootwrapper 4xx library to decode memory size on 440SPE processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: EP405 boards support for arch/powerpcBenjamin Herrenschmidt2007-12-231-1/+54
| | | | | | | | | | | | | | | | | Brings EP405 support to arch/powerpc. The IRQ routing for the CPLD comes from a device-tree property, PCI is working to the point where I can see the video card, USB device, and south bridge. This should work with both EP405 and EP405PC. I've not totally figured out how IRQs are wired on this hardware though, thus at this stage, expect only USB interrupts working, pretty much the same as what arch/ppc did. Also, the flash, nvram, rtc and temp control still have to be wired. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] arch/powerpc/: Spelling fixesjoe@perches.com2007-12-201-1/+1
| | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] PowerPC 440EPx: Sequoia bootwrapperValentine Barshak2007-09-071-0/+108
| | | | | | | | Bootwrapper code for AMCC PPC440EPx Sequoia. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] Bamboo zImage wrapperJosh Boyer2007-08-201-0/+82
| | | | | | | | Add a bootwrapper for the AMCC 440EP Bamboo Eval board. This also adds a common fixup_clock function for all 440EP(x) chips. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: David Gibson <david@gibson.dropbear.id.au>
* [POWERPC] 4xx bootwrapper reworksJosh Boyer2007-08-201-5/+30
| | | | | | | | Make the fixup_memsize function common for all of 4xx as several chips share the same SDRAM controller. Also add functions to reset 40x chips and quiesce the ethernet. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] Rename 44x bootwrapperJosh Boyer2007-08-201-0/+85
Rename the 44x.c wrapper file to 4xx.c. This will allow us to add common functions in a single file that can be shared across all of 4xx. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: David Gibson <david@gibson.dropbear.id.au>