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path: root/arch/powerpc/boot/dts/p1020rdb.dts
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* powerpc/fsl: Move Freescale device tree files into fsl folderHongtao Jia2015-10-171-66/+0
| | | | | | | | | | | | | | It makes no sense that some Freescale device tree files are in fsl directory while some others not. This patch move Freescale device tree files into fsl folder. To do that the following two steps are made: - Move Freescale device tree files into fsl folder. - Update the include path in these files from "fsl/*.dtsi" to "*.dtsi". Please add "fsl/" prefix when you make dtb using Makefile. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> [scottwood: fixed cuImage rule] Signed-off-by: Scott Wood <scottwood@freescale.com>
* powerpc/85xx: Rework P1020RDB device treeKumar Gala2011-11-241-224/+8
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Update SPI binding to match binding spec for P1020RDBKumar Gala2011-11-241-17/+13
| | | | | | | The SPI node is out of date with regards to the binding for fsl-espi and driver support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework PCI nodes on P1020RDBKumar Gala2011-11-241-24/+2
| | | | | | | | * Move SoC specific details like irq mapping to SoC dtsi * Update interrupt property to cover both error interrupt and PCIe runtime interrupts Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix PCIe IDSEL for Px020RDBPrabhakar Kushwaha2011-05-191-0/+16
| | | | | | | | | | | | | | PCIe device in legacy mode can trigger interrupts using the wires #INTA, #INTB ,#INTC and #INTD. PCI devices are obligated to use #INTx for interrupts under legacy mode. Each PCI slot or device is typically wired to different inputs on the interrupt controller. So, Define interrupt-map and interrupt-map-mask properties for device tree to of map each PCI interrupt signal to the inputs of the interrupt controller. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: P1020 DTS : re-organize dts filesPrabhakar Kushwaha2011-05-191-313/+3
| | | | | | | | | Creates P1020si.dtsi, containing information for the P1020 SoC. Modifies dts files for P1020 based systems to use dtsi file Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Grant Likely <grant.likelY@secretlab.ca> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Update dts for PCIe memory maps to match u-boot of Px020RDBPrabhakar Kushwaha2011-04-041-6/+6
| | | | | | | | | | PCIe memory address space is 1:1 mapped with u-boot. Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map changes in u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix P1020RDB boot hang due USB2Anton Vorontsov2010-05-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since USB2 is shared with local bus, either local bus or USB2 should be disabled. By default U-Boot enables local bus, so we have to disable USB2, otherwise kernel hangs: ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver fsl-ehci fsl-ehci.0: Freescale On-Chip EHCI Host Controller fsl-ehci fsl-ehci.0: new USB bus registered, assigned bus number 1 fsl-ehci fsl-ehci.0: irq 28, io base 0xffe22000 fsl-ehci fsl-ehci.0: USB 2.0 started, EHCI 1.00 hub 1-0:1.0: USB hub found hub 1-0:1.0: 1 port detected fsl-ehci fsl-ehci.1: Freescale On-Chip EHCI Host Controller fsl-ehci fsl-ehci.1: new USB bus registered, assigned bus number 2 <hangs here> Note that U-Boot doesn't clear 'status' property when it enables USB2, so we have to comment out the whole node. To enable USB2, one can issue 'setenv hwconfig usb2:dr_mode=<host|peripheral>' command at the U-Boot prompt. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add eTSEC 2.0 support for P1020RDB boardsAnton Vorontsov2010-05-171-0/+119
| | | | | | | | | | This patch adds support for eTSEC 2.0 as found in P1020. The changes include introduction of the group nodes for the etsec nodes. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Added P1020RDB Platform support.Poonam Aggrwal2009-11-111-0/+477
P1020 is another member of Freescale QorIQ series of processors. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences from P2020: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities(new controller). From board perspective P1020RDB is same as P2020RDB. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>