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* [POWERPC] fsl_soc: Fix get_immrbase() to use ranges, rather than reg.Scott Wood2008-01-231-2/+10
| | | | | | | | | Don't depend on the reg property as a way to determine the base of the immr space. The reg property might be defined differently for different SoC families. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Add IPIC Kconfig optionJohn Rigby2008-01-231-1/+1
| | | | | | | IPIC is not just for 83xx anymore so make it a separate config option. Signed-off-by: John Rigby <jrigby@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Add support for mpc512x interrupts to ipicJohn Rigby2008-01-231-0/+62
| | | | | | | | Added ipic_info entries for vectors used by 512x that were previously unused by 83xx. Signed-off-by: John Rigby <jrigby@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] QE: Add support for Freescale QUICCEngine UARTTimur Tabi2008-01-232-2/+10
| | | | | | | | | | Add support for UART serial ports using a Freescale QUICCEngine. Update booting-without-of.txt to define new properties for a QE UART node. Update the MPC8323E-MDS device tree to add UCC5 as a UART. Update the QE library to support slow UCC devices and modules. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] QE: Add ability to upload QE firmwareTimur Tabi2008-01-231-0/+247
| | | | | | | | | | | Define the layout of a binary blob that contains a QE firmware and instructions on how to upload it. Add function qe_upload_firmware() to parse the blob and perform the actual upload. Fully define 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. Added description of a new QE firmware node to booting-without-of.txt. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] fsl_soc: add support to gianfar for fixed-link propertyVitaly Bordug2008-01-231-17/+62
| | | | | | | | | fixed-link says: register new "Fixed/emulated PHY", i.e. PHY that not connected to the real MDIO bus. Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] 83xx: USB device tree cleanupsLi Yang2008-01-231-7/+5
| | | | | | | Remove device_type = "usb" for 83xx SoC USB controller Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Fixup use of phys_addr_t in mpic codeBecky Bruce2008-01-231-2/+2
| | | | | | | | The mpic_map() and __mpic_map_mmio() need to use phys_addr_t for the physical address they are passed. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] FSL: Rework PCI/PCIe support for 85xx/86xxKumar Gala2008-01-231-88/+62
| | | | | | | | | | | The current PCI code for Freescale 85xx/86xx was treating the virtual P2P PCIe bridge as a transparent bridge. Rather than doing that fixup the virtual P2P bridge by copying the resources from the PHB. Also, fixup a bit of the code for dealing with resource_size_t being 64-bits and how we set ATMU registers for >4G. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Use for_each macros in arch/powerpc/sysdevCyrill Gorcunov2008-01-176-38/+25
| | | | | Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* Merge branch 'virtex-for-2.6.25' of ↵Josh Boyer2008-01-111-1/+7
|\ | | | | | | git://git.secretlab.ca/git/linux-2.6-virtex into for-2.6.25
| * [POWERPC] Xilinx: update compatible list for interrupt controllerStephen Neuendorffer2008-01-091-1/+7
| | | | | | | | | | | | | | These values now match what is generated by the uboot BSP generator. Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* | [POWERPC] 4xx: PCIe: Increase max busses per port to 64Stefan Roese2008-01-081-1/+1
|/ | | | | | | | | | | Because of how big mapping the config space is (1M per bus), we limit how many busses we support for now. In the long run, we could replace that with something akin to kmap_atomic instead. This patch changes the limit from currently 16 to 64. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* Merge branch 'for-2.6.25' of ↵Paul Mackerras2007-12-312-6/+28
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/olof/pasemi
| * [POWERPC] pasemi: Distribute interrupts evenly across cpusOlof Johansson2007-12-281-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default the OpenPIC on PWRficient will bias to one core (since that will improve changes of the other core being able to stay idle/powered down). However, this conflicts with most irq load balancing schemes, since setting an interrupt to be delivered to either core doesn't really result in the load being shared. It also doesn't work well with the soft irq disable feature of PPC, since EE will stay on until the first interrupt is taken while soft disabled. Set the gconf0 config bit that enables even distribution of interrupts among the two cores. Signed-off-by: Olof Johansson <olof@lixom.net>
| * [POWERPC] pasemi: Implement NMI supportOlof Johansson2007-12-282-6/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some PWRficient-based boards have a NMI button that's wired up to a GPIO as interrupt source. By configuring the openpic accordingly, these get delivered as a machine check with high priority, instead of as an external interrupt. The device tree contains a property "nmi-source" in the openpic node for these systems, and it's the (hwirq) source for the input. Also, for these interrupts, the IACK is read from another register than the regular (MCACK instead), but they are EOI'd as usual. So implement said function for the mpic driver. Finally, move a couple of external function defines to include/ instead of local under sysdev. Being able to mask/unmask and eoi directly saves us from setting up a dummy irq handler that will never be called. Signed-off-by: Olof Johansson <olof@lixom.net>
* | [POWERPC] 4xx: Set ibpre for 405EX in 4xx PCIe driverStefan Roese2007-12-231-0/+2
| | | | | | | | | | | | | | | | This patch sets the ibpre flag (Inbound Presence) for the 405EX in the 4xx PCIe driver. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | [POWERPC] 4xx: rework UIC cascade irq handlingValentine Barshak2007-12-231-17/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a UIC cascade handler rework to use set_irq_chained_handler() for cascade, just like othe ppc platforms do. With current implementation we have additional redirection for irq handler and we call generic_handle_irq twice (once for the primary uic and the other time for handling cascade interrupt). This causes Ingo's realtime support patch to stop working on 4xx. Not sure of any other possible problems though, but with set_irq_chained_handler() we can abolish "struct irqaction cascade" from the chip descriptor and call generic_handle_irq() once, directly for cascade irq. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | [POWERPC] 4xx: make UIC use generic level irq handlerValentine Barshak2007-12-231-62/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes PowerPC 4xx UIC use generic level irq handler instead of a custom handle_uic_irq() function. We ack only edge irqs in mask_ack callback, since acking a level irq on UIC has no effect if the interrupt is still asserted by the device, even if the interrupt is already masked. So, to really de-assert the interrupt we need to de-assert the external source first *and* ack it on UIC then. The handle_level_irq() function masks and ack's the interrupt with mask_ack callback prior to calling the actual ISR and unmasks it at the end. So, to use it with UIC interrupts we need to ack level irqs in the unmask callback instead, after the ISR has de-asserted the external interrupt source. Even if we ack the interrupt that we didn't handle (unmask/ack it at the end of the handler, while next irq is already pending) it will not de-assert the irq, untill we de-assert its exteral source. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | [POWERPC] 4xx: Add 440SPe revA runtime detection to PCIeStefan Roese2007-12-231-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds runtime detection of the 440SPe revision A chips. These chips are equipped with a slighly different PCIe core and need special/ different initialization. The compatible node is changed to "plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that can be equipped with both PPC revisions like the AMCC Yucca. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | [POWERPC] 4xx: PCI-E Link setup improvementsBenjamin Herrenschmidt2007-12-232-89/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This improves the way the 4xx PCI-E code handles checking for a link and adds explicit testing of CRS result codes on config space accesses. This should make it more reliable. Also, bridges with no link are now still created, though config space accesses beyond the root complex are filtered. This is one step toward eventually supporting hotplug. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | [POWERPC] 4xx: PLB to PCI Express supportBenjamin Herrenschmidt2007-12-233-18/+1226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds to the previous 2 patches the support for the 4xx PCI Express cells as found in the 440SPe revA, revB and 405EX. Unfortunately, due to significant differences between these, and other interesting "features" of those pieces of HW, the code isn't as simple as it is for PCI and PCI-X and some of the functions differ significantly between the 3 implementations. Thus, not only this code can only support those 3 implementations for now and will refuse to operate on any other, but there are added ifdef's to avoid the bloat of building a fairly large amount of code on platforms that don't need it. Also, this code currently only supports fully initializing root complex nodes, not endpoint. Some more code will have to be lifted from the arch/ppc implementation to add the endpoint support, though it's mostly differences in memory mapping, and the question on how to represent endpoint mode PCI in the device-tree is thus open. Many thanks to Stefan Roese for testing & fixing up the 405EX bits ! Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | [POWERPC] 4xx: PLB to PCI 2.x supportBenjamin Herrenschmidt2007-12-232-1/+198
| | | | | | | | | | | | | | | | This adds to the previous patch the support for the 4xx PCI 2.x bridges. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | [POWERPC] 4xx: PLB to PCI-X supportBenjamin Herrenschmidt2007-12-233-0/+448
|/ | | | | | | | | | | This adds base support code for the 4xx PCI-X bridge. It also provides placeholders for the PCI and PCI-E version but they aren't supported with this patch. The bridges are configured based on device-tree properties. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* Merge branch 'linux-2.6'Paul Mackerras2007-12-211-2/+1
|\
| * [POWRPC] CPM2: Eliminate section mismatch warning in cpm2_reset().Scott Wood2007-12-131-2/+1
| | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] pci32: Add flags modifying the PCI code behaviourBenjamin Herrenschmidt2007-12-202-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds to the 32 bits PCI code some flags, replacing the old pci_assign_all_busses global, that allow us to control various aspects of the PCI probing, such as whether to re-assign all resources or not, or to not try to assign anything at all. This also adds the flag x86 already has to avoid ISA alignment on bridges that don't have ISA forwarding enabled (no legacy devices on the top level bus) and sets it for PowerMacs. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] arch/powerpc/: Spelling fixesjoe@perches.com2007-12-202-2/+2
| | | | | | | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] pasemi: Implement MSI supportOlof Johansson2007-12-204-1/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement MSI support for PA Semi PWRficient platforms. MSI is done through a special range of sources on the openpic controller, and they're unfortunately breaking the usual concepts of how sources are programmed: * The source is calculated as 512 + the value written into the MSI register * The vector for this source is added to the source and reported through IACK This means that for simplicity, it makes much more sense to just set the vector to 0 for the source, since that's really the vector we expect to see from IACK. Also, the affinity/priority registers will affect 16 sources at a time. To avoid most (simple) users from being limited by this, allocate 16 sources per device but use only one. This means that there's a total of 32 sources. If we get usage scenarions that need more sources, the allocator should probably be revised to take an alignment argument and size, not just do natural alignment. Finally, since I'm already touching the MPIC names on pasemi, rename the base one from the somewhat odd " PAS-OPIC " to "PASEMI-OPIC". Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] MPIC: Minor optimization of ipi handlerOlof Johansson2007-12-201-8/+7
| | | | | | | | | | | | | | | | | | | | Optimize MPIC IPIs, by passing in the IPI number as the argument to the handler, since all we did was translate it back based on which mpic the interrupt came though on (and that was always the primary mpic). Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] qe: add function qe_clock_source()Timur Tabi2007-12-131-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | Add function qe_clock_source() which takes a string containing the name of a QE clock source (as is typically found in device trees) and returns the matching enum qe_clock value. Update booting-without-of.txt to indicate that the UCC properties rx-clock and tx-clock are deprecated and replaced with rx-clock-name and tx-clock-name, which use strings instead of numbers to indicate QE clock sources. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] Move CPM command handling into the cpm driversJochen Friedrich2007-12-132-0/+53
| | | | | | | | | | | | | | | | | | | | | | This patch moves the CPM command handling into commproc.c for CPM1 and cpm2_common.c. This is yet another preparation to get rid of drivers accessing the CPM via the global cpmp. Signed-off-by: Jochen Friedrich <jochen@scram.de> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org>
* | [POWERPC] Add support for PORTA and PORTB odr registersJochen Friedrich2007-12-131-3/+16
| | | | | | | | | | | | | | | | | | PORTA and PORTB have odr registers, as well. However, the PORTB odr register is only 16bit. Signed-off-by: Jochen Friedrich <jochen@scram.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Vitaly Bordug <vitb@kernel.crashing.org>
* | [POWERPC] ipic: ack only for edge interruptsLi Yang2007-12-122-74/+45
| | | | | | | | | | | | | | | | | | | | Only external interrupts in edge detect mode support ack operation. Therefore, in most cases ack is not needed. The patch makes ipic ack only when it's needed. This could boost over all system performance. Signed-off-by: Li Yang <leoli@freescale.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] FSL: enet device tree cleanupsKumar Gala2007-12-121-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * Removed address fields in ethernet nodes * Removed #address-cells, #size-cells from gianfar nodes * Added cell-index to gianfar and ucc ethernet nodes * Added enet[0..3] labels * Renamed compatible node for gianfar mdio to "fsl,gianfar-mdio" * Removed device_type = "mdio" The matching for gianfar mdio still supports the old "mdio"/"gianfar" combo but it is now considered deprecated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] FSL: I2C device tree cleanupsKumar Gala2007-12-111-5/+3
| | | | | | | | | | | | | | | | * Removed device_type = "i2c" * Added missing second I2C controller on MPC8548 CDS, MPC8544 DS * Added #address-cells, #size-cells, and cell-index where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] QE: change qe_setbrg() to take an enum qe_clock instead of an integerTimur Tabi2007-12-111-5/+9
| | | | | | | | | | | | | | | | | | qe_setbrg() currently takes an integer to indicate the BRG number. Change that to take an enum qe_clock instead, since this enum is intended to represent clock sources. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] ipic: add new interrupts introduced by new chipLi Yang2007-12-112-9/+136
| | | | | | | | | | | | | | | | These interrupts are introduced by the latest Freescale SoC such as MPC837x. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | [POWERPC] Clean out asm/of_{platform, device}.h from sysdev/Jon Loeliger2007-12-062-4/+5
| | | | | | | | | | | | | | | | Convert #include of asm/of_{platform, device}.h into linux/of_{platform,device}.h for remaining arch/powerpc files. Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* | [POWERPC] Add missing spaces in printk formatsjoe@perches.com2007-12-031-1/+1
|/ | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
* Merge branch 'for-2.6.24' of ↵Paul Mackerras2007-11-201-1/+17
|\ | | | | | | master.kernel.org:/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx into merge
| * [POWERPC] 4xx: UIC add mask_ack callbackValentine Barshak2007-11-191-1/+17
| | | | | | | | | | | | | | | | | | | | This adds uic_mask_ack_irq() callback to PowerPC 4xx uic code to avoid kernel crash. It is used for edge-triggered interrupts by handle_uic_irq(). Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | [POWERPC] cpm: Fix a couple minor issues in cpm_common.c.Scott Wood2007-11-091-3/+1
|/ | | | | | | | A debugging printk is removed, and a comment is fixed to match the code. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* [POWERPC] Fix mv643xx_pci sysfs .read and .write functionsDale Farnsworth2007-11-081-4/+6
| | | | | | | | | | | | | Commit 91a69029 introduced an additional parameter to the .read and .write methods for sysfs binary attributes. Two mv64x60_pci functions were missed in that patch, resulting in these errors: /cache/git/linux-2.6/arch/powerpc/sysdev/mv64x60_pci.c:77: warning: initialization from incompatible pointer type /cache/git/linux-2.6/arch/powerpc/sysdev/mv64x60_pci.c:78: warning: initialization from incompatible pointer type Add the missing "struct bin_attribute *" parameter. Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] i8259: Add disable methodAurelien Jarno2007-11-081-0/+1
| | | | | | | | | | | | Since commit 76d2160147f43f982dfe881404cfde9fd0a9da21, the NE2000 card is not working anymore on PPC and POWERPC and produces WATCHDOG timeouts. The patch below fixes that the same way it has been done on x86, x86_64 and MIPS. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
* [POWERPC] bestcomm: Restrict bus prefetch bugfix to original mpc5200 silicon.Grant Likely2007-10-211-3/+6
| | | | | | Only the MPC5200 needs this bug fix. MPC5200B is okay. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* Merge branch 'for-2.6.24' of git://git.secretlab.ca/git/linux-2.6-mpc52xx ↵Paul Mackerras2007-10-1719-0/+2535
|\ | | | | | | into merge
| * [POWERPC] bestcomm: GenBD task supportSylvain Munaut2007-10-166-0/+449
| | | | | | | | | | | | | | | | | | | | | | | | | | This is the microcode for the GenBD task and the associated support code. This is a generic task that copy data to/from a hardware FIFO. This is currently locked to 32bits wide access but could be extended as needed. The microcode itself comes directly from the offical API (v2.2) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * [POWERPC] bestcomm: FEC task supportSylvain Munaut2007-10-166-0/+509
| | | | | | | | | | | | | | | | | | | | | | This is the microcode for the FEC task and the associated support code. The microcode itself comes directly from the offical API (v2.2) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * [POWERPC] bestcomm: ATA task supportSylvain Munaut2007-10-165-0/+267
| | | | | | | | | | | | | | | | | | | | | | This is the microcode for the ATA task and the associated support code. The microcode itself comes directly from the offical API (v2.2) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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