Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub... | Linus Torvalds | 2017-11-15 | 1 | -14/+0 |
* | RISC-V: Build Infrastructure | Palmer Dabbelt | 2017-09-26 | 1 | -0/+61 |
* | RISC-V: User-facing API | Palmer Dabbelt | 2017-09-26 | 15 | -0/+710 |
* | RISC-V: Paging and MMU | Palmer Dabbelt | 2017-09-26 | 7 | -0/+910 |
* | RISC-V: Device, timer, IRQs, and the SBI | Palmer Dabbelt | 2017-09-26 | 7 | -0/+364 |
* | RISC-V: Task implementation | Palmer Dabbelt | 2017-09-26 | 6 | -0/+328 |
* | RISC-V: ELF and module implementation | Palmer Dabbelt | 2017-09-26 | 3 | -0/+150 |
* | RISC-V: Generic library routines and assembly | Palmer Dabbelt | 2017-09-26 | 6 | -0/+822 |
* | RISC-V: Atomic and Locking Code | Palmer Dabbelt | 2017-09-26 | 10 | -0/+1423 |
* | RISC-V: Init and Halt Code | Palmer Dabbelt | 2017-09-26 | 3 | -0/+162 |