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* get rid of legacy 'get_ds()' functionLinus Torvalds2019-03-041-1/+0
* riscv: Add pte bit to distinguish swap from invalidStefan O'Rear2019-02-112-4/+10
* riscv: Adjust mmap base address at a third of task sizeAlexandre Ghiti2019-01-251-1/+1
* RISC-V: asm/page.h: fix spelling mistake "CONFIG_64BITS" -> "CONFIG_64BIT"Antony Pavlov2019-01-231-1/+1
* Fix a handful of audit-related issuePalmer Dabbelt2019-01-074-0/+23
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| * riscv: define NR_syscalls in unistd.hDavid Abdurachmanov2019-01-071-0/+2
| * riscv: add audit supportDavid Abdurachmanov2019-01-073-0/+21
* | RISC-V: Support MODULE_SECTIONS mechanism on RV32Zong Li2019-01-071-13/+15
* | arch: remove redundant UAPI generic-y definesMasahiro Yamada2019-01-061-27/+0
* | arch: remove stale comments "UAPI Header export list"Masahiro Yamada2019-01-061-1/+0
* | riscv: remove redundant kernel-space generic-yMasahiro Yamada2019-01-061-25/+0
* | Merge branch 'akpm' (patches from Andrew)Linus Torvalds2019-01-051-4/+2
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| * | mm: treewide: remove unused address argument from pte_alloc functionsJoel Fernandes (Google)2019-01-041-4/+2
* | | Remove 'type' argument from access_ok() functionLinus Torvalds2019-01-032-11/+5
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* | Merge tag 'dma-mapping-4.21' of git://git.infradead.org/users/hch/dma-mappingLinus Torvalds2018-12-281-15/+0
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| * | dma-direct: merge swiotlb_dma_ops into the dma_direct codeChristoph Hellwig2018-12-131-15/+0
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* / riscv, atomic: Add #define's for the atomic_{cmp,}xchg_*() variantsAndrea Parri2018-12-211-0/+9
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* riscv: add asm/unistd.h UAPI headerDavid Abdurachmanov2018-11-202-10/+21
* riscv: fix warning in arch/riscv/include/asm/module.hDavid Abdurachmanov2018-11-201-0/+1
* RISC-V: Fix raw_copy_{to,from}_user()Olof Johansson2018-11-201-2/+2
* riscv: fix spacing in struct pt_regsDavid Abdurachmanov2018-11-121-2/+2
* Merge tag 'riscv-for-linus-4.20-mw2' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-311-3/+0
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| * Move EM_RISCV into elf-em.hPalmer Dabbelt2018-10-311-3/+0
* | treewide: remove current_text_addrNick Desaulniers2018-10-311-6/+0
* | Merge tag 'riscv-for-linus-4.20-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-257-17/+192
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| * RISC-V: SMP cleanup and new featuresPalmer Dabbelt2018-10-223-15/+50
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| | * RISC-V: Show IPI statsAnup Patel2018-10-221-0/+9
| | * RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-221-3/+13
| | * RISC-V: Add logical CPU indexing for RISC-VAtish Patra2018-10-221-1/+23
| | * RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-221-1/+1
| | * RISC-V: Provide a cleaner raw_smp_processor_id()Palmer Dabbelt2018-10-221-10/+4
| * | riscv: Add support to no-FPU systemsPalmer Dabbelt2018-10-221-1/+11
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| | * | Auto-detect whether a FPU existsAlan Kao2018-10-221-4/+4
| | * | Allow to disable FPU supportAlan Kao2018-10-221-0/+10
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| * | RISC-V: Add futex support.Jim Wilson2018-10-222-1/+128
| * | RISC-V: Add FP register ptrace support for gdb.Jim Wilson2018-10-221-0/+3
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* | Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-10-251-0/+1
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| * | RISC-V: Request newstat syscallsGuenter Roeck2018-09-051-0/+1
* | | Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds2018-10-242-24/+1
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| * | signal: Remove the need for __ARCH_SI_PREABLE_SIZE and SI_PAD_SIZEEric W. Biederman2018-10-032-24/+1
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* | RISC-V: include linux/ftrace.h in asm-prototypes.hJames Cowgill2018-09-241-0/+7
* | riscv: tlb: Provide definition of tlb_flush() before including tlb.hWill Deacon2018-08-281-0/+4
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* RISC-V: Fix sys_riscv_flush_icachePalmer Dabbelt2018-08-203-7/+13
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| * RISC-V: Don't use a global include guard for uapi/asm/syscalls.hPalmer Dabbelt2018-08-202-5/+13
| * RISC-V: Define sys_riscv_flush_icache when SMP=nPalmer Dabbelt2018-08-201-2/+0
* | riscv: Delete asm/compat.hDeepa Dinamani2018-08-202-29/+1
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* Merge tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds2018-08-194-10/+3
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| * RISC-V: Fix !CONFIG_SMP compilation errorAtish Patra2018-08-131-0/+1
| * clocksource: new RISC-V SBI timer driverPalmer Dabbelt2018-08-131-3/+0
| * RISC-V: add a definition for the SIE SEIE bitChristoph Hellwig2018-08-131-0/+1
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