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* RISC-V: Add FP register ptrace support for gdb.Jim Wilson2018-10-221-0/+52
| | | | | | | | | | Add a variable and a macro to describe FP registers, assuming only D is supported. FP code is conditional on CONFIG_FPU. The FP regs and FCSR are copied separately to avoid copying struct padding. Tested by hand and with the gdb testsuite. Signed-off-by: Jim Wilson <jimw@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: Fix PTRACE_SETREGSET bug.Jim Wilson2018-07-041-1/+1
| | | | | | | | In riscv_gpr_set, pass regs instead of &regs to user_regset_copyin to fix gdb segfault. Signed-off-by: Jim Wilson <jimw@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* RISC-V: User-facing APIPalmer Dabbelt2017-09-261-0/+125
This patch contains code that is in some way visible to the user: including via system calls, the VDSO, module loading and signal handling. It also contains some generic code that is ABI visible. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>