summaryrefslogtreecommitdiffstats
path: root/arch/riscv
Commit message (Expand)AuthorAgeFilesLines
* riscv: Use -mno-relax when using lld linkerKhem Raj2021-06-181-0/+9
* riscv: Workaround mcount name prior to clang-13Nathan Chancellor2021-05-222-7/+17
* RISC-V: Fix error code returned by riscv_hartid_to_cpuid()Anup Patel2021-05-191-1/+1
* riscv: Fix spelling mistake "SPARSEMEM" to "SPARSMEM"Kefeng Wang2021-04-211-1/+1
* riscv,entry: fix misaligned base for excp_vect_tableZihao Yu2021-04-161-0/+1
* riscv: Correct SPARSEMEM configurationKefeng Wang2021-03-241-2/+2
* riscv: virt_addr_valid must check the address belongs to linear mappingAlexandre Ghiti2021-02-171-1/+4
* riscv: defconfig: enable gpio support for HiFive UnleashedSagar Shrikant Kadam2021-01-271-0/+2
* dts: phy: fix missing mdio device and probe failure of vsc8541-01 deviceSagar Shrikant Kadam2021-01-271-0/+1
* riscv: Fix kernel time_init()Damien Le Moal2021-01-271-0/+3
* arch: pgtable: define MAX_POSSIBLE_PHYSMEM_BITS where neededArnd Bergmann2020-12-021-0/+2
* riscv: Set text_offset correctly for M-ModeSean Anderson2020-11-181-0/+5
* riscv: Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFOZong Li2020-11-051-0/+3
* RISC-V: Take text_mutex in ftrace_init_nop()Palmer Dabbelt2020-10-012-0/+26
* riscv: Add sfence.vma after early page table changesGreentime Hu2020-09-231-4/+3
* RISC-V: Set maximum number of mapped pages correctlyAtish Patra2020-08-051-1/+1
* RISC-V: Upgrade smp_mb__after_spinlock() to iorw,iorwPalmer Dabbelt2020-07-291-1/+9
* riscv: use 16KB kernel stack on 64-bitAndreas Schwab2020-07-221-0/+4
* RISC-V: Don't allow write+exec only page mapping request in mmapYash Shah2020-06-301-0/+6
* riscv/atomic: Fix sign extension for RV64INathan Huckleberry2020-06-301-4/+4
* riscv: stacktrace: Fix undefined reference to `walk_stackframe'Kefeng Wang2020-06-031-1/+1
* riscv: fix vdso build with lldIlie Halip2020-05-201-3/+3
* riscv: set max_pfn to the PFN of the last pageVincent Chen2020-05-141-1/+2
* riscv: Fix range looking for kernel image memblockAlexandre Ghiti2020-03-251-1/+1
* riscv: Force flat memory model with no-mmuDamien Le Moal2020-03-251-0/+1
* riscv: avoid the PIC offset of static percpu data in module beyond 2G limitsVincent Chen2020-03-251-0/+16
* riscv, bpf: Fix broken BPF tail callsBjörn Töpel2020-02-111-2/+11
* riscv: delete temporary filesIlie Halip2020-02-051-1/+2
* riscv: export flush_icache_all to modulesOlof Johansson2020-01-171-0/+1
* riscv: Implement copy_thread_tlsAmanieu d'Antras2020-01-142-3/+4
* bpf, riscv: Limit to 33 tail callsPaul Chaignon2020-01-121-2/+2
* riscv: ftrace: correct the condition logic in function graph tracerZong Li2020-01-091-1/+1
* RISC-V: Add PCIe I/O BAR memory mappingYash Shah2019-10-282-1/+13
* riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley2019-10-285-8/+8
* riscv: fp: add missing __user pointer annotationsPaul Walmsley2019-10-281-2/+2
* riscv: add missing header file includesPaul Walmsley2019-10-2813-0/+17
* riscv: mark some code and data as file-staticPaul Walmsley2019-10-282-2/+2
* riscv: init: merge split string literals in preprocessor directivePaul Walmsley2019-10-281-2/+1
* riscv: add prototypes for assembly language functions from head.SPaul Walmsley2019-10-285-0/+29
* riscv: cleanup do_trap_breakChristoph Hellwig2019-10-251-20/+6
* riscv: cleanup <asm/bug.h>Christoph Hellwig2019-10-231-13/+3
* riscv: Fix undefined reference to vmemmap_populate_basepagesKefeng Wang2019-10-231-1/+1
* riscv: Fix implicit declaration of 'page_to_section'Kefeng Wang2019-10-231-4/+1
* riscv: fix fs/proc/kcore.c compilation with sparsemem enabledDavid Abdurachmanov2019-10-231-2/+0
* RISC-V: fix virtual address overlapped in FIXADDR_START and VMEMMAP_STARTGreentime Hu2019-10-151-8/+8
* riscv: tlbflush: remove confusing comment on local_flush_tlb_all()Paul Walmsley2019-10-141-4/+0
* riscv: dts: HiFive Unleashed: add default chosen/stdout-pathPaul Walmsley2019-10-141-0/+1
* riscv: remove the switch statement in do_trap_break()Vincent Chen2019-10-141-11/+11
* RISC-V: entry: Remove unneeded need_resched() loopValentin Schneider2019-10-091-2/+1
* riscv: Correct the handling of unexpected ebreak in do_trap_break()Vincent Chen2019-10-071-3/+3
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:45:20 +0000