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| * RISC-V: Add a non-void return for sbi v02 functionsAtish Patra2021-02-222-21/+21
| * RISC-V: Implement ASID allocatorAnup Patel2021-02-184-4/+279
| * RISC-V: remove unneeded semicolonChengyang Fan2021-02-181-1/+1
| * RISC-V: probes: Treat the instruction stream as host-endianPalmer Dabbelt2021-02-182-2/+2
| * pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driverDamien Le Moal2021-02-181-0/+1
| * arch/riscv:fix typo in a comment in arch/riscv/kernel/image-vars.htangchunyou2021-02-181-1/+1
| * riscv/kasan: add KASAN_VMALLOC supportNylon Chen2021-02-182-1/+57
| * riscv: Covert to reserve_initrd_mem()Kefeng Wang2021-02-181-53/+1
| * riscv: add BUILTIN_DTB support for MMU-enabled targetsVitaly Wool2021-02-183-7/+17
| * riscv/stacktrace: Fix stack output without ra on the stack topChen Huang2021-01-141-3/+9
| * riscv: Improve __show_regsKefeng Wang2021-01-141-1/+6
| * riscv: Add dump stack in show_regsKefeng Wang2021-01-145-4/+21
| * riscv: Enable per-task stack canariesGuo Ren2021-01-145-2/+23
| * riscv: Add support for function error injectionGuo Ren2021-01-144-0/+19
| * riscv: Add uprobes supportedGuo Ren2021-01-149-1/+253
| * riscv: Add KPROBES_ON_FTRACE supportedGuo Ren2021-01-143-0/+55
| * riscv: Add kprobes supportedGuo Ren2021-01-1413-0/+773
| * riscv: Using PATCHABLE_FUNCTION_ENTRY instead of MCOUNTGuo Ren2021-01-143-235/+204
| * riscv: Fixup patch_text panic in ftraceGuo Ren2021-01-142-0/+2
| * riscv: Fixup wrong ftrace remove cflagGuo Ren2021-01-142-3/+3
| * riscv: Fixup compile error BUILD_BUG_ON failedGuo Ren2021-01-141-2/+6
| * RISC-V: Implement ptrace regs and stack APIPatrick Stählin2021-01-143-0/+129
| * riscv: Add machine name to kernel boot log and stack dump outputKefeng Wang2021-01-141-1/+8
| * riscv: Add numa support for riscv64 platformAtish Patra2021-01-147-5/+87
| * riscv: Add support pte_protnone and pmd_protnone if CONFIG_NUMA_BALANCINGGreentime Hu2021-01-141-0/+20
| * riscv: Separate memory init from paging initAtish Patra2021-01-143-1/+7
| * riscv: Add Canaan Kendryte K210 reset controllerDamien Le Moal2021-01-141-0/+1
| * riscv: Fix Canaan Kendryte K210 device treeDamien Le Moal2021-01-141-5/+0
| * riscv: Use vendor name for K210 SoC supportDamien Le Moal2021-01-148-20/+20
| * riscv: Fix builtin DTB handlingDamien Le Moal2021-01-076-78/+19
| * riscv: dts: add initial board data for the SiFive HiFive UnmatchedYash Shah2021-01-072-1/+255
| * riscv: dts: add initial support for the SiFive FU740-C000 SoCYash Shah2021-01-071-0/+293
| * riscv/mm: Prevent kernel module to access user memory without uaccess routinesEric Lin2021-01-071-0/+5
| * riscv/mm: Introduce a die_kernel_fault() helper functionEric Lin2021-01-071-6/+17
| * riscv: Cleanup sbi function stubs when RISCV_SBI disabledKefeng Wang2021-01-073-12/+5
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextLinus Torvalds2021-02-202-8/+28
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| * \ Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netDavid S. Miller2021-02-104-5/+12
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| * \ \ Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski2021-02-021-1/+1
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| * \ \ \ Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski2021-01-2013-35/+67
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| * | | | | bpf: Rename BPF_XADD and prepare to encode other atomics in .immBrendan Jackman2021-01-142-8/+28
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* | | | | Revert "dts: phy: add GPIO number and active state used for phy reset"Palmer Dabbelt2021-02-101-1/+0
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* | | | RISC-V: Define MAXPHYSMEM_1GB only for RV32Atish Patra2021-02-021-0/+2
* | | | riscv: Align on L1_CACHE_BYTES when STRICT_KERNEL_RWXSebastien Van Cauwenberghe2021-02-021-3/+3
* | | | RISC-V: Fix .init section permission updateAtish Patra2021-02-021-1/+3
* | | | riscv: virt_addr_valid must check the address belongs to linear mappingAlexandre Ghiti2021-02-021-1/+4
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* | | riscv: Fixup pfn_valid error with wrong max_mapnrGuo Ren2021-01-221-1/+1
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* | RISC-V: Fix maximum allowed phsyical memory for RV32Atish Patra2021-01-151-2/+4
* | RISC-V: Set current memblock limitAtish Patra2021-01-151-2/+14
* | RISC-V: Do not allocate memblock while iterating reserved memblocksAtish Patra2021-01-151-11/+13
* | riscv: stacktrace: Move register keyword to beginning of declarationKefeng Wang2021-01-141-3/+2
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