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| | * | | riscv: vdso.lds.S: drop __alt_start and __alt_end symbolsJisheng Zhang2023-11-051-2/+0
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| * | | riscv: add userland instruction dump to RISC-V splatsYunhui Cui2023-11-051-3/+18
| * | | riscv: kprobes: allow writing to x0Nam Cao2023-11-051-1/+1
| * | | riscv: provide riscv-specific is_trap_insn()Nam Cao2023-11-051-0/+6
| * | | Merge patch series "Improve PTDUMP and introduce new fields"Palmer Dabbelt2023-11-052-21/+36
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| | * | | riscv: Introduce NAPOT field to PTDUMPYu Chien Peter Lin2023-11-051-0/+4
| | * | | riscv: Introduce PBMT field to PTDUMPYu Chien Peter Lin2023-11-051-0/+16
| | * | | riscv: Improve PTDUMP to show RSW with non-zero valueYu Chien Peter Lin2023-11-052-22/+17
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| * | | RISC-V: capitalise CMO op macrosConor Dooley2023-11-055-29/+29
| * | | riscv: don't probe unaligned access speed if already doneJisheng Zhang2023-11-051-0/+4
| * | | riscv: defconfig : add CONFIG_MMC_DW for starfiveJinyu Tang2023-11-051-0/+2
| * | | riscv: signal: handle syscall restart before get_signalHaorong Lu2023-11-051-39/+46
| * | | Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt2023-11-0511-59/+524
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| | * | | riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGNClément Léger2023-11-013-0/+33
| | * | | riscv: report misaligned accesses emulation to hwprobeClément Léger2023-11-014-1/+79
| | * | | riscv: annotate check_unaligned_access_boot_cpu() with __initClément Léger2023-11-011-1/+1
| | * | | riscv: add support for sysctl unaligned_enabled controlClément Léger2023-11-012-0/+10
| | * | | riscv: add floating point insn support to misaligned access emulationClément Léger2023-11-012-4/+269
| | * | | riscv: report perf event for misaligned faultClément Léger2023-11-011-0/+5
| | * | | riscv: add support for misaligned trap handling in S-modeClément Léger2023-11-015-23/+129
| | * | | riscv: remove unused functions in traps_misaligned.cClément Léger2023-11-011-39/+7
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* | | | Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2023-11-0836-245/+526
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| * | | RISC-V: hwprobe: Fix vDSO SIGSEGVAndrew Jones2023-11-022-1/+6
| * | | riscv: configs: defconfig: Enable configs required for RZ/Five SoCLad Prabhakar2023-11-021-0/+52
| * | | Merge patch series "riscv: SCS support"Palmer Dabbelt2023-11-0215-175/+237
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| | * | | riscv: Use separate IRQ shadow call stacksSami Tolvanen2023-10-273-0/+35
| | * | | riscv: Implement Shadow Call StackSami Tolvanen2023-10-2710-1/+99
| | * | | riscv: Move global pointer loading to a macroSami Tolvanen2023-10-274-20/+14
| | * | | riscv: Deduplicate IRQ stack switchingSami Tolvanen2023-10-276-55/+55
| | * | | riscv: VMAP_STACK overflow detection thread-safeDeepak Gupta2023-10-276-99/+34
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| * | | Merge patch "riscv: errata: improve T-Head CMO"Palmer Dabbelt2023-11-021-9/+9
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| | * | | riscv: errata: prefix T-Head mnemonics with th.Icenowy Zheng2023-11-021-7/+7
| * | | | Merge patch series "RISC-V: ACPI improvements"Palmer Dabbelt2023-10-314-8/+111
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| | * | | | RISC-V: cacheflush: Initialize CBO variables on ACPI systemsSunil V L2023-10-261-6/+19
| | * | | | RISC-V: ACPI: RHCT: Add function to get CBO block sizesSunil V L2023-10-261-0/+6
| | * | | | RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remappingSunil V L2023-10-262-2/+86
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| * | | | riscv: put interrupt entries into .irqentry.textNam Cao2023-10-311-0/+2
| * | | | riscv: mm: Update the comment of CONFIG_PAGE_OFFSETSong Shuai2023-10-311-2/+2
| * | | | riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpauseMinda Chen2023-10-311-1/+1
| * | | | riscv/mm: Fix the comment for swap pte formatXiao Wang2023-10-311-1/+1
| * | | | RISC-V: clarify the QEMU workaround in ISA parserTsukasa OI2023-10-311-3/+4
| * | | | riscv: correct pt_level name via pgtable_l5/4_enabledSong Shuai2023-10-311-0/+3
| * | | | RISC-V: Provide pgtable_l5_enabled on rv32Palmer Dabbelt2023-10-313-1/+5
| * | | | Merge patch series "RISC-V: Enable cbo.zero in usermode"Palmer Dabbelt2023-10-319-17/+69
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| | * | | | RISC-V: hwprobe: Expose Zicboz extension and its block sizeAndrew Jones2023-09-213-15/+35
| | * | | | RISC-V: Enable cbo.zero in usermodeAndrew Jones2023-09-216-0/+32
| | * | | | RISC-V: Make zicbom/zicboz errors consistentAndrew Jones2023-09-211-2/+2
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| * | | | Merge patch series "riscv: kexec: cleanup and fixups"Palmer Dabbelt2023-10-313-30/+34
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| | * | | riscv: kexec: Remove -fPIE for PURGATORY_CFLAGSSong Shuai2023-09-201-0/+4
| | * | | riscv: kexec: Align the kexeced kernel entrySong Shuai2023-09-201-1/+7
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