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path: root/arch/x86/events/intel/lbr.c
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* perf/x86: Avoid exposing wrong/stale data in intel_pmu_lbr_read_32()Peter Zijlstra2017-04-141-0/+3
* perf/x86/intel: Remove an inconsistent NULL checkDan Carpenter2016-10-161-2/+2
* perf/x86/intel: Clean up LBR state trackingPeter Zijlstra2016-08-101-28/+29
* perf/x86/intel: Remove redundant test from intel_pmu_lbr_add()Peter Zijlstra2016-08-101-2/+1
* perf/x86/intel: Eliminate dead code in intel_pmu_lbr_del()Peter Zijlstra2016-08-101-6/+0
* perf/x86: Ensure perf_sched_cb_{inc,dec}() is only called from pmu::{add,del}()Peter Zijlstra2016-08-101-2/+2
* perf/x86/intel: Fix rdlbr_to() MSR reading typoPeter Zijlstra2016-07-071-1/+1
* perf/x86/intel: Add {rd,wr}lbr_{to,from} wrappersPeter Zijlstra2016-06-271-13/+40
* perf/x86/intel: Add MSR_LAST_BRANCH_FROM_x quirk for ctx switchDavid Carrillo-Cisneros2016-06-271-3/+21
* perf/x86/intel: Fix trivial formatting and style bugDavid Carrillo-Cisneros2016-06-271-3/+3
* perf/x86/intel: Fix MSR_LAST_BRANCH_FROM_x bug when no TSXDavid Carrillo-Cisneros2016-06-271-0/+52
* perf/x86/intel: Print LBR support statement after validationDavid Carrillo-Cisneros2016-06-271-9/+0
* Merge branch 'perf/urgent' into perf/core, to resolve conflictIngo Molnar2016-04-281-2/+4
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| * perf/x86/intel: Fix incorrect lbr_sel_mask valueKan Liang2016-04-281-2/+4
* | perf/x86/intel: Add LBR filter support for Silvermont and Airmont CPUsKan Liang2016-04-231-0/+18
* | perf/x86/intel: Add Goldmont CPU supportKan Liang2016-04-231-1/+12
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* Merge branch 'x86/cleanups' into x86/urgentIngo Molnar2016-03-171-1/+1
* perf/x86: Move perf_event.h to its new homeBorislav Petkov2016-02-171-1/+1
* perf/x86: Move perf_event_intel_lbr.c ........ => x86/events/intel/lbr.cBorislav Petkov2016-02-171-0/+1062