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* x86/speculation: Split out TIF updateThomas Gleixner2018-12-051-12/+23
* x86/speculation: Prepare for conditional IBPB in switch_mm()Thomas Gleixner2018-12-051-5/+24
* x86/speculation: Prepare for per task indirect branch speculation controlTim Chen2018-12-051-0/+4
* x86/speculation: Add command line control for indirect branch speculationThomas Gleixner2018-12-051-17/+116
* x86/speculation: Unify conditional spectre v2 print functionsThomas Gleixner2018-12-051-13/+4
* x86/speculataion: Mark command line parser data __initdataThomas Gleixner2018-12-051-2/+2
* x86/speculation: Mark string arrays const correctlyThomas Gleixner2018-12-051-3/+3
* x86/speculation: Reorder the spec_v2 codeThomas Gleixner2018-12-051-84/+84
* x86/l1tf: Show actual SMT stateThomas Gleixner2018-12-051-2/+3
* x86/speculation: Rework SMT state changeThomas Gleixner2018-12-051-6/+5
* x86/speculation: Rename SSBD update functionsThomas Gleixner2018-12-051-2/+2
* x86/speculation: Disable STIBP when enhanced IBRS is in useTim Chen2018-12-051-0/+7
* x86/speculation: Move STIPB/IBPB string conditionals out of cpu_show_common()Tim Chen2018-12-051-2/+18
* x86/speculation: Remove unnecessary ret variable in cpu_show_common()Tim Chen2018-12-051-4/+1
* x86/speculation: Clean up spectre_v2_parse_cmdline()Tim Chen2018-12-051-14/+13
* x86/retpoline: Remove minimal retpoline supportZhenzhong Duan2018-12-051-11/+2
* x86/retpoline: Make CONFIG_RETPOLINE depend on compiler supportZhenzhong Duan2018-12-051-1/+1
* x86/speculation: Propagate information about RSB filling mitigation to sysfsJiri Kosina2018-12-051-1/+2
* x86/speculation: Enable cross-hyperthread spectre v2 STIBP mitigationJiri Kosina2018-12-051-6/+51
* x86/bugs: Fix the AMD SSBD usage of the SPEC_CTRL MSRTom Lendacky2018-12-051-3/+5
* x86/bugs: Update when to check for the LS_CFG SSBD mitigationTom Lendacky2018-12-051-1/+3
* x86/bugs: Switch the selection of mitigation from CPU vendor to CPU featuresKonrad Rzeszutek Wilk2018-12-051-8/+3
* x86/bugs: Add AMD's SPEC_CTRL MSR usageKonrad Rzeszutek Wilk2018-12-052-5/+13
* x86/bugs: Add AMD's variant of SSB_NOKonrad Rzeszutek Wilk2018-12-051-1/+2
* Revert "x86/speculation: Enable cross-hyperthread spectre v2 STIBP mitigation"Greg Kroah-Hartman2018-11-231-51/+6
* x86/hyper-v: Enable PIT shutdown quirkMichael Kelley2018-11-211-0/+11
* x86/cpu/vmware: Do not trace vmware_sched_clock()Steven Rostedt (VMware)2018-11-211-1/+1
* x86/speculation: Support Enhanced IBRS on future CPUsSai Praneeth2018-11-132-2/+21
* x86/speculation: Enable cross-hyperthread spectre v2 STIBP mitigationJiri Kosina2018-11-131-6/+51
* x86/microcode: Update the new microcode revision unconditionallyFilippo Sironi2018-09-192-14/+21
* x86/microcode: Make sure boot_cpu_data.microcode is up-to-datePrarit Bhargava2018-09-192-0/+8
* x86/speculation/l1tf: Increase l1tf memory limit for Nehalem+Andi Kleen2018-09-052-5/+42
* x86/spectre: Add missing family 6 check to microcode checkAndi Kleen2018-09-051-0/+3
* x86/speculation/l1tf: Suggest what to do on systems with too much RAMVlastimil Babka2018-09-051-0/+4
* x86/microcode/intel: Fix memleak in save_microcode_patch()Zhenzhong Duan2018-08-241-1/+4
* x86/l1tf: Fix build error seen if CONFIG_KVM_INTEL is disabledGuenter Roeck2018-08-171-2/+1
* x86/CPU/AMD: Have smp_num_siblings and cpu_llc_id always be presentBorislav Petkov2018-08-152-9/+8
* x86/microcode: Allow late microcode loading with SMT disabledJosh Poimboeuf2018-08-151-4/+12
* cpu/hotplug: Fix SMT supported evaluationThomas Gleixner2018-08-151-1/+1
* x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentryPaolo Bonzini2018-08-151-0/+1
* x86/speculation: Simplify sysfs report of VMX L1TF vulnerabilityPaolo Bonzini2018-08-151-3/+9
* x86/bugs, kvm: Introduce boot-time control of L1TF mitigationsJiri Kosina2018-08-151-0/+44
* cpu/hotplug: Set CPU_SMT_NOT_SUPPORTED earlyThomas Gleixner2018-08-151-0/+6
* x86/kvm: Allow runtime control of L1D flushThomas Gleixner2018-08-151-1/+1
* x86/l1tf: Handle EPT disabled state properThomas Gleixner2018-08-151-4/+5
* x86/litf: Introduce vmx status variableThomas Gleixner2018-08-151-2/+34
* x86/CPU/AMD: Move TOPOEXT reenablement before reading smp_num_siblingsBorislav Petkov2018-08-151-20/+17
* x86/cpu/AMD: Evaluate smp_num_siblings earlyThomas Gleixner2018-08-151-0/+13
* x86/CPU/AMD: Do not check CPUID max ext level before parsing SMP infoBorislav Petkov2018-08-151-5/+2
* x86/cpu/intel: Evaluate smp_num_siblings earlyThomas Gleixner2018-08-151-0/+7
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