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* arm64/mm: enable HugeTLB migration for contiguous bit HugeTLB pagesAnshuman Khandual2019-03-052-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | Let arm64 subscribe to the previously added framework in which architecture can inform whether a given huge page size is supported for migration. This just overrides the default function arch_hugetlb_migration_supported() and enables migration for all possible HugeTLB page sizes on arm64. With this, HugeTLB migration support on arm64 now covers all possible HugeTLB options. CONT PTE PMD CONT PMD PUD -------- --- -------- --- 4K: 64K 2M 32M 1G 16K: 2M 32M 1G 64K: 2M 512M 16G Link: http://lkml.kernel.org/r/1545121450-1663-6-git-send-email-anshuman.khandual@arm.com Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Naoya Horiguchi <n-horiguchi@ah.jp.nec.com> Reviewed-by: Steve Capper <steve.capper@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Michal Hocko <mhocko@kernel.org> Cc: Michal Hocko <mhocko@suse.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* arm64/mm: enable HugeTLB migrationAnshuman Khandual2019-03-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | Let arm64 subscribe to generic HugeTLB page migration framework. Right now this only works on the following PMD and PUD level HugeTLB page sizes with various kernel base page size combinations. CONT PTE PMD CONT PMD PUD -------- --- -------- --- 4K: NA 2M NA 1G 16K: NA 32M NA 64K: NA 512M NA Link: http://lkml.kernel.org/r/1545121450-1663-5-git-send-email-anshuman.khandual@arm.com Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Naoya Horiguchi <n-horiguchi@ah.jp.nec.com> Reviewed-by: Steve Capper <steve.capper@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Michal Hocko <mhocko@kernel.org> Cc: Michal Hocko <mhocko@suse.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* mm: replace all open encodings for NUMA_NO_NODEAnshuman Khandual2019-03-0516-29/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch series "Replace all open encodings for NUMA_NO_NODE", v3. All these places for replacement were found by running the following grep patterns on the entire kernel code. Please let me know if this might have missed some instances. This might also have replaced some false positives. I will appreciate suggestions, inputs and review. 1. git grep "nid == -1" 2. git grep "node == -1" 3. git grep "nid = -1" 4. git grep "node = -1" This patch (of 2): At present there are multiple places where invalid node number is encoded as -1. Even though implicitly understood it is always better to have macros in there. Replace these open encodings for an invalid node number with the global macro NUMA_NO_NODE. This helps remove NUMA related assumptions like 'invalid node' from various places redirecting them to a common definition. Link: http://lkml.kernel.org/r/1545127933-10711-2-git-send-email-anshuman.khandual@arm.com Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> [ixgbe] Acked-by: Jens Axboe <axboe@kernel.dk> [mtip32xx] Acked-by: Vinod Koul <vkoul@kernel.org> [dmaengine.c] Acked-by: Michael Ellerman <mpe@ellerman.id.au> [powerpc] Acked-by: Doug Ledford <dledford@redhat.com> [drivers/infiniband] Cc: Joseph Qi <jiangqi903@gmail.com> Cc: Hans Verkuil <hverkuil@xs4all.nl> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* sh: remove nargs from __SYSCALLFiroz Khan2019-03-052-3/+3
| | | | | | | | | | | | | | | | | | | | | | | The __SYSCALL macro's arguments are system call number, system call entry name and number of arguments for the system call. Argument- nargs in __SYSCALL(nr, entry, nargs) is neither calculated nor used anywhere. So it would be better to keep the implementation as __SYSCALL(nr, entry). This unifies the implementation with some other architectures too. Link: http://lkml.kernel.org/r/1546443445-21075-2-git-send-email-firoz.khan@linaro.org Signed-off-by: Firoz Khan <firoz.khan@linaro.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: Simon Horman <horms+renesas@verge.net.au> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Philippe Ombredanne <pombredanne@nexb.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* kasan: remove use after scope bugs detection.Andrey Ryabinin2019-03-051-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use after scope bugs detector seems to be almost entirely useless for the linux kernel. It exists over two years, but I've seen only one valid bug so far [1]. And the bug was fixed before it has been reported. There were some other use-after-scope reports, but they were false-positives due to different reasons like incompatibility with structleak plugin. This feature significantly increases stack usage, especially with GCC < 9 version, and causes a 32K stack overflow. It probably adds performance penalty too. Given all that, let's remove use-after-scope detector entirely. While preparing this patch I've noticed that we mistakenly enable use-after-scope detection for clang compiler regardless of CONFIG_KASAN_EXTRA setting. This is also fixed now. [1] http://lkml.kernel.org/r/<20171129052106.rhgbjhhis53hkgfn@wfg-t540p.sh.intel.com> Link: http://lkml.kernel.org/r/20190111185842.13978-1-aryabinin@virtuozzo.com Signed-off-by: Andrey Ryabinin <aryabinin@virtuozzo.com> Acked-by: Will Deacon <will.deacon@arm.com> [arm64] Cc: Qian Cai <cai@lca.pw> Cc: Alexander Potapenko <glider@google.com> Cc: Dmitry Vyukov <dvyukov@google.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds2019-03-05114-4335/+1607
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Paul Burton: - Support for the MIPSr6 MemoryMapID register & Global INValidate TLB (GINVT) instructions, allowing for more efficient TLB maintenance when running on a CPU such as the I6500 that supports these. - Enable huge page support for MIPS64r6. - Optimize post-DMA cache sync by removing that code entirely for kernel configurations in which we know it won't be needed. - The number of pages allocated for interrupt stacks is now calculated correctly, where before we would wastefully allocate too much memory in some configurations. - The ath79 platform migrates to devicetree. - The bcm47xx platform sees fixes for the Buffalo WHR-G54S board. - The ingenic/jz4740 platform gains support for appended devicetrees. - The cavium_octeon, lantiq, loongson32 & sgi-ip27 platforms all see cleanups as do various pieces of core architecture code. * tag 'mips_5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (66 commits) MIPS: lantiq: Remove separate GPHY Firmware loader MIPS: ingenic: Add support for appended devicetree MIPS: SGI-IP27: rework HUB interrupts MIPS: SGI-IP27: do boot CPU init later MIPS: SGI-IP27: do xtalk scanning later MIPS: SGI-IP27: use pr_info/pr_emerg and pr_cont to fix output MIPS: SGI-IP27: clean up bridge access and header files MIPS: SGI-IP27: get rid of volatile and hubreg_t MIPS: irq: Allocate accurate order pages for irq stack MIPS: dma-noncoherent: Remove bogus condition in dma_sync_phys() MIPS: eBPF: Remove REG_32BIT_ZERO_EX MIPS: eBPF: Always return sign extended 32b values MIPS: CM: Fix indentation MIPS: BCM47XX: Fix/improve Buffalo WHR-G54S support MIPS: OCTEON: program rx/tx-delay always from DT MIPS: OCTEON: delete board-specific link status MIPS: OCTEON: don't lie about interface type of CN3005 board MIPS: OCTEON: warn if deprecated link status is being used MIPS: OCTEON: add fixed-link nodes to in-kernel device tree MIPS: Delete unused flush_cache_sigtramp() ...
| * MIPS: lantiq: Remove separate GPHY Firmware loaderHauke Mehrtens2019-02-252-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The separate GPHY Firmware loader driver is not used any more, the GPHY firmware is now loaded by the GSWIP switch driver which also makes use of the GPHY. Remove the old unused GPHY firmware loader driver. The GPHY firmware is useless without an Ethernet and switch driver, it should not harm if loading this does not work for system using an old device tree. I am not aware of any vendor separating the device tree from the kernel binary, it should be ok to remove this. The code and the functionality form this separate GPHY firmware loader was added to the gswip driver in commit 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: john@phrozen.org Cc: netdev@vger.kernel.org
| * MIPS: ingenic: Add support for appended devicetreePaul Cercueil2019-02-212-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add support for booting the kernel from an externally-appended devicetree, if no devicetree was built-in. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
| * MIPS: SGI-IP27: rework HUB interruptsThomas Bogendoerfer2019-02-1911-531/+260
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit rearranges the HUB interrupt code by using MIPS_IRQ_CPU interrupt handling code and modern Linux IRQ framework features to get rid of global arrays. It also adds support for irq affinity setting. Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
| * MIPS: SGI-IP27: do boot CPU init laterThomas Bogendoerfer2019-02-194-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | To make use of per_cpu variables in interrupt code per_cpu_init() must be done after setup_per_cpu_areas(). This is achieved by calling it in smp_prepare_boot_cpu() via a new smp_ops method. Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
| * MIPS: SGI-IP27: do xtalk scanning laterThomas Bogendoerfer2019-02-192-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | Move xtalk scanning to a later boot stage to be able using things like kmalloc and friends. Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
| * MIPS: SGI-IP27: use pr_info/pr_emerg and pr_cont to fix outputThomas Bogendoerfer2019-02-192-45/+45
| | | | | | | | | | | | | | | | | | | | | | | | Topology and NMI output needs pr_cont() to look the way it was in the old days of printk. Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
| * MIPS: SGI-IP27: clean up bridge access and header filesThomas Bogendoerfer2019-02-195-192/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduced bridge_read/bridge_write/bridge_set/bridge_clr for accessing bridge register and get rid of volatile declarations. Also removed all typedefs from arch/mips/include/asm/pci/bridge.h and cleaned up language in arch/mips/pci/ops-bridge.c Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
| * MIPS: SGI-IP27: get rid of volatile and hubreg_tThomas Bogendoerfer2019-02-198-75/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | Replace hub register access with __raw_readq/__raw_writeq and get rid of hubreg_t completely. Also remove no longer (probably never used) used defines Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
| * MIPS: irq: Allocate accurate order pages for irq stackLiu Xiang2019-02-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | The irq_pages is the number of pages for irq stack, but not the order which is needed by __get_free_pages(). We can use get_order() to calculate the accurate order. Signed-off-by: Liu Xiang <liu.xiang6@zte.com.cn> Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: fe8bd18ffea5 ("MIPS: Introduce irq_stack") Cc: linux-mips@vger.kernel.org Cc: stable@vger.kernel.org # v4.11+
| * MIPS: dma-noncoherent: Remove bogus condition in dma_sync_phys()Paul Burton2019-02-191-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e36863a550da ("MIPS: HIGHMEM DMA on noncoherent MIPS32 processors") introduced code which: 1) Calculates an offset within a page, by ANDing an address with ~PAGE_MASK. 2) Checks whether that offset is >= PAGE_SIZE. This check can never evaluate true, making the code it guards unreachable. smatch spots bogus arithmetic resulting from the impossible condition, resulting in the following warning: arch/mips/mm/dma-noncoherent.c:125 dma_sync_phys() warn: mask and shift to zero Fix this by removing the impossible to satisfy condition & the unreachable code it guards. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: Christoph Hellwig <hch@lst.de> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Robin Murphy <robin.murphy@arm.com>
| * MIPS: eBPF: Remove REG_32BIT_ZERO_EXPaul Burton2019-02-191-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REG_32BIT_ZERO_EX and REG_64BIT are always handled in exactly the same way, and reg_val_propagate_range() never actually sets any register to type REG_32BIT_ZERO_EX. Remove the redundant & unused REG_32BIT_ZERO_EX. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: Alexei Starovoitov <ast@kernel.org> Cc: Daniel Borkmann <daniel@iogearbox.net> Cc: Martin KaFai Lau <kafai@fb.com> Cc: Song Liu <songliubraving@fb.com> Cc: Yonghong Song <yhs@fb.com> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Jiong Wang <jiong.wang@netronome.com>
| * MIPS: eBPF: Always return sign extended 32b valuesPaul Burton2019-02-191-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function prototype used to call JITed eBPF code (ie. the type of the struct bpf_prog bpf_func field) returns an unsigned int. The MIPS n64 ABI that MIPS64 kernels target defines that 32 bit integers should always be sign extended when passed in registers as either arguments or return values. This means that when returning any value which may not already be sign extended (ie. of type REG_64BIT or REG_32BIT_ZERO_EX) we need to perform that sign extension in order to comply with the n64 ABI. Without this we see strange looking test failures from test_bpf.ko, such as: test_bpf: #65 ALU64_MOV_X: dst = 4294967295 jited:1 ret -1 != -1 FAIL (1 times) Although the return value printed matches the expected value, this is only because printf is only examining the least significant 32 bits of the 64 bit register value we returned. The register holding the expected value is sign extended whilst the v0 register was set to a zero extended value by our JITed code, so when compared by a conditional branch instruction the values are not equal. We already handle this when the return value register is of type REG_32BIT_ZERO_EX, so simply extend this to also cover REG_64BIT. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: b6bd53f9c4e8 ("MIPS: Add missing file for eBPF JIT.") Cc: stable@vger.kernel.org # v4.13+ Cc: linux-mips@vger.kernel.org Cc: Alexei Starovoitov <ast@kernel.org> Cc: Daniel Borkmann <daniel@iogearbox.net> Cc: Martin KaFai Lau <kafai@fb.com> Cc: Song Liu <songliubraving@fb.com> Cc: Yonghong Song <yhs@fb.com> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Jiong Wang <jiong.wang@netronome.com>
| * MIPS: CM: Fix indentationPaul Burton2019-02-151-2/+2
| | | | | | | | | | | | | | | | mips_cm_error_report() contains a function call that's incorrectly indented a level further than it ought to be. Remove a tab from the start of both affected lines. Signed-off-by: Paul Burton <paul.burton@mips.com>
| * MIPS: BCM47XX: Fix/improve Buffalo WHR-G54S supportRafał Miłecki2019-02-112-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | 1) Fix reset button support which is active *high* 2) Specify LEDs colors Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org
| * MIPS: OCTEON: program rx/tx-delay always from DTAaro Koskinen2019-02-076-52/+52
| | | | | | | | | | | | | | | | Program rx/tx-delay always from DT. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: OCTEON: delete board-specific link statusAaro Koskinen2019-02-071-42/+1
| | | | | | | | | | | | | | | | | | Delete board-specific link status. This info should now come from the DT only. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: OCTEON: don't lie about interface type of CN3005 boardAaro Koskinen2019-02-071-16/+0
| | | | | | | | | | | | | | | | | | The fixed-link node in the DT should now take care of the link status, so this hack can be deleted. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: OCTEON: warn if deprecated link status is being usedAaro Koskinen2019-02-072-0/+6
| | | | | | | | | | | | | | | | Warn if deprecated link status is being used. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: OCTEON: add fixed-link nodes to in-kernel device treeAaro Koskinen2019-02-072-0/+32
| | | | | | | | | | | | | | | | | | | | | | Currently OCTEON ethernet falls back to phyless operation on boards where we have no known PHY address or a fixed-link node. Add fixed-link support for boards that need it, so we can clean up the platform code and ethernet driver from some legacy code. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: Delete unused flush_cache_sigtramp()Paul Burton2019-02-076-183/+0
| | | | | | | | | | | | | | | | | | Commit adcc81f148d7 ("MIPS: math-emu: Write-protect delay slot emulation pages") left flush_cache_sigtramp() unused. Delete the dead code. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Davidlohr Bueso <dave@stgolabs.net> Cc: linux-mips@vger.kernel.org
| * MIPS: Fix set_pte() for Netlogic XLR using cmpxchg64()Paul Burton2019-02-062-6/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 46011e6ea392 ("MIPS: Make set_pte() SMP safe.") introduced an open-coded version of cmpxchg() within set_pte(), that always operated on a value the size of an unsigned long. That is, it used ll/sc instructions when CONFIG_32BIT=y or lld/scd instructions when CONFIG_64BIT=y. This was broken for configurations in which pte_t is larger than an unsigned long (with the exception of XPA configurations which have a different implementation of set_pte()), because we no longer update the whole PTE. Indeed commit 46011e6ea392 ("MIPS: Make set_pte() SMP safe.") notes: > The case of CONFIG_64BIT_PHYS_ADDR && CONFIG_CPU_MIPS32 is *not* > handled. In practice this affects Netlogic XLR/XLS systems including nlm_xlr_defconfig. Commit 82f4f66ddf11 ("MIPS: Remove open-coded cmpxchg() in set_pte()") then replaced this open-coded version of cmpxchg() with an actual call to cmpxchg(). Unfortunately the configurations mentioned above then fail to build because cmpxchg() can only operate on values 32 bits or smaller in size, resulting in: arch/mips/include/asm/cmpxchg.h:166:11: error: call to '__cmpxchg_called_with_bad_pointer' declared with attribute error: Bad argument size for cmpxchg One option that would fix the build failure & restore the previous behaviour would be to cast the pte pointer to a pointer to unsigned long, so that cmpxchg() would operate on just 32 bits of the PTE as it has been since commit 46011e6ea392 ("MIPS: Make set_pte() SMP safe."). That feels like an ugly hack though, and the behaviour of set_pte() is likely a little broken. Instead we take advantage of the fact that the affected configurations already know at compile time that the CPU will support 64 bits (ie. have hardcoded cpu_has_64bits in cpu-feature-overrides.h) in order to allow cmpxchg64() to be used in these configurations. set_pte() then makes use of cmpxchg64() when necessary. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: 46011e6ea392 ("MIPS: Make set_pte() SMP safe.") Fixes: 82f4f66ddf11 ("MIPS: Remove open-coded cmpxchg() in set_pte()")
| * MIPS: Export mm switching functions used by KVMPaul Burton2019-02-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | KVM makes use of check_switch_mmu_context(), check_mmu_context() & get_new_mmu_context() which are no longer static inline functions in a header. As such they need to be exported for KVM to successfully build as a module, which was previously overlooked. Add the missing exports. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: 4ebea49ce233 ("MIPS: mm: Un-inline get_new_mmu_context") Fixes: 42d5b846574f ("MIPS: mm: Unify ASID version checks")
| * MIPS: Loongson32: Remove DMA & NAND devices from ls1b/board.cPaul Burton2019-02-041-28/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7b3415f581c7 ("MIPS: Loongson32: Remove unused platform devices") removed the definitions of platform devices which have no in tree drivers from common Loongson32 code, but missed their removal from Loongson 1B board code in arch/mips/loongson32/ls1b/board.c. This causes build failures due to the missing declarations of ls1x_dma_pdev, ls1x_nand_pdev & their associated *_set_platdata functions. Remove the dead code from arch/mips/loongson32/ls1b/board.c to fix the build. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: 7b3415f581c7 ("MIPS: Loongson32: Remove unused platform devices")
| * MIPS: Loongson32: Fix config brokenness; select SYS_SUPPORTS_32BIT_KERNELPaul Burton2019-02-042-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a96d68ba3b41 ("MIPS: Loongson32: clarify we don't support MIPS16 and merge configs") attempted to reduce duplication in Kconfig by consolidating some selects common to Loongson 1B & 1C CPUs under CPU_LOONGSON1. Unfortunately it clearly wasn't tested because by removing SYS_SUPPORTS_32BIT_KERNEL it prevented 32BIT from being enabled leading to all sorts of strange build errors from a kernel configured to build as neither 32 nor 64 bit. Both loongson1b_defconfig & loongson1c_defconfig failed to build due to this problem. Revert the cleanup portions of commit a96d68ba3b41 ("MIPS: Loongson32: clarify we don't support MIPS16 and merge configs"), keeping only its removal of the selection of SYS_SUPPORTS_MIPS16. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: a96d68ba3b41 ("MIPS: Loongson32: clarify we don't support MIPS16 and merge configs")
| * MIPS: Don't select ARCH_HAS_SYNC_DMA_FOR_CPU when DMA is coherentPaul Burton2019-02-041-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f263f2a2c682 ("MIPS: Compile post DMA flush only when needed") pushed the selection of ARCH_HAS_SYNC_DMA_FOR_CPU down to various SYS_HAS_CPU_* Kconfig entries corresponding to CPUs for which cpu_needs_post_dma_flush() might return true, but unfortunately missed the fact that some of these CPUs can be used in configurations with DMA_NONCOHERENT=n. When this is the case the kernel build does not include our definition of arch_sync_dma_for_cpu() from arch/mips/mm/dma-noncoherent.c and the build fails with a link error. One example of this problem is ip27_defconfig: kernel/dma/direct.o: In function `dma_direct_sync_single_for_cpu': direct.c:(.text+0x6c): undefined reference to `arch_sync_dma_for_cpu' kernel/dma/direct.o: In function `dma_direct_sync_sg_for_cpu': direct.c:(.text+0x1f0): undefined reference to `arch_sync_dma_for_cpu' kernel/dma/direct.o: In function `dma_direct_alloc': direct.c:(.text+0xc20): undefined reference to `arch_dma_alloc' kernel/dma/direct.o: In function `dma_direct_free': direct.c:(.text+0xc3c): undefined reference to `arch_dma_free' make[1]: *** [Makefile:1021: vmlinux] Error 1 make: *** [Makefile:152: sub-make] Error 2 Fix this by selecting ARCH_HAS_SYNC_DMA_FOR_CPU only when DMA_NONCOHERENT is also selected. The SYS_HAS_CPU_BMIPS5000 case is left as-is because systems with that CPU always select DMA_NONCOHERENT anyway. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: f263f2a2c682 ("MIPS: Compile post DMA flush only when needed")
| * MIPS: Enable hugepage support for MIPS64r6Paul Burton2019-02-041-0/+1
| | | | | | | | | | | | | | | | | | | | Our hugepage support already exists for MIPS64 CPUs, and is already enabled for older architecture revisions. There's nothing MIPSr6 specific involved, and our hugepage support already works fine for MIPS64r6 CPUs such as the I6500, so allow it to be selected in Kconfig. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: Remove open-coded cmpxchg() in set_pte()Paul Burton2019-02-041-43/+2
| | | | | | | | | | | | | | | | | | set_pte() contains an open coded version of cmpxchg() - it atomically replaces the buddy pte's value if it is currently zero. Simplify the code considerably by just using cmpxchg() instead of reinventing it. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: MemoryMapID (MMID) SupportPaul Burton2019-02-0415-31/+509
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce support for using MemoryMapIDs (MMIDs) as an alternative to Address Space IDs (ASIDs). The major difference between the two is that MMIDs are global - ie. an MMID uniquely identifies an address space across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs, wherein each address space is allocated a separate ASID for each CPU upon which it is used. This global namespace allows a new GINVT instruction be used to globally invalidate TLB entries associated with a particular MMID across all coherent CPUs in the system, removing the need for IPIs to invalidate entries with separate ASIDs on each CPU. The allocation scheme used here is largely borrowed from arm64 (see arch/arm64/mm/context.c). In essence we maintain a bitmap to track available MMIDs, and MMIDs in active use at the time of a rollover to a new MMID version are preserved in the new version. The allocation scheme requires efficient 64 bit atomics in order to perform reasonably, so this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it will only be included in MIPS64 kernels). The first, and currently only, available CPU with support for MMIDs is the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap our MMIDs to 16 bits wide in order to prevent the bitmap growing to absurd sizes if any future CPU does implement 32 bit MMIDs as the architecture manuals suggest is recommended. When MMIDs are in use we also make use of GINVT instruction which is available due to the global nature of MMIDs. By executing a sequence of GINVT & SYNC 0x14 instructions we can avoid the overhead of an IPI to each remote CPU in many cases. One complication is that GINVT will invalidate wired entries (in all cases apart from type 0, which targets the entire TLB). In order to avoid GINVT invalidating any wired TLB entries we set up, we make sure to create those entries using a reserved MMID (0) that we never associate with any address space. Also of note is that KVM will require further work in order to support MMIDs & GINVT, since KVM is involved in allocating IDs for guests & in configuring the MMU. That work is not part of this patch, so for now when MMIDs are in use KVM is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: Add GINVT instruction helpersPaul Burton2019-02-044-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a family of ginvt_* functions making it easy to emit a GINVT instruction to globally invalidate TLB entries. We make use of the _ASM_MACRO infrastructure to support emitting the instructions even if the assembler isn't new enough to support them natively. An associated STYPE_GINV definition & sync_ginv() function are added to emit a sync instruction of type 0x14, which operates as a completion barrier for these new GINVT (and GINVI) instructions. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Add set_cpu_context() for ASID assignmentsPaul Burton2019-02-045-13/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we gain MMID support we'll be storing MMIDs as atomic64_t values and accessing them via atomic64_* functions. This necessitates that we don't use cpu_context() as the left hand side of an assignment, ie. as a modifiable lvalue. In preparation for this introduce a new set_cpu_context() function & replace all assignments with cpu_context() on their left hand side with an equivalent call to set_cpu_context(). To enforce that cpu_context() should not be used for assignments, we rewrite it as a static inline function. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Unify ASID version checksPaul Burton2019-02-044-26/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new check_mmu_context() function to check an mm's ASID version & get a new one if it's outdated, and a check_switch_mmu_context() function which additionally sets up the new ASID & page directory. Simplify switch_mm() & various get_new_mmu_context() callsites in MIPS KVM by making use of the new functions, which will help reduce the amount of code that requires modification to gain MMID support. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Un-inline get_new_mmu_contextPaul Burton2019-02-043-19/+21
| | | | | | | | | | | | | | | | | | In preparation for adding MMID support to get_new_mmu_context() which will increase the size of the function somewhat, move it from asm/mmu_context.h into a C file. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Split obj-y to a file per linePaul Burton2019-02-041-3/+12
| | | | | | | | | | | | | | | | Split always-included objects to one per line in order to make it easier to modify the list of included objects. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Remove local_flush_tlb_mm()Paul Burton2019-02-045-28/+5
| | | | | | | | | | | | | | | | All 3 variants of local_flush_tlb_mm() are now effectively simple calls to drop_mmu_context(). Remove them and use drop_mmu_context() directly. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Remove redundant preempt_disable in local_flush_tlb_mm()Paul Burton2019-02-041-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The r4k variant of local_flush_tlb_mm() wraps its call to drop_mmu_context() with a preempt_disable() & preempt_enable() pair, but this is redundant since drop_mmu_context() disables interrupts and from Documentation/preempt-locking.txt: Note that you do not need to explicitly prevent preemption if you are holding any locks or interrupts are disabled, since preemption is implicitly disabled in those cases. Remove the redundant preempt_disable() & preempt_enable() calls. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Move drop_mmu_context() comment into appropriate blockPaul Burton2019-02-041-5/+5
| | | | | | | | | | | | | | | | | | | | drop_mmu_context() is preceded by a comment indicating what happens if the mm provided is currently active on the local CPU. Move that comment into the block that executes in this case, adjusting slightly to reflect its new location. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Consolidate drop_mmu_context() has-ASID checksPaul Burton2019-02-045-22/+10
| | | | | | | | | | | | | | | | | | | | | | If an mm does not have an ASID on the local CPU then drop_mmu_context() is always redundant, since there's no context to "drop". Various callers of drop_mmu_context() check whether the mm has been allocated an ASID before making the call. Move that check into drop_mmu_context() and remove it from callers to simplify them. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Avoid HTW stop/start when dropping an inactive mmPaul Burton2019-02-041-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | If drop_mmu_context() is called with an mm that is not currently active on the local CPU then there's no need for us to stop & start a hardware page table walker because it can't be fetching entries for the ASID corresponding to the mm we're operating on. Move the htw_stop() & htw_start() calls into the block which we run only if the mm is currently active, in order to avoid the redundant work. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Remove redundant get_new_mmu_context() cpu argumentPaul Burton2019-02-044-11/+15
| | | | | | | | | | | | | | | | | | | | | | | | get_new_mmu_context() accepts a cpu argument, but implicitly assumes that this is always equal to smp_processor_id() by operating on the local CPU's TLB & icache. Remove the cpu argument and have get_new_mmu_context() call smp_processor_id() instead. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Remove redundant drop_mmu_context() cpu argumentPaul Burton2019-02-045-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The drop_mmu_context() function accepts a cpu argument, but it implicitly expects that this is always equal to smp_processor_id() by allocating & configuring an ASID on the local CPU when the mm is active on the CPU indicated by the cpu argument. All callers do provide the value of smp_processor_id() to the cpu argument. Remove the redundant argument and have drop_mmu_context() call smp_processor_id() itself, making it clearer that the cpu variable always represents the local CPU. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: mm: Define activate_mm() using switch_mm()Paul Burton2019-02-041-27/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS has separate definitions of activate_mm() & switch_mm() which are identical apart from switch_mm() checking that the ASID is valid before acquiring a new one. We know that when activate_mm() is called cpu_context(X, mm) will be zero, and this will never be considered a valid ASID because we never allow the ASID version number to be zero, instead beginning with version 1 using asid_first_version(). Therefore switch_mm() will always allocate a new ASID when called for a new task, meaning that it will behave identically to activate_mm(). Take advantage of this to remove the duplication & define activate_mm() using switch_mm() just like many other architectures do. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: OCTEON: delete unused cvmx-smix-defs.hAaro Koskinen2019-01-281-276/+0
| | | | | | | | | | | | | | | | Delete unused cvmx-smix-defs.h. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: OCTEON: delete SMI/MDIO enableAaro Koskinen2019-01-281-20/+0
| | | | | | | | | | | | | | | | | | SMI/MDIO enable is handled by the OCTEON MDIO driver, so we can delete the duplicated functionality from the platform code. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
| * MIPS: remove meaningless generic-(CONFIG_GENERIC_CSUM) += checksum.hMasahiro Yamada2019-01-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This line is weird in multiple ways. (CONFIG_GENERIC_CSUM) might be a typo of $(CONFIG_GENERIC_CSUM). Even if you add '$' to it, $(CONFIG_GENERIC_CSUM) is never evaluated to 'y' because scripts/Makefile.asm-generic does not include include/config/auto.conf. So, the asm-generic wrapper of checksum.h is never generated. Even if you manage to generate it, it is never included by anyone because MIPS has the checkin header with the same file name: arch/mips/include/asm/checksum.h As you see in the top Makefile, the checkin headers are included before generated ones. LINUXINCLUDE := \ -I$(srctree)/arch/$(SRCARCH)/include \ -I$(objtree)/arch/$(SRCARCH)/include/generated \ ... Commit 4e0748f5beb9 ("MIPS: Use generic checksum functions for MIPS R6") already added the asm-generic fallback code in the checkin header: #ifdef CONFIG_GENERIC_CSUM #include <asm/generic/checksum.h> #else ... #endif Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-kernel@vger.kernel.org
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-12 13:52:03 +0000