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* Merge tag 'mips_5.10' of ↵Linus Torvalds2020-10-16158-3672/+1700
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - removed support for PNX833x alias NXT_STB22x - included Ingenic SoC support into generic MIPS kernels - added support for new Ingenic SoCs - converted workaround selection to use Kconfig - replaced old boot mem functions by memblock_* - enabled COP2 usage in kernel for Loongson64 to make use of 16byte load/stores possible - cleanups and fixes * tag 'mips_5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (92 commits) MIPS: DEC: Restore bootmem reservation for firmware working memory area MIPS: dec: fix section mismatch bcm963xx_tag.h: fix duplicated word mips: ralink: enable zboot support MIPS: ingenic: Remove CPU_SUPPORTS_HUGEPAGES MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bit MIPS: cpu-probe: introduce exclusive R3k CPU probe MIPS: cpu-probe: move fpu probing/handling into its own file MIPS: replace add_memory_region with memblock MIPS: Loongson64: Clean up numa.c MIPS: Loongson64: Select SMP in Kconfig to avoid build error mips: octeon: Add Ubiquiti E200 and E220 boards MIPS: SGI-IP28: disable use of ll/sc in kernel MIPS: tx49xx: move tx4939_add_memory_regions into only user MIPS: pgtable: Remove used PAGE_USERIO define MIPS: alchemy: Share prom_init implementation MIPS: alchemy: Fix build breakage, if TOUCHSCREEN_WM97XX is disabled MIPS: process: include exec.h header in process.c MIPS: process: Add prototype for function arch_dup_task_struct MIPS: idle: Add prototype for function check_wait ...
| * MIPS: DEC: Restore bootmem reservation for firmware working memory areaMaciej W. Rozycki2020-10-141-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a crash on DEC platforms starting with: VFS: Mounted root (nfs filesystem) on device 0:11. Freeing unused PROM memory: 124k freed BUG: Bad page state in process swapper pfn:00001 page:(ptrval) refcount:0 mapcount:-128 mapping:00000000 index:0x1 pfn:0x1 flags: 0x0() raw: 00000000 00000100 00000122 00000000 00000001 00000000 ffffff7f 00000000 page dumped because: nonzero mapcount Modules linked in: CPU: 0 PID: 1 Comm: swapper Not tainted 5.9.0-00858-g865c50e1d279 #1 Stack : 8065dc48 0000000b 8065d2b8 9bc27dcc 80645bfc 9bc259a4 806a1b97 80703124 80710000 8064a900 00000001 80099574 806b116c 1000ec00 9bc27d88 806a6f30 00000000 00000000 80645bfc 00000000 31232039 80706ba4 2e392e35 8039f348 2d383538 00000070 0000000a 35363867 00000000 806c2830 80710000 806b0000 80710000 8064a900 00000001 81000000 00000000 00000000 8035af2c 80700000 ... Call Trace: [<8004bc5c>] show_stack+0x34/0x104 [<8015675c>] bad_page+0xfc/0x128 [<80157714>] free_pcppages_bulk+0x1f4/0x5dc [<801591cc>] free_unref_page+0xc0/0x130 [<8015cb04>] free_reserved_area+0x144/0x1d8 [<805abd78>] kernel_init+0x20/0x100 [<80046070>] ret_from_kernel_thread+0x14/0x1c Disabling lock debugging due to kernel taint caused by an attempt to free bootmem space that as from commit b93ddc4f9156 ("mips: Reserve memory for the kernel image resources") has not been anymore reserved due to the removal of generic MIPS arch code that used to reserve all the memory from the beginning of RAM up to the kernel load address. This memory does need to be reserved on DEC platforms however as it is used by REX firmware as working area, as per the TURBOchannel firmware specification[1]: Table 2-2 REX Memory Regions ------------------------------------------------------------------------- Starting Ending Region Address Address Use ------------------------------------------------------------------------- 0 0xa0000000 0xa000ffff Restart block, exception vectors, REX stack and bss 1 0xa0010000 0xa0017fff Keyboard or tty drivers 2 0xa0018000 0xa001f3ff 1) CRT driver 3 0xa0020000 0xa002ffff boot, cnfg, init and t objects 4 0xa0020000 0xa002ffff 64KB scratch space ------------------------------------------------------------------------- 1) Note that the last 3 Kbytes of region 2 are reserved for backward compatibility with previous system software. ------------------------------------------------------------------------- (this table uses KSEG2 unmapped virtual addresses, which in the MIPS architecture are offset from physical addresses by a fixed value of 0xa0000000 and therefore the regions referred do correspond to the beginning of the physical address space) and we call into the firmware on several occasions throughout the bootstrap process. It is believed that pre-REX firmware used with non-TURBOchannel DEC platforms has the same requirements, as hinted by note #1 cited. Recreate the discarded reservation then, in DEC platform code, removing the crash. References: [1] "TURBOchannel Firmware Specification", On-line version, EK-TCAAD-FS-004, Digital Equipment Corporation, January 1993, Chapter 2 "System Module Firmware", p. 2-5 Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Fixes: b93ddc4f9156 ("mips: Reserve memory for the kernel image resources") Cc: stable@vger.kernel.org # v5.2+ Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: dec: fix section mismatchThomas Bogendoerfer2020-10-141-2/+2
| | | | | | | | | | | | | | | | Drop inline for memory setup functions and mark them __init to fix section mismatch of pmax_setup_memory_region. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Acked-by: Maciej W. Rozycki <macro@linux-mips.org>
| * mips: ralink: enable zboot supportChuanhong Guo2020-10-131-0/+1
| | | | | | | | | | | | | | | | | | | | Some of these ralink devices come with an ancient u-boot which can't extract LZMA properly when image gets too big. Enable zboot support to get a self-extracting kernel instead of relying on broken u-boot support. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: ingenic: Remove CPU_SUPPORTS_HUGEPAGESPaul Cercueil2020-10-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | While it is true that Ingenic SoCs support huge pages, we cannot use them yet as PTEs don't have any single bit that is free. Right now, having that symbol only causes build errors, so remove it until the situation with PTEs is resolved. Fixes: f0f4a753079c ("MIPS: generic: Add support for Ingenic SoCs") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: cpu-probe: remove MIPS_CPU_BP_GHIST option bitThomas Bogendoerfer2020-10-124-11/+4
| | | | | | | | | | | | | | | | MIPS_CPU_BP_GHIST is only set two times and more or less immediately used in cpu-probe.c itself. Remove this option to make room in options word. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: cpu-probe: introduce exclusive R3k CPU probeThomas Bogendoerfer2020-10-122-1/+178
| | | | | | | | | | | | | | | | | | | | | | | | Running a kernel on a R3k of machine definitly will never see one of the newer CPU cores. And since R3k system usually are low on memory we could save quite some kbytes: text data bss dec hex filename 15070 88 32 15190 3b56 arch/mips/kernel/cpu-probe.o 844 4 16 864 360 arch/mips/kernel/cpu-r3k-probe.o Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: cpu-probe: move fpu probing/handling into its own fileThomas Bogendoerfer2020-10-124-324/+364
| | | | | | | | | | | | | | | | | | cpu-probe.c has grown when supporting more and more CPUs and there are use cases where probing for all the CPUs isn't useful like running on a R3k system. But still the fpu handling is nearly the same. For sharing put the fpu code into it's own file. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: replace add_memory_region with memblockThomas Bogendoerfer2020-10-1228-149/+82
| | | | | | | | | | | | | | | | add_memory_region was the old interface for registering memory and was already changed to used memblock internaly. Replace it by directly calling memblock functions. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Loongson64: Clean up numa.cTiezhu Yang2020-10-122-31/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (1) Replace nid_to_addroffset() with nid_to_addrbase() and then remove the related useless code. (2) Since end_pfn = start_pfn + node_psize, use "node_psize" instead of "end_pfn - start_pfn" to avoid the redundant calculation. (3) After commit 6fbde6b492df ("MIPS: Loongson64: Move files to the top-level directory"), CONFIG_ZONE_DMA32 is always set for Loongson64 due to MACH_LOONGSON64 selects ZONE_DMA32, so no need to use ifdef any more, just remove it. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Loongson64: Select SMP in Kconfig to avoid build errorTiezhu Yang2020-10-122-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current code, CONFIG_SMP can be set as N by user on the Loongson platform, then there exists the following build error under !CONFIG_SMP: CC arch/mips/kernel/asm-offsets.s In file included from ./include/linux/gfp.h:9:0, from ./include/linux/xarray.h:14, from ./include/linux/radix-tree.h:18, from ./include/linux/fs.h:15, from ./include/linux/compat.h:17, from arch/mips/kernel/asm-offsets.c:12: ./include/linux/topology.h: In function 'numa_node_id': ./include/linux/topology.h:119:2: error: implicit declaration of function 'cpu_logical_map' [-Werror=implicit-function-declaration] return cpu_to_node(raw_smp_processor_id()); ^ cc1: some warnings being treated as errors scripts/Makefile.build:117: recipe for target 'arch/mips/kernel/asm-offsets.s' failed make[1]: *** [arch/mips/kernel/asm-offsets.s] Error 1 Select SMP in Kconfig to avoid the above build error and then remove CONFIG_SMP=y in loongson3_defconfig. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * mips: octeon: Add Ubiquiti E200 and E220 boardsMikhail Gusarov2020-10-121-0/+4
| | | | | | | | | | | | | | | | | | | | These boards are used in - Ubiquiti EdgeRouter (E200), - Ubiquiti EdgeRouter Pro (E200) and - Ubiquiti Security Gateway Pro 4 (E220). Signed-off-by: Mikhail Gusarov <dottedmag@dottedmag.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: SGI-IP28: disable use of ll/sc in kernelThomas Bogendoerfer2020-10-081-1/+1
| | | | | | | | | | | | | | | | SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock up, if ll/sc sequences are issued in certain order. Since those systems are all non-SMP, we can disable ll/sc usage in kernel. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: tx49xx: move tx4939_add_memory_regions into only userThomas Bogendoerfer2020-10-083-19/+13
| | | | | | | | | | | | tx4939_add_memory_regions() is only used in txx9/rbtx4939/prom.c. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: pgtable: Remove used PAGE_USERIO defineThomas Bogendoerfer2020-10-061-2/+0
| | | | | | | | | | | | There are no users of PAGE_USERIO. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: alchemy: Share prom_init implementationThomas Bogendoerfer2020-10-065-69/+20
| | | | | | | | | | | | | | All boards have the same prom_init() function. Move it to common code and delete the duplicates. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: alchemy: Fix build breakage, if TOUCHSCREEN_WM97XX is disabledThomas Bogendoerfer2020-10-061-0/+7
| | | | | | | | | | | | | | Only include wm97xx touchscreen probing code, if driver is enabled. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: process: include exec.h header in process.cPujin Shi2020-09-301-0/+1
| | | | | | | | | | | | | | arch/mips/kernel/process.c:696:15: error: no previous prototype for 'arch_align_stack' [-Werror=missing-prototypes] Signed-off-by: Pujin Shi <shipujin.t@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: process: Add prototype for function arch_dup_task_structPujin Shi2020-09-301-0/+1
| | | | | | | | | | | | | | | | | | This commit adds a prototype to fix warning at W=1: arch/mips/kernel/process.c:95:5: error: no previous prototype for 'arch_dup_task_struct' [-Werror=missing-prototypes] Signed-off-by: Pujin Shi <shipujin.t@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: idle: Add prototype for function check_waitPujin Shi2020-09-271-0/+2
| | | | | | | | | | | | | | | | | | This commit adds a prototype to fix warning at W=1: arch/mips/kernel/idle.c:126:13: error: no previous prototype for 'check_wait' [-Werror=missing-prototypes] Signed-off-by: Pujin Shi <shipujin.t@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Increase range of CONFIG_FORCE_MAX_ZONEORDERPaul Cercueil2020-09-271-1/+1
| | | | | | | | | | | | | | | | | | There is nothing that prevents us from using lower maximum values. It's something that we actually want, when using bigger page sizes on devices with low RAM. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.周琰杰 (Zhou Yanjie)2020-09-271-0/+2
| | | | | | | | | | | | | | | | | | 1.Fix bugs when detecting ways value of JZ4775's L2 cache. 2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Ingenic: Add system type for new Ingenic SoCs.周琰杰 (Zhou Yanjie)2020-09-272-0/+14
| | | | | | | | | | | | | | | | | | Add JZ4775, X1000E, X2000, and X2000E system type for cat /proc/cpuinfo to give out JZ4775, X1000E, X2000 and X2000E. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * Revert "MIPS: OCTEON: use devm_platform_ioremap_resource"Thomas Bogendoerfer2020-09-231-1/+9
| | | | | | | | | | | | | | | | | | This reverts commit 0ee69c589ec8659560910815f32c13af8587a779. Resource is still needed later in the code, so using devm_platform_ioremap_resource is no win at all. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: kexec: Add crashkernel=YM handlingYouling Tang2020-09-211-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the kernel crashkernel parameter is specified with just a size, we are supposed to allocate a region from RAM to store the crashkernel. However, MIPS merely reserves physical address zero with no checking that there is even RAM there. Fix this by lifting similar code from x86, importing it to MIPS with the MIPS specific parameters added. In the absence of any platform specific information, we allocate the crashkernel region from the first 512MB of physical memory (limited to CKSEG0 or KSEG0 address range). When X is not specified, crash_base defaults to 0 (crashkernel=YM@XM). E.g. without this patch: The environment as follows: [ 0.000000] MIPS: machine is loongson,loongson64c-4core-ls7a ... [ 0.000000] Kernel command line: root=/dev/sda2 crashkernel=96M ... The warning as follows: [ 0.000000] Invalid memory region reserved for crash kernel And the iomem as follows: 00200000-0effffff : System RAM 00200000-00b47f87 : Kernel code 00b47f88-00dfffff : Kernel data 00e60000-01f73c7f : Kernel bss 1a000000-1bffffff : pci@1a000000 ... With this patch: After increasing crash_base <= 0 handling. And the iomem as follows: 00200000-0effffff : System RAM 00200000-00b47f87 : Kernel code 00b47f88-00dfffff : Kernel data 00e60000-01f73c7f : Kernel bss 04000000-09ffffff : Crash kernel 1a000000-1bffffff : pci@1a000000 ... Signed-off-by: Youling Tang <tangyouling@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Loongson64: Add UART node for LS7A PCHTiezhu Yang2020-09-211-0/+39
| | | | | | | | | | | | | | | | | | | | When I update the latest kernel on the Loongson platform used with LS7A bridge chip, the serial console has no output, this is because the machine uses LS7A UART0 instead of CPU UART0, add UART node for LS7A PCH to enhance the compatibility. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Ingenic: Add CPU nodes for Ingenic SoCs.周琰杰 (Zhou Yanjie)2020-09-216-1/+93
| | | | | | | | | | | | | | | | | | | | | | Add 'cpus' node to the jz4725b.dtsi, jz4740.dtsi, jz4770.dtsi, jz4780.dtsi, x1000.dtsi, and x1830.dtsi files. Tested-by: H. Nikolaus Schaller <hns@goldelico.com> Tested-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: malta: remove mach-malta/malta-dtshim.h header fileThomas Bogendoerfer2020-09-213-26/+2
| | | | | | | | | | | | | | To clean up mach-* directories move external declaration of malta_dt_shim() to mips-boards/malta.h and remove malta-dtshim.h. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: malta: remove unused header fileThomas Bogendoerfer2020-09-211-33/+0
| | | | | | | | | | | | Remove unused heasder file asm/mach-malta/malta-pm.h. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: alchemy: remove unused ALCHEMY_GPIOINT_AU1000Thomas Bogendoerfer2020-09-211-7/+0
| | | | | | | | | | | | Remove unused config option ALCHEMY_GPIOINT_AU1000. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: alchemy: remove unused ALCHEMY_GPIOINT_AU1300Thomas Bogendoerfer2020-09-212-141/+0
| | | | | | | | | | | | Remove unused config option ALCHEMY_GPIOINT_AU1300 and related code. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: SGI-IP30: Move irq bits to better header filesThomas Bogendoerfer2020-09-214-87/+67
| | | | | | | | | | | | | | Move HEART specific parts of mach-ip30/irq.h to asm/sgi/heart.h and IP30 specific parts to sgi-ip30/ip30-common.h. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Loongson-3: Calculate ra properly when unwinding the stackHuacai Chen2020-09-211-1/+15
| | | | | | | | | | | | | | | | | | Loongson-3 has 16-bytes load/store instructions: gslq and gssq. This patch calculate ra properly when unwinding the stack, if ra is saved by gssq and restored by gslq. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Loongson-3: Enable COP2 usage in kernelHuacai Chen2020-09-216-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loongson-3's COP2 is Multi-Media coprocessor, it is disabled in kernel mode by default. However, gslq/gssq (16-bytes load/store instructions) overrides the instruction format of lwc2/swc2. If we wan't to use gslq/ gssq for optimization in kernel, we should enable COP2 usage in kernel. Please pay attention that in this patch we only enable COP2 in kernel, which means it will lose ST0_CU2 when a process go to user space (try to use COP2 in user space will trigger an exception and then grab COP2, which is similar to FPU). And as a result, we need to modify the context switching code because the new scheduled process doesn't contain ST0_CU2 in its THERAD_STATUS probably. For zboot, we disable gslq/gssq be generated by toolchain. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: context switch: Use save/restore instead of set/clear for Status.CU2Huacai Chen2020-09-211-1/+3
| | | | | | | | | | | | | | | | | | Some processors (such as Loongson-3) need to enable CU2 in kernel mode, current set/clear method will lose Status.CU2 during context switching, so use save/restore method instead. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: kernel: include probes-common.h header in branch.cPujin Shi2020-09-211-0/+2
| | | | | | | | | | | | | | | | arch/mips/kernel/branch.c:876:5: error: no previous prototype for '__insn_is_compact_branch' [-Werror=missing-prototypes] Signed-off-by: Pujin Shi <shipujin.t@gmail.com> Signed-off-by: Pujin Shi <shipj@lemote.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Make setup_elfcorehdr and setup_elfcorehdr_size staticJason Yan2020-09-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | This addresses the following sparse warning: arch/mips/kernel/setup.c:446:33: warning: symbol 'setup_elfcorehdr_size' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: configs: Regenerate configs of Ingenic boardsPaul Cercueil2020-09-186-35/+11
| | | | | | | | | | | | | | | | For each board the MACH_INGENIC_SOC option was selected instead of MACH_INGENIC. Nothing else was changed in the menuconfig. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: jz4740: Rename jz4740 folders to ingenicPaul Cercueil2020-09-184-2/+2
| | | | | | | | | | | | | | | | | | | | Now that all the jz4740 platform code has been removed, and we're left with only a Kconfig and the cpu-feature-overrides.h file, finalize the cleanup process by renaming the jz4740 and include/mach-jz4740 folders to ingenic and include/mach-ingenic. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: jz4740: Drop all obsolete filesPaul Cercueil2020-09-184-170/+0
| | | | | | | | | | | | | | | | | | Support for Ingenic SoCs is now provided by the arch/mips/generic/ code, so all files in the arch/mips/jz4740/ folder can dropped, except for the Kconfig, and the cpu-feature-overrides.h header file. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: generic: Add support for Ingenic SoCsPaul Cercueil2020-09-187-18/+149
| | | | | | | | | | | | | | | | | | | | | | Add support for Ingenic SoCs in arch/mips/generic/. The Kconfig changes are here to ensure that it is possible to compile either a generic kernel that supports Ingenic SoCs, or a Ingenic-only kernel, both using the same code base, to avoid duplicated code. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: generic: Increase NR_IRQS to 256Paul Cercueil2020-09-181-1/+1
| | | | | | | | | | | | | | 128 IRQs is not enough to support Ingenic SoCs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: generic: Add support for zbootPaul Cercueil2020-09-182-0/+2
| | | | | | | | | | | | | | | | There is no reason we can't create compressed kernels here, so select the option SYS_SUPPORTS_ZBOOT. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: generic: Support booting with built-in or appended DTBPaul Cercueil2020-09-181-5/+4
| | | | | | | | | | | | | | | | | | | | | | The plat_get_fdt() checked that the kernel was booted using UHI before reading the 'fw_passed_dtb' variable. However, this variable is also set when the DT has been appended, or when it has been built into the kernel. Support these usecases by removing the UHI check. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: generic: Init command line with fw_init_cmdline()Paul Cercueil2020-09-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function bootcmdline_init() in arch/mips/kernel/setup.c will populate the boot_command_line string using the parameters hardcoded in the kernel, and those provided in the devicetree file. Then, it would append the content of the arcs_cmdline variable, which is filled by the board's plat_mem_setup() function. The plat_mem_setup() function for the generic MIPS board would just copy the current boot_command_line to arcs_cmdline, which is nonsense for two reasons: - the result will be appended to the boot_command_line anyway, so all it does is duplicate every single parameter on the command line; - the code did not perform at all what it's supposed to, which is to retrieve the parameters passed by the bootloader. Fix this by calling fw_init_cmdline() in plat_mem_setup(), which will properly initialize arcs_cmdline to the parameters passed by the bootloader. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: generic: Allow boards to set system typePaul Cercueil2020-09-181-0/+5
| | | | | | | | | | | | | | | | Check for the system_type variable in the get_system_type() function. If non-NULL, return it as the system type. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: Kconfig: add MIPS_GENERIC_KERNEL symbolPaul Cercueil2020-09-182-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS_GENERIC symbol now won't select any other configuration option. The MIPS_GENERIC_KERNEL will select all the options that the previous MIPS_GENERIC option did select, and will select MIPS_GENERIC as well. The whole point of this, is that it now becomes possible to compile a kernel for a SoC supported by the arch/mips/generic/ code, without making that kernel generic itself. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: cpu-probe: ingenic: Fix broken BUG_ONPaul Cercueil2020-09-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous code was doing: BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); This only worked as the "cpu_has_counter" macro was overridden in <cpu-feature-overrides.h>. The default "cpu_has_counter" macro is non-constant, which triggered the BUG_ON() independently of the value returned by the macro. What we want to check here, is that *if* the macro was overridden to a compile-time constant, then must be defined to zero, otherwise it's a bug. So the correct check is: BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter); Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: cpu-probe: Mark XBurst CPU as having vtagged cachesPaul Cercueil2020-09-181-0/+3
| | | | | | | | | | | | | | | | | | | | XBurst CPUs present in Ingenic SoCs have virtually tagged caches, according to the <cpu-features-override.h> header. Add that information to cpu_probe_ingenic(). Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| * MIPS: cpu-probe: Set Ingenic's writecombine to _CACHE_CACHABLE_WAPaul Cercueil2020-09-182-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously, in cpu_probe_ingenic(), c->writecombine was set to _CACHE_UNCACHED_ACCELERATED, but this macro was defined differently when CONFIG_MACH_INGENIC was set. This made it impossible to support multiple CPUs. Address this issue by setting c->writecombine to _CACHE_CACHABLE_WA directly and removing the dependency on CONFIG_MACH_INGENIC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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