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* powerpc/85xx: separate cpm2 pic initDmitry Eremin-Solenikov2011-11-2416-157/+89
| | | | | | | | Separate handling of CPM2 PIC initialization to mpc85xx_cpm2_pic_init() function. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/83xx: make mpc830x_rdb use mpc83xx_setup_pciDmitry Eremin-Solenikov2011-11-241-8/+1
| | | | | | | | | | | Traditionally mpc830x_rdb board file searched for mpc8308-pcie devices. However both in-kernel dts from the beginning declared those pcie units as compatible with mpc8314-pci, which is handled by mpc83xx_setup_pci(). Drop special handling for mpc8308 and use common function instead. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/83xx: merge PCI bridge additionsDmitry Eremin-Solenikov2011-11-2413-80/+34
| | | | | | | | | Nearly all mpc83xx-based boards have a common piece of code - one that loops over all pci/pcie bridges and registers them. Merge that code into a special function common to all boards. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/83xx: consolidate of_platform_bus_probe callsDmitry Eremin-Solenikov2011-11-2415-180/+31
| | | | | | | | | | | | | 83xx board files have a lot of duplication in *_declare_of_platform_devices() functions. Merge that into a single function common to most of the boards. The only leftover is mpc834x_itx.c board file which explicitly asks for fsl,pq2pro-localbus, as corresponding bindings don't provide "simple-bus" compatibility in localbus node. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/83xx: consolidate init_IRQ functionsDmitry Eremin-Solenikov2011-11-2415-287/+68
| | | | | | | | | On mpc83xx platform nearly all _init_IRQ functions look alike. They either just setup ipic, or setup ipic and QE PIC. Separate this to special functions to be either referenced from ppc_md, or called from board file. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: add pixis indirect mode device tree nodeTimur Tabi2011-11-241-0/+14
| | | | | | | | | | | | | | | | | | | The Freescale P1022 has a unique pin muxing "feature" where the DIU video controller's video signals are muxed with 24 of the local bus address signals. When the DIU is enabled, the bulk of the local bus is disabled, preventing access to memory-mapped devices like NOR flash and the pixis FPGA. In this situation, the pixis supports "indirect mode", which allows access to the pixis itself by reading/writing addresses on specific local bus chip selects. CS0 is used to select which pixis register to access, and CS1 is used to read/write the value. To support this, we introduce another board-control child node of the localbus node that contains a 'reg' property for CS0 and CS1. This will produce the correct physical addresses for CS0 and CS1. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add lbc suspend support for PMJia Hongtao2011-11-242-2/+41
| | | | | | | | | | | | | | Power supply for LBC registers is off when system go to deep-sleep state. We save the values of registers before suspend and restore to registers after resume. We removed the last two reservation arrays from struct fsl_lbc_regs for allocating less memory and minimizing the memcpy size. Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/fsl-pci: Don't hide resource for pci/e when configured as Agent/EPJason Jin2011-11-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | Current pci/pcie init code will hide the pci/pcie host resource. But did not judge it is host/RC or agent/EP. If configured as agent/EP, we should avoid hiding its resource in the host side. In PCI system, the Programing Interface can be used to judge the host/agent status: Programing Interface = 0: host Programing Interface = 1: Agent In PCIE system, both the Programing Interface and Header type can be used to judge the RC/EP status. Header Type = 0: EP Header Type = 1: RC Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Update SRIO device tree nodesKumar Gala2011-11-2415-49/+285
| | | | | | | Update all dts files that support SRIO controllers to match the new fsl,srio device tree binding. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P5020DS device treeKumar Gala2011-11-244-719/+441
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p5020-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P4080DS device treesKumar Gala2011-11-244-758/+498
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p4080-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P3060QDS device treeKumar Gala2011-11-244-722/+430
| | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p3060-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Removed mpic interrupt-parent from sec nodes, just use top level * Fixed l3-cache IRQs, we have 2 CPCs, so we should have IRQs for both Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P3041DS device treeKumar Gala2011-11-244-731/+454
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p3041-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level * Fixed some dcsr compatiable typo's from 'p43041' to 'p3041' Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P2041RDB device treeKumar Gala2011-11-244-694/+425
| | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Adding of MPIC timer blocks * Dropping "fsl,p2041-IP..." from compatibles for standard blocks * Removed mpic interrupt-parent from dcsr-epu node, just use top level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P2020RDB device treeKumar Gala2011-11-244-644/+22
| | | | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Updated spi node to new espi binding specification * Renamed 'sdhci' node to 'sdhc' * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Fixed wrong reg offsets for mdio nodes associated with etsec2 & * etsec3 * Dropping "fsl,p2020-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P2020DS device treeKumar Gala2011-11-245-397/+634
| | | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Updated spi node to new espi binding specification * Renamed 'sdhci' node to 'sdhc' * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Fixed wrong reg offsets for mdio nodes associated with etsec2 & etsec3 * Dropping "fsl,p2020-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P1023RDS device treeKumar Gala2011-11-243-358/+322
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1023-IP..." from compatibles for standard blocks * Removed incorrect power/pmc node, there are no etsec on P1023 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P1022DS device treeKumar Gala2011-11-243-418/+320
| | | | | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum * Updated spi node to new espi binding specification * Renamed SDHC node from 'sdhci' to 'sdhc' * Added usb node for 2nd usb controller * Dropping "fsl,p1022-IP..." from compatibles for standard blocks * Fixed bug in local bus range node for CS2, was maping to 0x0 0x0xffa00000 instead of 0xf 0xffa00000 * Fixed localbus reg property should have been 0xf 0xffe05000 Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Timur Tabi <timur@freescale.com>
* powerpc/85xx: Rework P1021MDS device treeKumar Gala2011-11-243-400/+314
| | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Added usb node for 2nd usb controller * Dropping "fsl,p1021-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add P1020RDB 36-bit address map device treeKumar Gala2011-11-241-0/+66
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P1020RDB device treeKumar Gala2011-11-245-631/+492
| | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Dropping "fsl,p1020-IP..." from compatibles for standard blocks * Fixed PCIe interrupt-maps to have proper number of cells * Added mdio node for etsec@26000 * Added usb node for 2nd usb controller Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add a P1010RDB 36-bit address map device treeKumar Gala2011-11-241-0/+89
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add crypto engine to P1010 SoC device treeKumar Gala2011-11-241-0/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add RTC to P1010RDB device treeKumar Gala2011-11-241-0/+7
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework P1010RDB and P1010 device treeKumar Gala2011-11-245-592/+493
| | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Dropping "fsl,p1010-IP..." from compatibles for standard blocks * PCI interrupt map - wrong IRQs for PCI-0 controller * SDHC interrupt sense was wrong Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8572DS device treeKumar Gala2011-11-247-2110/+788
| | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8569MDS device treeKumar Gala2011-11-243-376/+389
| | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Renamed SDHC node from 'sdhci' to 'sdhc' * Dropping "fsl,mpc8569-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8568MDS device treeKumar Gala2011-11-243-417/+393
| | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Dropping "fsl,mpc8568-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8548CDS device treesKumar Gala2011-11-243-383/+327
| | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Moved mdio nodes up one level instead of under tsec nodes * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Added MPIC / PCIe msi node * Dropping "fsl,mpc8548-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8544DS device treeKumar Gala2011-11-244-435/+453
| | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8536DS device treesKumar Gala2011-11-245-829/+489
| | | | | | | | | | | | | | | | | | | | | Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) * and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8536 SoC template [ marked as MPC8572 compatiable to get errata handling that applies ] * Added missing cache-line-size & cache-size properties missing from L2-cache node * Added IP level IEEE 1588 / ptp timer node Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: create dts components to build up an SoCKumar Gala2011-11-2448-0/+2575
| | | | | | | Introduce some common components that we can utilize to build up the various PQ3/85xx device trees. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: p1020si.dtsi update interrupt handlingKumar Gala2011-11-241-61/+56
| | | | | | | | * set interrupt-parent at root so its not duplicate in every node * Add mpic timers * Move to 4-prop cells for mpic timer Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add ethernet magic packet property to P1020 device treeKumar Gala2011-11-241-0/+3
| | | | | | | All eTSEC2 controllers support waking on magic packet so fixup device tree to report that. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Update P1020 SEC3.3 node to match actual SoC HWKumar Gala2011-11-241-4/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Update SPI binding to match binding spec for P1020RDBKumar Gala2011-11-242-20/+15
| | | | | | | The SPI node is out of date with regards to the binding for fsl-espi and driver support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework PCI nodes on P1020RDBKumar Gala2011-11-242-28/+38
| | | | | | | | * Move SoC specific details like irq mapping to SoC dtsi * Update interrupt property to cover both error interrupt and PCIe runtime interrupts Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Simplify P1020RDB CAMP dts using includesKumar Gala2011-11-242-161/+4
| | | | | | | | If we include the p1020rdb.dts instead of p1020si.dts we greatly reduce duplication and maintenance. We can just list which devices are disabled for the given core and mpic protected sources. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Update device tree bus probe for new RapidIO node bindingKai Jiang2011-11-243-3/+3
| | | | | | | | | Update of_platform_bus_probe() RapidIO node to be compitable with new RapidIO dts compatible property. Signed-off-by: Kai Jiang <Kai.Jiang@freescale.com> Acked-by: Alexandre Bounine <alexandre.bounine@idt.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-rio: Add two ports and rapidio message units supportLiu Gang2011-11-243-423/+545
| | | | | | | | | | | | | | Usually, freescale rapidio endpoint can support one or two 1x or 4X LP-Serial link interfaces, and rapidio message transactions can be implemented by two message units. This adds the support of two rapidio ports and initializes message unit 0 and message unit 1. And these ports and message units can work simultaneously. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: Alexandre Bounine <alexandre.bounine@idt.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-rio: Split rio driver into two parts, RapidIO endpoint and message unitLiu Gang2011-11-244-1128/+1267
| | | | | | | | | | | | | | | The Freescale PowerPC RapidIO controller consists of a RapidIO endpoint and a RapidIO message unit(RMU). Or use RapidIO message manager(RMan) to replace the RMU in DPAA architecture. Therefore, we should split the code into two function modules according to the hardware architecture. Add new struct for RMU module, and new initialization function to set up RMU module. This policy is very conducive to adding new module like RMan, or adding multi-ports or message units support. Signed-off-by: Lian Minghuan <Minghuan.Lian@freescale.com> Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: Alexandre Bounine <alexandre.bounine@idt.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* arch/powerpc/sysdev/ehv_pic.c: add missing kfreeJulia Lawall2011-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At this point, ehv_pic has been allocated but not stored anywhere, so it should be freed before leaving the function. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @exists@ local idexpression x; statement S,S1; expression E; identifier fl; expression *ptr != NULL; @@ x = \(kmalloc\|kzalloc\|kcalloc\)(...); ... if (x == NULL) S <... when != x when != if (...) { <+...kfree(x)...+> } when any when != true x == NULL x->fl ...> ( if (x == NULL) S1 | if (...) { ... when != x when forall ( return \(0\|<+...x...+>\|ptr\); | * return ...; ) } ) // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/fsl-lbc: Fix for fsl_upmAlexandre Rusev2011-11-241-0/+1
| | | | | | | | | | If Freescale LBC driver fails to initialise itself from device tree, then internal structure is freed only but not NULL-fied. As result functions fsl_lbc_find() after checking the structure is not NULL are trying to access device registers. Signed-off-by: Alexandre Rusev <arusev@dev.rtsoft.ru> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/qe: Fixup QE_General4 errataJoakim Tjernlund2011-11-241-1/+1
| | | | | | | | | | QE_General4 should only round up the divisor iff divisor is > 3. Rounding up lower divisors makes the error too big, causing USB on MPC832x to fail. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Fix compile error on p3060_qds.cKumar Gala2011-11-231-1/+1
| | | | | | | | | arch/powerpc/platforms/85xx/p3060_qds.c: In function '__machine_initcall_p3060_qds_declare_of_platform_devices': arch/powerpc/platforms/85xx/p3060_qds.c:73:1: error: implicit declaration of function 'declare_of_platform_devices' declare_of_platform_devices should have been corenet_ds_publish_devices. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p3060qds: Fix select of 'MPC8xxx_GPIO'Paul Bolle2011-11-231-1/+1
| | | | | | | | | | | | | | The driver for the Freescale P3060 QDS got added by commit 96cc017c5b ("[...] Add support for P3060QDS board"). Its Kconfig entry selects MPC8xxx_GPIO. But at the time that driver got added MPC8xxx_GPIO was already renamed to GPIO_MPC8XXX, by commit c68308dd50c ("gpio: move mpc8xxx/512x gpio driver to drivers/gpio"). So make this driver select GPIO_MPC8XXX. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p1023: set IRQ[4:6,11] to active-high level sensitive for PCIeRoy Zang2011-11-231-4/+13
| | | | | | | | | | | | | P1023 external IRQ[4:6, 11] are not pin out, but the interrupts are utilized by the PCIe controllers. As they are not exposed as pins we need to set them as active-high (internal to the SoC these interrupts are pulled down). IRQs[0:3,7:10] are pulled up on the board so we have them set as active-low. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* microblaze: bury asm/namei.hAl Viro2011-11-211-22/+0
| | | | | | | altroot support has been gone for years, along with arch/*/asm/namei.h; looks like a dummy survivor that sat it out in microblaze tree... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* fix braino in um patchset (mea culpa)Al Viro2011-11-211-1/+1
| | | | | | | wrong register returned... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds2011-11-202-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (86 commits) ipv4: fix redirect handling ping: dont increment ICMP_MIB_INERRORS sky2: fix hang in napi_disable sky2: enforce minimum ring size bonding: Don't allow mode change via sysfs with slaves present f_phonet: fix page offset of first received fragment stmmac: fix pm functions avoiding sleep on spinlock stmmac: remove spin_lock in stmmac_ioctl. stmmac: parameters auto-tuning through HW cap reg stmmac: fix advertising 1000Base capabilties for non GMII iface stmmac: use mdelay on timeout of sw reset sky2: version 1.30 sky2: used fixed RSS key sky2: reduce default Tx ring size sky2: rename up/down functions sky2: pci posting issues sky2: fix hang on shutdown (and other irq issues) r6040: fix check against MCRO_HASHEN bit in r6040_multicast_list MAINTAINERS: change email address for shemminger pch_gbe: Move #include of module.h ...
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