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* bus: arm-ccn: Fix node->XP config conversionPawel Moll2015-08-031-1/+1
| | | | | | | | | | | | | commit a18f8e97fe69195823d7fb5c68a8d6565f39db4b upstream. Events defined as watchpoints on nodes must have their config values converted so that they apply to the respective node's XP. The function setting new values was using wrong mask for the "port" field, resulting in corrupted value. Fixed now. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'mvebu-fixes-4.1-3' of git://git.infradead.org/linux-mvebu into fixesArnd Bergmann2015-06-011-90/+19
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge "mvebu fixes for 4.1 (part 3)" from Gregory CLEMENT: Disable unused internal RTC for Mamba from linksys (Armada XP) And 2 commits fixing regressions on mvebu-mbus: - the first one for Kirkwood or Orion SoC - the second one for DMA when the platform have more than 4GB (only possible on Armada XP as far as I know) * tag 'mvebu-fixes-4.1-3' of git://git.infradead.org/linux-mvebu: Revert "bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window" bus: mvebu-mbus: do not set WIN_CTRL_SYNCBARRIER on non io-coherent platforms. ARM: mvebu: armada-xp-linksys-mamba: Disable internal RTC
| * Revert "bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus ↵Thomas Petazzoni2015-05-281-89/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | bridge window" This reverts commit 1737cac69369 ("bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window"), because it breaks DMA on platforms having more than 2 GB of RAM. This commit changed the information reported to DMA masters device drivers through the mv_mbus_dram_info() function so that the returned DRAM ranges do not overlap with I/O windows. This was necessary as a preparation to support the new CESA Crypto Engine driver, which will use DMA for cryptographic operations. But since it does DMA with the SRAM which is mapped as an I/O window, having DRAM ranges overlapping with I/O windows was problematic. To solve this, the above mentioned commit changed the mvebu-mbus to adjust the DRAM ranges so that they don't overlap with the I/O windows. However, by doing this, we re-adjust the DRAM ranges in a way that makes them have a size that is no longer a power of two. While this is perfectly fine for the Crypto Engine, which supports DRAM ranges with a granularity of 64 KB, it breaks basically all other DMA masters, which expect power of two sizes for the DRAM ranges. Due to this, if the installed system memory is 4 GB, in two chip-selects of 2 GB, the second DRAM range will be reduced from 2 GB to a little bit less than 2 GB to not overlap with the I/O windows, in a way that results in a DRAM range that doesn't have a power of two size. This means that whenever you do a DMA transfer with an address located in the [ 2 GB ; 4 GB ] area, it will freeze the system. Any serious DMA activity like simply running: for i in $(seq 1 64) ; do dd if=/dev/urandom of=file$i bs=1M count=16 ; done in an ext3 partition mounted over a SATA drive will freeze the system. Since the new CESA crypto driver that uses DMA has not been merged yet, the easiest fix is to simply revert this commit. A follow-up commit will introduce a different solution for the CESA crypto driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Fixes: 1737cac69369 ("bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge window") Cc: <stable@vger.kernel.org> # v4.0+ Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * bus: mvebu-mbus: do not set WIN_CTRL_SYNCBARRIER on non io-coherent platforms.Nicolas Schichan2015-05-281-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit a0b5cd4ac2d6 ("bus: mvebu-mbus: use automatic I/O synchronization barriers") enabled the usage of automatic I/O synchronization barriers by enabling bit WIN_CTRL_SYNCBARRIER in the control registers of MBus windows, but on non io-coherent platforms (orion5x, kirkwood and dove) the WIN_CTRL_SYNCBARRIER bit in the window control register is either reserved (all windows except 6 and 7) or enables read-only protection (windows 6 and 7). Signed-off-by: Nicolas Schichan <nschichan@freebox.fr> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v4.0+ Fixes: a0b5cd4ac2d6 ("bus: mvebu-mbus: use automatic I/O synchronization barriers") Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | MIPS: Fix CDMM to use native endian MMIO readsJames Hogan2015-05-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS Common Device Memory Map (CDMM) is internal to the core and has native endianness. There is therefore no need to byte swap the accesses on big endian targets, so convert the CDMM bus driver to use __raw_readl() rather than readl(). Fixes: 8286ae03308c ("MIPS: Add CDMM bus support") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9904/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | drivers: CCI: fix used_mask init in validate_group()Mark Salter2015-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently in validate_group(), there is a static initializer for fake_pmu.used_mask which is based on CPU_BITS_NONE but the used_mask array size is based on CCI_PMU_MAX_HW_EVENTS. CCI_PMU_MAX_HW_EVENTS is not based on NR_CPUS, so CPU_BITS_NONE is not correct and will cause a build failure if NR_CPUS is set high enough to make CPU_BITS_NONE larger than used_mask. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | bus: omap_l3_noc: Fix master id address decoding for OMAP5Suman Anna2015-05-042-15/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The L3 Error handling on OMAP5 for the most part is very similar to that of OMAP4, and had leveraged common data structures and register layout definitions so far. Upon closer inspection, there are a few minor differences causing an incorrect decoding and reporting of the master NIU upon an error: 1. The L3_TARG_STDERRLOG_MSTADDR.STDERRLOG_MSTADDR occupies 11 bits on OMAP5 as against 8 bits on OMAP4, with the master NIU connID encoded in the 6 MSBs of the STDERRLOG_MSTADDR field. 2. The CLK3 FlagMux component has 1 input source on OMAP4 and 3 input sources on OMAP5. The common DEBUGSS source is at a different input on each SoC. Fix the above issues by using a OMAP5-specific compatible property and using SoC-specific data where there are differences. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | bus: omap_l3_noc: Fix offset for DRA7 CLK1_HOST_CLK1_2 instanceIllia Smyrnov2015-05-041-1/+1
|/ | | | | | | | | | | | | The base address for DRA7 CLK1_HOST_CLK1_2 host instance is 0x44800000, so correct offset is 0x800000. DRA7 TRM rev X(fewb 2015) has updates for this information. With wrong offset these errors are not correctly cleared by the L3 IRQ handler and cause an continuous interrupt scenario and system lockup. Signed-off-by: Illia Smyrnov <illia.smyrnov@globallogic.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2015-04-224-255/+410
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Driver updates for v4.1. Some of these are for drivers/soc, where we find more and more SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. The larger parts of this branch are: - MediaTek support for their PMIC wrapper interface, a high-level interface for talking to the system PMIC over a dedicated I2C interface. - Qualcomm SCM driver has been moved to drivers/firmware. It's used for CPU up/down and needs to be in a shared location for arm/arm64 common code. - cleanup of ARM-CCI PMU code. - another set of cleanusp to the OMAP GPMC code" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits) soc/mediatek: Remove unused variables clocksource: atmel-st: select MFD_SYSCON soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs arm-cci: Fix CCI PMU event validation arm-cci: Split the code for PMU vs driver support arm-cci: Get rid of secure transactions for PMU driver arm-cci: Abstract the CCI400 PMU specific definitions arm-cci: Rearrange code for splitting PMU vs driver code drivers: cci: reject groups spanning multiple HW PMUs ARM: at91: remove useless include clocksource: atmel-st: remove mach/hardware dependency clocksource: atmel-st: use syscon/regmap ARM: at91: time: move the system timer driver to drivers/clocksource ARM: at91: properly initialize timer ARM: at91: at91rm9200: remove deprecated arm_pm_restart watchdog: at91rm9200: implement restart handler watchdog: at91rm9200: use the system timer syscon mfd: syscon: Add atmel system timer registers definition ARM: at91/dt: declare atmel,at91rm9200-st as a syscon soc: qcom: gsbi: Add support for ADM CRCI muxing ...
| * Merge tag 'arm-perf-4.1' of ↵Olof Johansson2015-04-032-230/+313
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/drivers Merge "arm-cci PMU updates for 4.1" from Will Deacon: CCI-400 PMU updates This series reworks some of the CCI-400 PMU code so that it can be used on both ARM and ARM64-based systems, without the need to boot in secure mode on the latter. This paves the way for CCI-500 support in future. * tag 'arm-perf-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux: arm-cci: Fix CCI PMU event validation arm-cci: Split the code for PMU vs driver support arm-cci: Get rid of secure transactions for PMU driver arm-cci: Abstract the CCI400 PMU specific definitions arm-cci: Rearrange code for splitting PMU vs driver code drivers: cci: reject groups spanning multiple HW PMUs + Linux 4.0-rc4 Signed-off-by: Olof Johansson <olof@lixom.net>
| | * arm-cci: Fix CCI PMU event validationSuzuki K. Poulose2015-03-271-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We mask the event with the CCI_PMU_EVENT_MASK, before passing the config to pmu_validate_hw_event(), which causes extra bits to be ignored and qualifies an invalid event code as valid. e.g, $ perf stat -a -C 0 -e CCI_400/config=0x1ff,name=cycles/ sleep 1 Performance counter stats for 'system wide': 506951142 cycles 1.013879626 seconds time elapsed where, cycles has an event coding of 0xff. This patch also removes the unnecessary 'event' mask in pmu_write_register, since the config_base is set by the pmu code after the event is validated. Acked-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * arm-cci: Split the code for PMU vs driver supportSuzuki K. Poulose2015-03-272-8/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch separates the PMU driver code from the low level CCI driver code and enables the PMU driver for ARM64. Introduces config options for both. ARM_CCI400_PORT_CTRL - controls the low level driver code for CCI400 ports. ARM_CCI400_PMU - controls the PMU driver code ARM_CCI400_COMMON - Common defintions for CCI400 This patch also changes: ARM_CCI - common code for probing the CCI devices. This can be used for adding support for newer CCI versions(e.g, CCI-500). Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Punit Agrawal <punit.agrawal@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * arm-cci: Get rid of secure transactions for PMU driverSuzuki K. Poulose2015-03-271-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid secure transactions while probing the CCI PMU. The existing code makes use of the Peripheral ID2 (PID2) register to determine the revision of the CCI400, which requires a secure transaction. This puts a limitation on the usage of the driver on systems running non-secure Linux(e.g, ARM64). Updated the device-tree binding for cci pmu node to add the explicit revision number for the compatible field. The supported strings are : arm,cci-400-pmu,r0 arm,cci-400-pmu,r1 arm,cci-400-pmu - DEPRECATED. See NOTE below NOTE: If the revision is not mentioned, we need to probe the cci revision, which could be fatal on a platform running non-secure. We need a reliable way to know if we can poke the CCI registers at runtime on ARM32. We depend on 'mcpm_is_available()' when it is available. mcpm_is_available() returns true only when there is a registered driver for mcpm. Otherwise, we assume that we don't have secure access, and skips probing the revision number(ARM64 case). The MCPM should figure out if it is safe to access the CCI. Unfortunately there isn't a reliable way to indicate the same via dtb. This patch doesn't address/change the current situation. It only deals with the CCI-PMU, leaving the assumptions about the secure access as it has been, prior to this patch. Cc: devicetree@vger.kernel.org Cc: Punit Agrawal <punit.agrawal@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * arm-cci: Abstract the CCI400 PMU specific definitionsSuzuki K. Poulose2015-03-271-60/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CCI400 has different event specifications for PMU, for revsion 0 and revision 1. As of now, we check the revision every single time before using the parameters for the PMU. This patch abstracts the details of the pmu models in a struct (cci_pmu_model) and stores the information in cci_pmu at initialisation time, avoiding multiple probe operations. Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * arm-cci: Rearrange code for splitting PMU vs driver codeSuzuki K. Poulose2015-03-271-163/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional changes, only code re-arrangements for easier split of the PMU code vs low level driver code. Extracts the port handling code to cci_probe_ports(). Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * drivers: cci: reject groups spanning multiple HW PMUsSuzuki K. Poulose2015-03-271-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The perf core implicitly rejects events spanning multiple HW PMUs, as in these cases the event->ctx will differ. However this validation is performed after pmu::event_init() is called in perf_init_event(), and thus pmu::event_init() may be called with a group leader from a different HW PMU. The CCI PMU driver does not take this fact into account, and assumes that the any other hardware event belongs to the CCI. There are two issues with it : 1) It is wrong and we should reject such groups. 2) Validation allocates an temporary idx for this non-cci event, which leads to wrong calculation of the counter availability, and eventually lesser number of events in the group. This patch updates the CCI PMU driver to first test for and reject events from other PMUs, which is the right thing to do. Cc: Will Deacon <will.deacon@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Peter Ziljstra (Intel) <peterz@infradead.org> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | drivers: bus: Add Simple Power-Managed Bus DriverGeert Uytterhoeven2015-02-243-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver for transparent busses that don't need a real driver, but where the bus controller is part of a PM domain, or under the control of a functional clock. Typically, the bus controller's PM domain and/or clock must be enabled for child devices connected to the bus (either on-SoC or externally) to function. Hence the sole purpose of this driver is to enable its clock and PM domain (if exist(s)), which are specified in the DT and managed from platform and PM domain code, and to probe for child devices. Due to the child-parent relationship with devices connected to the bus, PM domain and clock state transitions are handled in the correct order. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | drivers: bus: Sort Makefile entries alphabeticallyGeert Uytterhoeven2015-02-241-7/+7
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | drivers: bus: Sort Kconfig entries alphabeticallyGeert Uytterhoeven2015-02-241-22/+22
| |/ | | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | Merge tag 'armsoc-soc' of ↵Linus Torvalds2015-04-221-6/+7
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "Our SoC branch usually contains expanded support for new SoCs and other core platform code. In this case, that includes: - support for the new Annapurna Labs "Alpine" platform - a rework greatly simplifying adding new platform support to the MCPM subsystem (Multi-cluster power management) - cpuidle and PM improvements for Exynos3250 - misc updates for Renesas, OMAP, Meson, i.MX. Some of these could have gone in other branches but ended up here for various reasons" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits) ARM: alpine: add support for generic pci ARM: Exynos: migrate DCSCB to the new MCPM backend abstraction ARM: vexpress: migrate DCSCB to the new MCPM backend abstraction ARM: vexpress: DCSCB: tighten CPU validity assertion ARM: vexpress: migrate TC2 to the new MCPM backend abstraction ARM: MCPM: move the algorithmic complexity to the core code ARM: EXYNOS: allow cpuidle driver usage on Exynos3250 SoC ARM: EXYNOS: add AFTR mode support for Exynos3250 ARM: EXYNOS: add code for setting/clearing boot flag ARM: EXYNOS: fix CPU1 hotplug on Exynos3250 ARM: S3C64XX: Use fixed IRQ bases to avoid conflicts on Cragganmore ARM: cygnus: fix const declaration bcm_cygnus_dt_compat ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4 ARM: DRA7: hwmod: Add data for GPTimers 13 through 16 ARM: EXYNOS: Remove left over 'extra_save' ARM: EXYNOS: Constify exynos_pm_data array ARM: EXYNOS: use static in suspend.c ARM: EXYNOS: Use platform device name as power domain name ARM: EXYNOS: add support for async-bridge clocks for pm_domains ARM: omap-device: add missed callback for suspend-to-disk ...
| * | bus: imx-weim: improve error handling upon child probe-failureAlison Chaiken2015-03-021-6/+7
| |/ | | | | | | | | | | | | | | | | Probe all children of the WEIM node, reporting any failures. Report failure from parsing of WEIM node itself if probes of all children fail. Signed-off-by: Alison Chaiken <alison_chaiken@mentor.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge tag 'armsoc-fixes' of ↵Linus Torvalds2015-04-221-0/+34
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "Here's the usual "low-priority fixes that didn't make it into the last few -rcs, with a twist: We had a fixes pull request that I didn't send in time to get into 4.0, so we'll send some of them to Greg for -stable as well. Contents here is as usual not all that controversial: - a handful of randconfig fixes from Arnd, in particular for older Samsung platforms - Exynos fixes, !SMP building, DTS updates for MMC and lid switch - Kbuild fix to create output subdirectory for DTB files - misc minor fixes for OMAP" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits) ARM: at91/dt: sama5d3 xplained: add phy address for macb1 kbuild: Create directory for target DTB ARM: mvebu: Disable CPU Idle on Armada 38x ARM: DRA7: Enable Cortex A15 errata 798181 ARM: dts: am57xx-beagle-x15: Add thermal map to include fan and tmp102 ARM: dts: DRA7: Add bandgap and related thermal nodes bus: ocp2scp: SYNC2 value should be changed to 0x6 ARM: dts: am4372: Add "ti,am437x-ocp2scp" as compatible string for OCP2SCP ARM: OMAP2+: remove superfluous NULL pointer check ARM: EXYNOS: Fix build breakage cpuidle on !SMP ARM: dts: fix lid and power pin-functions for exynos5250-spring ARM: dts: fix mmc node updates for exynos5250-spring ARM: OMAP4: remove dead kconfig option OMAP4_ERRATA_I688 MAINTAINERS: add OMAP defconfigs under OMAP SUPPORT ARM: OMAP1: PM: fix some build warnings on 1510-only Kconfigs ARM: cns3xxx: don't export static symbol ARM: S3C24XX: avoid a Kconfig warning ARM: S3C24XX: fix header file inclusions ARM: S3C24XX: fix building without PM_SLEEP ARM: S3C24XX: use SAMSUNG_WAKEMASK for s3c2416 ...
| * | bus: ocp2scp: SYNC2 value should be changed to 0x6Kishon Vijay Abraham I2015-03-261-0/+34
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the TRMs of AM572x, OMAP4430, OMAP4460, OMAP543x, the value of SYNC2 must be set to 0x6 in order to ensure correct operation. So modified the SYNC2 value of OCP2SCP TIMING register to 0x6 in all the platforms that use OCP2SCP driver except AM437x. Also introduced a new compatible property since we don't want to modify the OCP2SCP TIMING register for AM437x. The sections in TRM where the above caution can be found is mentioned below. AM572x TRM SPRUHZ6 (http://www.ti.com/lit/ug/spruhz6/spruhz6.pdf) under section 26.3.2.2, table 26-26. OMAP4430 TRM SWPU231AP (http://www.ti.com/lit/ug/swpu231ap/swpu231ap.pdf) under section 23.12.6.2.2 , Table 23-1213. OMAP4460 TRM SWPU235AB (http://www.ti.com/lit/ug/swpu235ab/swpu235ab.pdf) under section 23.12.6.2.2, Table 23-1213. OMAP543x TRM SWPU249 (http://www.ti.com/lit/pdf/swpu249) under section 27.3.2.2, Table 27-27. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-04-173-0/+730
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS for Linux 4.1. Most noteworthy: - Add more Octeon-optimized crypto functions - Octeon crypto preemption and locking fixes - Little endian support for Octeon - Use correct CSR to soft reset Octeons - Support LEDs on the Octeon-based DSR-1000N - Fix PCI interrupt mapping for the Octeon-based DSR-1000N - Mark prom_free_prom_memory() as __init for a number of systems - Support for Imagination's Pistachio SOC. This includes arch and CLK bits. I'd like to merge pinctrl bits later - Improve parallelism of csum_partial for certain pipelines - Organize DTB files in subdirs like other architectures - Implement read_sched_clock for all MIPS platforms other than Octeon - Massive series of 38 fixes and cleanups for the FPU emulator / kernel - Further FPU remulator work to support new features. This sits on a separate branch which also has been pulled into the 4.1 KVM branch - Clean up and fixes for the SEAD3 eval board; remove unused file - Various updates for Netlogic platforms - A number of small updates for Loongson 3 platforms - Increase the memory limit for ATH79 platforms to 256MB - A fair number of fixes and updates for BCM47xx platforms - Finish the implementation of XPA support - MIPS FDC support. No, not floppy controller but Fast Debug Channel :) - Detect the R16000 used in SGI legacy platforms - Fix Kconfig dependencies for the SSB bus support" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits) MIPS: Makefile: Fix MIPS ASE detection code MIPS: asm: elf: Set O32 default FPU flags MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G MIPS: Kconfig: Disable SMP/CPS for 64-bit MIPS: Hibernate: flush TLB entries earlier MIPS: smp-cps: cpu_set FPU mask if FPU present MIPS: lose_fpu(): Disable FPU when MSA enabled MIPS: ralink: add missing symbol for RALINK_ILL_ACC MIPS: ralink: Fix bad config symbol in PCI makefile. SSB: fix Kconfig dependencies MIPS: Malta: Detect and fix bad memsize values Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores." MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard. MIPS: Fix cpu_has_mips_r2_exec_hazard. MIPS: kernel: entry.S: Set correct ISA level for mips_ihb MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter MIPS: unaligned: Fix regular load/store instruction emulation for EVA MIPS: unaligned: Surround load/store macros in do {} while statements ...
| * | MIPS: Add CDMM bus supportJames Hogan2015-03-313-0/+730
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MIPS Common Device Memory Map (CDMM) support in the form of a bus in the standard Linux device model. Each device attached via CDMM is discoverable via an 8-bit type identifier and may contain a number of blocks of memory mapped registers in the CDMM region. IRQs are expected to be handled separately. Due to the per-cpu (per-VPE for MT cores) nature of the CDMM devices, all the driver callbacks take place from workqueues which are run on the right CPU for the device in question, so that the driver doesn't need to be as concerned about which CPU it is running on. Callbacks also exist for when CPUs are taken offline, so that any per-CPU resources used by the driver can be disabled so they don't get forcefully migrated. CDMM devices are created as children of the CPU device they are attached to. Any existing CDMM configuration by the bootloader will be inherited, however platforms wishing to enable CDMM should implement the weak mips_cdmm_phys_base() function (see asm/cdmm.h) so that the bus driver knows where it should put the CDMM region in the physical address space if the bootloader hasn't already enabled it. A mips_cdmm_early_probe() function is also provided to allow early boot or particularly low level code to set up the CDMM region and probe for a specific device type, for example early console or KGDB IO drivers for the EJTAG Fast Debug Channel (FDC) CDMM device. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9599/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* / genirq: Remove the deprecated 'IRQF_DISABLED' request_irq() flag entirelyValentin Rothberg2015-03-052-8/+6
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IRQF_DISABLED flag is a NOOP and has been scheduled for removal since Linux v2.6.36 by commit 6932bf37bed4 ("genirq: Remove IRQF_DISABLED from core code"). According to commit e58aa3d2d0cc ("genirq: Run irq handlers with interrupts disabled"), running IRQ handlers with interrupts enabled can cause stack overflows when the interrupt line of the issuing device is still active. This patch ends the grace period for IRQF_DISABLED (i.e., SA_INTERRUPT in older versions of Linux) and removes the definition and all remaining usages of this flag. There's still a few non-functional references left in the kernel source: - The bigger hunk in Documentation/scsi/ncr53c8xx.txt is removed entirely as IRQF_DISABLED is gone now; the usage in older kernel versions (including the old SA_INTERRUPT flag) should be discouraged. The trouble of using IRQF_SHARED is a general problem and not specific to any driver. - I left the reference in Documentation/PCI/MSI-HOWTO.txt untouched since it has already been removed in linux-next. - All remaining references are changelogs that I suggest to keep. Signed-off-by: Valentin Rothberg <valentinrothberg@gmail.com> Cc: Afzal Mohammed <afzal@ti.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Dan Carpenter <dan.carpenter@oracle.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Ewan Milne <emilne@redhat.com> Cc: Eyal Perry <eyalpe@mellanox.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Hannes Reinecke <hare@suse.de> Cc: Hongliang Tao <taohl@lemote.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Keerthy <j-keerthy@ti.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Nishanth Menon <nm@ti.com> Cc: Paul Bolle <pebolle@tiscali.nl> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Quentin Lambert <lambert.quentin@gmail.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Sricharan R <r.sricharan@ti.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Lindgren <tony@atomide.com> Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: iss_storagedev@hp.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Link: http://lkml.kernel.org/r/1425565425-12604-1-git-send-email-valentinrothberg@gmail.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
* Merge tag 'soc-for-linus' of ↵Linus Torvalds2015-02-171-67/+219
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "New and updated SoC support. Also included are some cleanups where the platform maintainers hadn't separated cleanups from new developent in separate branches. Some of the larger things worth pointing out: - A large set of changes from Alexandre Belloni and Nicolas Ferre preparing at91 platforms for multiplatform and cleaning up quite a bit in the process. - Removal of CSR's "Marco" SoC platform that never made it out to the market. We love seeing these since it means the vendor published support before product was out, which is exactly what we want! New platforms this release are: - Conexant Digicolor (CX92755 SoC) - Hisilicon HiP01 SoC - CSR/sirf Atlas7 SoC - ST STiH418 SoC - Common code changes for Nvidia Tegra132 (64-bit SoC) We're seeing more and more platforms having a harder time labelling changes as cleanups vs new development -- which is a good sign that we've come quite far on the cleanup effort. So over time we might start combining the cleanup and new-development branches more" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (124 commits) ARM: at91/trivial: unify functions and machine names ARM: at91: remove at91_dt_initialize and machine init_early() ARM: at91: change board files into SoC files ARM: at91: remove at91_boot_soc ARM: at91: move alternative initial mapping to board-dt-sama5.c ARM: at91: merge all SOC_AT91SAM9xxx ARM: at91: at91rm9200: set idle and restart from rm9200_dt_device_init() ARM: digicolor: select syscon and timer ARM: zynq: Simplify SLCR initialization ARM: zynq: PM: Fixed simple typo. ARM: zynq: Setup default gpio number for Xilinx Zynq ARM: digicolor: add low level debug support ARM: initial support for Conexant Digicolor CX92755 SoC ARM: OMAP2+: Add dm816x hwmod support ARM: OMAP2+: Add clock domain support for dm816x ARM: OMAP2+: Add board-generic.c entry for ti81xx ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage ARM: at91: remove unused mach/system_rev.h ARM: at91: stop using HAVE_AT91_DBGUx ARM: at91: fix ordering of SRAM and PM initialization ...
| * bus: mvebu-mbus: make sure SDRAM CS for DMA don't overlap the MBus bridge windowThomas Petazzoni2015-01-191-16/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mvebu-mbus driver reads the SDRAM window registers, and make the information about the DRAM CS configuration available to device drivers using the mv_mbus_dram_info() API. This information is used by the DMA-capable device drivers to program their address decoding windows. Until now, we were basically providing the SDRAM window register details as is. However, it turns out that the DMA capability of the CESA cryptographic engine consists in doing DMA being the DRAM and the crypto SRAM mapped as a MBus window. For this case, it is very important that the SDRAM CS information does not overlap with the MBus bridge window. Therefore, this commit improves the mvebu-mbus driver to make sure we adjust the SDRAM CS information so that it doesn't overlap with the MBus bridge window. This problem was reported by Boris Brezillon, while working on the mv_cesa driver for Armada 37x/38x/XP. We use the memblock memory information to know where the usable RAM is located, as this information is guaranteed to be correct on all SoC variants. We could have used the MBus bridge window registers on Armada 370/XP, but they are not really used on Armada 375/38x (Cortex-A9 based), since the PL310 L2 filtering is used instead to discriminate between RAM accesses and I/O accesses. Therefore, using the memblock information is more generic and works accross the different platforms. Reported-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [Andrew Lunn <andrew@lunn.ch>: Fixed merge conflict] Signed-off-by: Andrew Lunn <andrew@lunn.ch>
| * bus: mvebu-mbus: fix support of MBus window 13 on Armada XP/375/38xMichal Mazur2015-01-191-48/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Armada XP, 375 and 38x the MBus window 13 has the remap capability, like windows 0 to 7. However, the mvebu-mbus driver isn't currently taking into account this special case, which means that when window 13 is actually used, the remap registers are left to 0, making the device using this MBus window unavailable. To make things even more fun, the hardware designers have chosen to put the window 13 remap registers in a completely custom location, using a logic that differs from the one used for all other remappable windows. To solve this problem, this commit: * Adds a SoC specific function to calculate offset of remap registers to the mvebu_mbus_soc_data structure. This function, ->win_remap_offset(), returns the offset of the remap registers, or MVEBU_MBUS_NO_REMAP if the window does not have the remap capability. This new function replaces the previous integer field num_remappable_wins, which was insufficient to encode the special case of window 13. * Adds an implementation of the ->win_remap_offset() function for the various SoC families. Some have 2 first windows that are remapable, some the 4 first, some the 8 first, and then the Armada XP/375/38x case where the 8 first are remapable plus the special window 13. This is implemented in functions generic_mbus_win_remap_2_offset(), generic_mbus_win_remap_4_offset(), generic_mbus_win_remap_8_offset() and armada_xp_mbus_win_remap_offset() respectively. * Change the code to use the ->win_remap_offset() function when accessing the remap registers, and also to use a newly introduced mvebu_mbus_window_is_remappable() helper function that tells whether a given window is remapable or not. * Separate Armada 370 from XP/375/38X because the window 13 of Armada 370 does not support the remap capability. [Thomas: adapted for the mainline kernel, minor clarifications in the code, reword the commit log.] Signed-off-by: Michal Mazur <arg@semihalf.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [Andrew Lunn <andrew@lunn.ch>: Undo the simple fix for stable] Signed-off-by: Andrew Lunn <andrew@lunn.ch>
| * bus: mvebu-mbus: use automatic I/O synchronization barriersThomas Petazzoni2015-01-191-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using explicit I/O synchronization barriers shoehorned inside the streaming DMA mappings API (in arch/arm/mach-mvebu/coherency.c), we are switching to use automatic I/O synchronization barrier. The primary motivation for this change is that explicit I/O synchronization barriers are not only needed for streaming DMA mappings (which can easily be done by overriding the dma_map_ops), but also for coherent DMA mappings (which is a lot less easy to do, since the kernel assumes such mappings are coherent and don't require any sort of cache maintenance operation to ensure the consistency of the buffers). Switching to automatic I/O synchronization barriers will also allow us to use the existing arm_coherent_dma_ops instead of our custom arm_dma_ops. In order to use automatic I/O synchronization barriers, this commit changes mvebu-mbus in two ways: - It enables automatic I/O synchronization barriers in the 0x84 register of the MBus bridge, by enabling such barriers for all MBus units. This enables automatic barriers for the on-SoC peripherals that are doing DMA. - It enables the SyncEnable bit in the MBus windows, so that PCIe devices also use automatic I/O synchronization barrier. This automatic synchronization barrier relies on the assumption that at least one register of a given hardware unit is read before the driver accesses the DMA mappings modified by this unit. This assumption is guaranteed for PCI devices by vertue of the PCI standard, and we can reasonably verify that this assumption is also true for the limited number of platform drivers doing DMA used on Marvell EBU platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
* | arm: use %*pb[l] to print bitmaps including cpumasks and nodemasksTejun Heo2015-02-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | printk and friends can now format bitmaps using '%*pb[l]'. cpumask and nodemask also provide cpumask_pr_args() and nodemask_pr_args() respectively which can be used to generate the two printf arguments necessary to format the specified cpu/nodemask. * Line termination only requires one extra space at the end of the buffer. Use PAGE_SIZE - 1 instead of PAGE_SIZE - 2 when formatting. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge tag 'mvebu-fixes-3.19-4' of git://git.infradead.org/linux-mvebu into fixesOlof Johansson2015-01-231-0/+13
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | Merge "mvebu/fixes #3" from Andrew Lunn: mvebu fixes for 3.19. (Part 4) bus: mvebu-mbus: fix support of MBus window 13 * tag 'mvebu-fixes-3.19-4' of git://git.infradead.org/linux-mvebu: bus: mvebu-mbus: fix support of MBus window 13 ARM: mvebu: completely disable hardware I/O coherency Signed-off-by: Olof Johansson <olof@lixom.net>
| * bus: mvebu-mbus: fix support of MBus window 13Andrew Lunn2015-01-191-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Armada XP, 375 and 38x the MBus window 13 has the remap capability, like windows 0 to 7. However, the mvebu-mbus driver isn't currently taking into account this special case, which means that when window 13 is actually used, the remap registers are left to 0, making the device using this MBus window unavailable. As a minimal fix for stable, don't use window 13. A full fix will follow later. Fixes: fddddb52a6c ("bus: introduce an Marvell EBU MBus driver") Cc: <stable@vger.kernel.org> # v3.10+ Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
* | drivers: bus: check cci device tree node statusAbhilash Kesavan2015-01-161-0/+3
|/ | | | | | | | | | | | | The arm-cci driver completes the probe sequence even if the cci node is marked as disabled. Add a check in the driver to honour the cci status in the device tree. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* Merge tag 'driver-core-3.19-rc1' of ↵Linus Torvalds2014-12-144-4/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
| * bus: drop owner assignment from platform_driversWolfram Sang2014-10-204-4/+0
| | | | | | | | | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* | Merge tag 'drivers-for-linus' of ↵Linus Torvalds2014-12-094-135/+612
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "These are changes for drivers that are intimately tied to some SoC and for some reason could not get merged through the respective subsystem maintainer tree. The largest single change here this time around is the Tegra iommu/memory controller driver, which gets updated to the new iommu DT binding. More drivers like this are likely to follow for the following merge window, but we should be able to do those through the iommu maintainer. Other notable changes are: - reset controller drivers from the reset maintainer (socfpga, sti, berlin) - fixes for the keystone navigator driver merged last time - at91 rtc driver changes related to the at91 cleanups - ARM perf driver changes from Will Deacon - updates for the brcmstb_gisb driver" * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits) clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers clocksource: arch_timer: Fix code to use physical timers when requested memory: Add NVIDIA Tegra memory controller support bus: brcmstb_gisb: Add register offset tables for older chips bus: brcmstb_gisb: Look up register offsets in a table bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses bus: brcmstb_gisb: Make the driver buildable on MIPS of: Add NVIDIA Tegra memory controller binding ARM: tegra: Move AHB Kconfig to drivers/amba amba: Add Kconfig file clk: tegra: Implement memory-controller clock serial: samsung: Fix serial config dependencies for exynos7 bus: brcmstb_gisb: resolve section mismatch ARM: common: edma: edma_pm_resume may be unused ARM: common: edma: add suspend resume hook powerpc/iommu: Rename iommu_[un]map_sg functions rtc: at91sam9: add DT bindings documentation rtc: at91sam9: use clk API instead of relying on AT91_SLOW_CLOCK ARM: at91: add clk_lookup entry for RTT devices rtc: at91sam9: rework the Kconfig description ...
| * \ Merge branch 'brcm/stb-smp-uart' into next/driversArnd Bergmann2014-12-081-6/+41
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This resolves a nonobvious merge conflict that I got wrong the first time. * brcm/stb-smp-uart: bus: brcmstb_gisb: save and restore GISB timeout bus: brcmstb_gisb: register the fault code hook ARM: brcmstb: Kconfig: drop unneeded symbol selections ARM: brcmstb: reintroduce SMP support ARM: brcmstb: add debug UART for earlyprintk support Conflicts: drivers/bus/brcmstb_gisb.c Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reported-by: Florian Fainelli <f.fainelli@gmail.com>
| * \ \ Merge tag 'arm-soc/for-3.19/brcmstb-drivers' of ↵Arnd Bergmann2014-12-042-20/+100
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/brcm/linux into next/drivers This pull request contains the following changes to the Broadcom GISB bus arbiter from Kevin Cernekee: - Extend brcmstb GISB bus driver to work on MIPS (currently ARM-only) and support 65nm and 40nm MIPS-based chips such as: BCM7038, BCM7400 and BCM7435 * tag 'arm-soc/for-3.19/brcmstb-drivers' of https://github.com/brcm/linux: bus: brcmstb_gisb: Add register offset tables for older chips bus: brcmstb_gisb: Look up register offsets in a table bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses bus: brcmstb_gisb: Make the driver buildable on MIPS Conflicts: drivers/bus/brcmstb_gisb.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | | bus: brcmstb_gisb: Add register offset tables for older chipsKevin Cernekee2014-11-281-6/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will select the appropriate register layout based on the DT "compatible" string. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * | | bus: brcmstb_gisb: Look up register offsets in a tableKevin Cernekee2014-11-281-8/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are at least 4 incompatible variations of this hardware block, so let's use the ARB_* constants as a table index instead of hardcoding specific register offsets. Also, allow for the possibility of adding old devices that are missing some of the registers. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * | | bus: brcmstb_gisb: Introduce wrapper functions for MMIO accessesKevin Cernekee2014-11-281-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These will be used to abstract out chip-to-chip differences. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * | | bus: brcmstb_gisb: Make the driver buildable on MIPSKevin Cernekee2014-11-282-1/+5
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BCM7xxx ARM and MIPS platforms share a similar hardware block for reporting GISB errors, so they both benefit from the use of this driver. Conditionally compile the ARM-specific bus error handler so that the GISB error IRQ handler works on other architectures. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | bus: brcmstb_gisb: resolve section mismatchFlorian Fainelli2014-11-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f1bee783dd37 moved the call to hook_fault_code in brcmstb_gisb_arb_probe() which now calls a function annotated with __init, so this one must also be annotated with __init. In order to avoid introducing another section mismatch, call platform_driver_probe() manually and remove the .probe assignment from brcmstb_gisb_arb_driver, this is very similar to what drivers/pci/host/pci-imx6.c does since we basically have the same constraints here. Fixes: f1bee783dd37 ("bus: brcmstb_gisb: register the fault code hook") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | Merge tag 'arm-perf-3.19' of ↵Arnd Bergmann2014-11-201-108/+444
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/drivers Pull "ARM: perf: updates for 3.19" from Will Deacon: This patch series takes us slightly further on the road to big.LITTLE support in perf. The main change enabling this is moving the CCI PMU driver away from the arm-pmu abstraction, allowing the arch code to focus specifically on support for CPU PMUs. * tag 'arm-perf-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux: arm: perf: fold hotplug notifier into arm_pmu arm: perf: dynamically allocate cpu hardware data arm: perf: fold percpu_pmu into pmu_hw_events arm: perf: kill get_hw_events() arm: perf: limit size of accounting data arm: perf: use IDR types for CPU PMUs arm: perf: make PMU probing data-driven arm: perf: add missing pr_info newlines arm: perf: factor out callchain code ARM: perf: use pr_* instead of printk ARM: perf: remove useless return and check of idx in counter handling bus: cci: move away from arm_pmu framework Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | | bus: cci: move away from arm_pmu frameworkMark Rutland2014-10-301-108/+444
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM CPU PMUs and the ARM CCI PMU are using the same framework despite being substantially different in programming model, which makes it difficult to handle either particularly well. This patch migrates the ARM CCI PMU driver away from the arm_pmu framework, matching the style of the CCN PMU driver and other 'uncore' PMU drivers. This will enable refactoring of the arm_pmu framework to better support CPU PMUs. Event context migration on hotplug is not yet added due to a race on event->ctx in the core perf code. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Punit Agrawal <punit.agrawal@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Will Deacon <will.deacon@arm.com> [will: fix whitespace issues] Signed-off-by: Will Deacon <will.deacon@arm.com>
| * | | bus: omap_l3_noc: Correct returning IRQ_HANDLED unconditionally in the irq ↵Keerthy2014-11-121-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | handler Correct returning IRQ_HANDLED unconditionally in the irq handler. Return IRQ_NONE for some interrupt which we do not expect to be handled in this handler. This prevents kernel stalling with back to back spurious interrupts. Fixes: 2722e56de6 ("OMAP4: l3: Introduce l3-interconnect error handling driver") Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | bus: omap_l3_noc: Add resume hook to restore contextKeerthy2014-11-121-0/+55
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On certain SoCs such as AM437x SoC, L3_noc error registers are maintained in power domain such as per domain which looses context as part of low power state such as RTC+DDR mode. On these platforms when we mask interrupts which we cannot handle, the source of these interrupts still remain on resume, however, the flag mux registers now contain their reset value (unmasked) - this breaks the system with infinite interrupts since we do not these interrupts to take place ever again. To handle this: restore the masking of interrupts which we have already recorded in the system as ones we cannot handle. Fixes: 2100b595b7 ("bus: omap_l3_noc: ignore masked out unclearable targets") Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | Merge tag 'soc-for-linus' of ↵Linus Torvalds2014-12-092-10/+215
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Arnd Bergmann: "New and updated SoC support, notable changes include: - bcm: brcmstb SMP support initial iproc/cygnus support - exynos: Exynos4415 SoC support PMU and suspend support for Exynos5420 PMU support for Exynos3250 pm related maintenance - imx: new LS1021A SoC support vybrid 610 global timer support - integrator: convert to using multiplatform configuration - mediatek: earlyprintk support for mt8127/mt8135 - meson: meson8 soc and l2 cache controller support - mvebu: Armada 38x CPU hotplug support drop support for prerelease Armada 375 Z1 stepping extended suspend support, now works on Armada 370/XP - omap: hwmod related maintenance prcm cleanup - pxa: initial pxa27x DT handling - rockchip: SMP support for rk3288 add cpu frequency scaling support - shmobile: r8a7740 power domain support various small restart, timer, pci apmu changes - sunxi: Allwinner A80 (sun9i) earlyprintk support - ux500: power domain support Overall, a significant chunk of changes, coming mostly from the usual suspects: omap, shmobile, samsung and mvebu, all of which already contain a lot of platform specific code in arch/arm" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits) ARM: mvebu: use the cpufreq-dt platform_data for independent clocks soc: integrator: Add terminating entry for integrator_cm_match ARM: mvebu: add SDRAM controller description for Armada XP ARM: mvebu: adjust mbus controller description on Armada 370/XP ARM: mvebu: add suspend/resume DT information for Armada XP GP ARM: mvebu: synchronize secondary CPU clocks on resume ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume ARM: mvebu: Armada XP GP specific suspend/resume code ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume ARM: mvebu: implement suspend/resume support for Armada XP clk: mvebu: add suspend/resume for gatable clocks bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration bus: mvebu-mbus: suspend/resume support clocksource: time-armada-370-xp: add suspend/resume support irqchip: armada-370-xp: Add suspend/resume support ARM: add lolevel debug support for asm9260 ARM: add mach-asm9260 ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf power: reset: imx-snvs-poweroff: add power off driver for i.mx6 ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A ...
| * \ \ Merge tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu ↵Arnd Bergmann2014-12-041-4/+176
| |\ \ \ | | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/soc Pull "mvebu SoC suspend changes for v3.19" from Jason Cooper: - Armada 370/XP suspend/resume support - mvebu SoC driver suspend/resume support - irqchip - clocksource - mbus - clk * tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu: ARM: mvebu: add SDRAM controller description for Armada XP ARM: mvebu: adjust mbus controller description on Armada 370/XP ARM: mvebu: add suspend/resume DT information for Armada XP GP ARM: mvebu: synchronize secondary CPU clocks on resume ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume ARM: mvebu: Armada XP GP specific suspend/resume code ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume ARM: mvebu: implement suspend/resume support for Armada XP clk: mvebu: add suspend/resume for gatable clocks bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration bus: mvebu-mbus: suspend/resume support clocksource: time-armada-370-xp: add suspend/resume support irqchip: armada-370-xp: Add suspend/resume support Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 03:56:17 +0000