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path: root/drivers/clk/clk-divider.c
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* clk: divider: fix incorrect usage of container_ofJerome Brunet2018-04-121-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | [ Upstream commit 12a26c298d2a8b1cab498533fa65198e49e3afd3 ] divider_recalc_rate() is an helper function used by clock divider of different types, so the structure containing the 'hw' pointer is not always a 'struct clk_divider' At the following line: > div = _get_div(table, val, flags, divider->width); in several cases, the value of 'divider->width' is garbage as the actual structure behind this memory is not a 'struct clk_divider' Fortunately, this width value is used by _get_val() only when CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so far when the structure is not a 'struct clk_divider'. This is probably why we did not notice this bug before Fixes: afe76c8fd030 ("clk: allow a clk divider with max divisor when zero") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: Don't write error code into divider registerAlex Frid2017-08-311-2/+4
| | | | | | | | | | | Add a check for error returned by divider value calculation to avoid writing error code into hw register. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Fixes: bca9690b9426 ("clk: divider: Make generic for usage elsewhere") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: divider: Make divider_round_rate take the parent clockMaxime Ripard2017-06-071-9/+10
| | | | | | | | | | | | | | | | | | | | So far, divider_round_rate only considers the parent clock returned by clk_hw_get_parent. This works fine on clocks that have a single parents, this doesn't work on muxes, since we will only consider the first parent, while other parents may totally be able to provide a better combination. Clocks in that case cannot use divider_round_rate, so would have to come up with a very similar logic to work around it. Instead of having to do something like this, and duplicate that logic everywhere, create a divider_round_rate parent to allow caller to give an additional parameter for the parent clock to consider. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* clk: divider: Fix clk_divider_round_rate() to use clk_readl()Geert Uytterhoeven2016-08-121-1/+1
| | | | | | | | | | | clk-divider uses clk_readl()/clk_writel() everywhere, except in clk_divider_round_rate(), where plain readl() is used. Change this to clk_readl(), as it makes a difference on powerpc. Fixes: e6d5e7d90be92cee ("clk-divider: Fix READ_ONLY when divider > 1") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: divider: Add hw based registration APIsStephen Boyd2016-04-191-8/+83
| | | | | | | | | Add registration APIs in the clk divider code to return struct clk_hw pointers instead of struct clk pointers. This way we hide the struct clk pointer from providers unless they need to use consumer facing APIs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: optimize the divider walk in clk_divider_bestdiv()Masahiro Yamada2016-01-291-3/+2
| | | | | | | | | Because _next_div() returns a valid divider, there is no need to consult _is_valid_div() for the validity of the divider in every iteration. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang2016-01-291-2/+0
| | | | | | | | | | to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definitions in the common clock framework to public header clk-provider.h, and drop the local definitions. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk-divider: make sure read-only dividers do not write to their registerHeiko Stuebner2016-01-291-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: divider: Cap table divider values to 'width' memberStephen Boyd2015-11-301-4/+5
| | | | | | | | | | | | | | | When we use a clk divider with a divider table, we limit the maximum divider value in divider_get_val() to the div_mask(width), but when we calculate the divider in divider_round_rate() we don't consider that the maximum divider may be limited by the width. Pass the width along to _get_table_maxdiv() so that we only return the maximum divider that is valid. This is useful for clocks that want to share the same divider table while limiting the available dividers to some subset of the table depending on the width of the bitfield. Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: divider: handle integer overflow when dividing large clock ratesBrian Norris2015-09-161-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | On 32-bit architectures, 'unsigned long' (the type used to hold clock rates, in Hz) is often only 32 bits wide. DIV_ROUND_UP() (as used in, e.g., commit b11d282dbea2 "clk: divider: fix rate calculation for fractional rates") can yield an integer overflow on clock rates that are not (by themselves) too large to fit in 32 bits, because it performs addition before the division. See for example: DIV_ROUND_UP(3000000000, 1500000000) = (3.0G + 1.5G - 1) / 1.5G = OVERFLOW / 1.5G This patch fixes such cases by always promoting the dividend to 64-bits (unsigned long long) before doing the division. While this patch does not resolve the issue with large clock rates across the common clock framework nor address the problems with doing full 64-bit arithmetic on a 32-bit architecture, it does fix some issues seen when using clock dividers on a 3GHz reference clock to produce a 1.5GHz CPU clock for an ARMv7 Brahma B15 SoC. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reference: http://lkml.kernel.org/g/20150413201433.GQ32500@ld-irv-0074 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: Convert basic types to clk_hw based provider APIsStephen Boyd2015-08-241-3/+3
| | | | | | | We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: Convert __clk_get_flags() to clk_hw_get_flags()Stephen Boyd2015-08-241-1/+1
| | | | | | | | | | | | | | | | | | | Mostly converted with the following snippet: @@ struct clk_hw *E; @@ -__clk_get_flags(E->clk) +clk_hw_get_flags(E) Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: basic-type: Silence warnings about lock imbalancesStephen Boyd2015-07-281-0/+4
| | | | | | | | | | | | | | | | The basic clock types use conditional locking for the register accessor spinlocks. Add __acquire() and __release() markings in the right locations so that sparse isn't tripped up on the conditional locking. drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic block Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: allow a clk divider with max divisor when zeroJim Quinlan2015-07-281-5/+11
| | | | | | | | | | | | | | | | | This commit allows certain Broadcom STB clock dividers to be used with clk-divider.c. It allows for a clock whose field value is the equal to the divisor, execpt when the field value is zero, in which case the divisor is 2^width. For example, consider a divisor clock with a two bit field: value divisor 0 4 1 1 2 2 3 3 Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: basic-types: Remove useless allocation failure printksStephen Boyd2015-05-141-4/+2
| | | | | | | Printing an error on kmalloc() failures is unnecessary. Remove the print and use *ptr in sizeof() for future-proof code. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: divider: fix calculation of initial best divider when rounding to closestUwe Kleine-König2015-03-091-6/+7
| | | | | | | | | | | | | | | | | | | | Similar to the reasoning for the previous commit DIV_ROUND_CLOSEST(parent_rate, rate) might not be the best integer divisor to get a good approximation for rate from parent_rate (given the metric for CLK_DIVIDER_ROUND_CLOSEST). For example assume a parent rate of 1000 Hz and a target rate of 700. Using DIV_ROUND_CLOSEST the suggested divisor gets calculated to 1 resulting in a target rate of 1000 with a delta of 300 to the desired rate. With choosing 2 as divisor however the resulting rate is 500 which is nearer to 700. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: divider: fix selection of divider when rounding to closestUwe Kleine-König2015-03-091-1/+5
| | | | | | | | | | | | | | | | | It's an invalid approach to assume that among two divider values the one nearer the exact divider is the better one. Assume a parent rate of 1000 Hz, a divider with CLK_DIVIDER_POWER_OF_TWO and a target rate of 89 Hz. The exact divider is ~ 11.236 so 8 and 16 are the candidates to choose from yielding rates 125 Hz and 62.5 Hz respectivly. While 8 is nearer to 11.236 than 16 is, the latter is still the better divider as 62.5 is nearer to 89 than 125 is. Fixes: 774b514390b1 (clk: divider: Add round to closest divider) Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: divider: fix calculation of maximal parent rate for a given dividerUwe Kleine-König2015-03-091-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The rate provided at the output of a clk-divider is calculated as: DIV_ROUND_UP(parent_rate, div) since commit b11d282dbea2 (clk: divider: fix rate calculation for fractional rates). So to yield a rate not bigger than r parent_rate must be <= r * div. The effect of choosing a parent rate that is too big as was done before this patch results in wrongly ruling out good dividers. Note that this is not a complete fix as __clk_round_rate might return a value >= its 2nd parameter. Also for dividers with CLK_DIVIDER_ROUND_CLOSEST set the calculation is not accurate. But this fixes the test case by Sascha Hauer that uses a chain of three dividers under a fixed clock. Fixes: b11d282dbea2 (clk: divider: fix rate calculation for fractional rates) Suggested-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: divider: return real rate instead of divider valueHeiko Stübner2015-03-061-1/+1
| | | | | | | | | | | | | Commit bca9690b9426 ("clk: divider: Make generic for usage elsewhere") returned only the divider value for read-only dividers instead of the actual rate. Fixes: bca9690b9426 ("clk: divider: Make generic for usage elsewhere") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: James Hogan <james.hogan@imgtec.com> Tested-by: James Hogan <james.hogan@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: divider: Make generic for usage elsewhereStephen Boyd2015-01-271-84/+128
| | | | | | | | | | Some devices don't use mmio to interact with dividers. Split out the logic from the register read/write parts so that we can reuse the division logic elsewhere. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: Add clk_unregister_{divider, gate, mux} to close memory leakKrzysztof Kozlowski2015-01-171-0/+16
| | | | | | | | | | | | The common clk_register_{divider,gate,mux} functions allocated memory for internal data which wasn't freed anywhere. Drivers using these helpers could only unregister clocks but the memory would still leak. Add corresponding unregister functions which will release all resources. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk-divider: Fix READ_ONLY when divider > 1James Hogan2014-11-171-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 79c6ab509558 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the recalc_rate() and round_rate() clock callbacks to be omitted. However using this flag has the unfortunate side effect of causing the clock recalculation code when a clock rate change is attempted to always treat it as a pass-through clock, i.e. with a fixed divide of 1, which may not be the case. Child clock rates are then recalculated using the wrong parent rate. Therefore instead of dropping the recalc_rate() and round_rate() callbacks, alter clk_divider_bestdiv() to always report the current divider as the best divider so that it is never altered. For me the read only clock was the system clock, which divided the PLL rate by 2, from which both the UART and the SPI clocks were divided. Initial setting of the UART rate set it correctly, but when the SPI clock was set, the other child clocks were miscalculated. The UART clock was recalculated using the PLL rate as the parent rate, resulting in a UART new_rate of double what it should be, and a UART which spewed forth garbage when the rate changes were propagated. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Max Schwarz <max.schwarz@online.de> Cc: <stable@vger.kernel.org> # v3.16+ Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: divider: Fix overflow in clk_divider_bestdivTomasz Figa2014-05-271-1/+1
| | | | | | | | | | | | | | | | | Commit c686078 ("clk: divider: Add round to closest divider") introduced a helper function to check whether given divisor is the best one instead of direct check. However due to int type used instead of unsigned long for passing calculated rates to this function in certain cases an overflow could occur, for example when trying to obtain maximum possible clock rate by calling clk_round_rate(..., UINT_MAX). This patch fixes this issue by changing the type of rate, now and best arguments of the function to unsigned long, which is the type that should be used for clock rates. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge branch 'clk-fixes' into clk-nextMike Turquette2014-05-231-1/+1
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| * clk: divider: Fix table round up functionMaxime COQUELIN2014-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1d9fe6b97 ("clk: divider: Fix best div calculation for power-of-two and table dividers") introduces a regression in its _table_round_up function. When the divider passed to this function is greater than the max divider available in the table, this function returns table's max divider. Problem is that it causes an infinite loop in clk_divider_bestdiv() because _next_div() will never return a value greater than maxdiv. Instead of returning table's max divider, this patch returns INT_MAX. Reported-by: Fabio Estevam <festevam@gmail.com> Reported-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <festevam@gmail.com> Tested-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: divider: add CLK_DIVIDER_READ_ONLY flagHeiko Stuebner2014-05-231-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Heiko Stuebner <heiko@sntech.de> Similar to muxes which already have a read-only flag there sometimes exist dividers which should not be changed by the clock framework but whose value still should be readable. Therefore add a READ_ONLY flag similar to the mux-one to clk-divider Signed-off-by: Heiko Stuebner <heiko@sntech.de> [changed flag bit to BIT(5) as suggested by Tomasz Figa] Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Max Schwarz <max.schwarz@online.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: divider: Optimize clk_divider_bestdiv loopMaxime COQUELIN2014-04-301-1/+13
| | | | | | | | | | | | | | | | | | | | | | Currently, the for-loop used to try all the different dividers to find the one that best fit tries all the values from 1 to max_div, incrementing by one. In case of power-of-two, or table based divider, the loop isn't optimal. Instead of incrementing by one, this patch provides directly the next divider. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | clk: divider: Add round to closest dividerMaxime COQUELIN2014-04-301-2/+67
|/ | | | | | | | | | | In some cases, we want to be able to round the divider to the closest one, instead than rounding up. This patch adds a new CLK_DIVIDER_ROUND_CLOSEST flag to specify the divider has to round to closest div, keeping rounding up as de default behaviour. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: divider: Fix best div calculation for power-of-two and table dividersMaxime COQUELIN2014-04-301-1/+36
| | | | | | | | | | | The divider returned by clk_divider_bestdiv() is likely to be invalid in case of power-of-two and table dividers when CLK_SET_RATE_PARENT flag isn't set. Fixes boot on STiH416 platform. Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: trivial merge conflict & updated changelog]
* clk: divider: fix rate calculation for fractional ratesTomi Valkeinen2014-02-261-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: clk-divider: fix divisor > 255 bugJames Hogan2014-01-081-1/+1
| | | | | | | | | | | | | | | | | | Commit 6d9252bd9a4bb (clk: Add support for power of two type dividers) merged in v3.6 added the _get_val function to convert a divisor value to a register field value depending on the flags. However it used the type u8 for the div field, causing divisors larger than 255 to be masked and the resultant clock rate to be too high. E.g. in my case an 11bit divider was supposed to divide 24.576 MHz down to 32.768KHz. The divisor was correctly calculated as 750 (0x2ee). This was masked to 238 (0xee) resulting in a frequency of 103.26KHz. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: wrap I/O access for improved portabilityGerhard Sittig2013-08-271-3/+3
| | | | | | | | | | | the common clock drivers were motivated/initiated by ARM development and apparently assume little endian peripherals wrap register/peripherals access in the common code (div, gate, mux) in preparation of adding COMMON_CLK support for other platforms Signed-off-by: Gerhard Sittig <gsi@denx.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: clk-divider: Export clk_register_divider()Fabio Estevam2013-08-161-0/+2
| | | | | | | | | | | clk_register_divider() needs to be exported so that it could be used in a module driver, otherwise we get the following error: ERROR: "clk_register_divider" [sound/soc/mxs/snd-soc-mxs.ko] undefined! Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: also export clk_register_divider_table]
* clk: divider: add CLK_DIVIDER_HIWORD_MASK flagHaojian Zhuang2013-06-151-2/+13
| | | | | | | | | | | | | | | In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: divider: do not propagate rate change request when unnecessaryShawn Guo2013-06-101-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the current rate of parent clock is sufficient to provide child a requested rate with a proper divider setting, the rate change request should not be propagated. Instead, changing the divider setting is good enough to get child clock run at the requested rate. On an imx6q clock configuration illustrated below, ahb --> ipg --> ipg_per 132M 66M 66M calling clk_set_rate(ipg_per, 22M) with the current clk_divider_bestdiv() implementation will result in the rate change up to ahb level like the following, because of the unnecessary/incorrect rate change propagation. ahb --> ipg --> ipg_per 66M 22M 22M Fix the problem by trying to see if the requested rate can be achieved by simply changing the divider value, and in that case return the divider immediately from function clk_divider_bestdiv() as the best one, so that all those unnecessary rate change propagation can be saved. Reported-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: divider: Introduce CLK_DIVIDER_ALLOW_ZERO flagSoren Brinkmann2013-04-031-2/+3
| | | | | | | | | | | Dividers which have CLK_DIVIDER_ONE_BASED set have a redundant state, being a divider value of zero. Some hardware implementations allow a zero divider which simply doesn't alter the frequency. I.e. it acts like a divide by one or bypassing the divider. This flag is used to handle such HW in the clk-divider model. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk-divider: fix macrosJames Hogan2013-01-181-3/+3
| | | | | | | | | | | | | The macro is_power_of_two() in clk-divider.c was defined as !(i & ~i) which is always true. Instead use is_power_of_2() from log2.h. Also add brackets around the macro arguments in div_mask to avoid any future operator precedence problems. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Joe Perches <joe@perches.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: use log2.h per Joe Perches; update changelog]
* clk: Add CLK_IS_BASIC flag to identify basic clocksRajendra Nayak2012-07-111-1/+1
| | | | | | | | | | | | | | | | Most platforms end up using a mix of basic clock types and some which use clk_hw_foo struct for filling in custom platform information when the clocks don't fit into basic types supported. In platform code, its useful to know if a clock is using a basic type or clk_hw_foo, which helps platforms know if they can safely use to_clk_hw_foo to derive the clk_hw_foo pointer from clk_hw. Mark all basic clocks with a CLK_IS_BASIC flag. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: Add support for rate table based dividersRajendra Nayak2012-07-111-16/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | Some divider clks do not have any obvious relationship between the divider and the value programmed in the register. For instance, say a value of 1 could signify divide by 6 and a value of 2 could signify divide by 4 etc. Also there are dividers where not all values possible based on the bitfield width are valid. For instance a 3 bit wide bitfield can be used to program a value from 0 to 7. However its possible that only 0 to 4 are valid values. All these cases need the platform code to pass a simple table of divider/value tuple, so the framework knows the exact value to be written based on the divider calculation and can also do better error checking. This patch adds support for such rate table based dividers and as part of the support adds a new registration function 'clk_register_divider_table()' and a new macro for static definition 'DEFINE_CLK_DIVIDER_TABLE'. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: Add support for power of two type dividersRajendra Nayak2012-07-111-19/+47
| | | | | | | | | | | | | | | | | | Quite often dividers and the value programmed in the register have a relation of 'power of two', something like value div 0 1 1 2 2 4 3 8... Add support for such dividers as part of clk-divider. The clk-divider flag 'CLK_DIVIDER_POWER_OF_TWO' should be used to define such clocks. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: Use a separate struct for holding init data.Saravana Kannan2012-05-011-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a struct clk_init_data to hold all data that needs to be passed from the platfrom specific driver to the common clock framework during clock registration. Add a pointer to this struct inside clk_hw. This has several advantages: * Completely hides struct clk from many clock platform drivers and static clock initialization code that don't care for static initialization of the struct clks. * For platforms that want to do complete static initialization, it removed the need to directly mess with the struct clk's fields while still allowing to statically allocate struct clk. This keeps the code more future proof even if they include clk-private.h. * Simplifies the generic clk_register() function and allows adding optional fields in the future without modifying the function signature. * Simplifies the static initialization of clocks on all platforms by removing the need for forward delcarations or convoluted macros. Signed-off-by: Saravana Kannan <skannan@codeaurora.org> [mturquette@linaro.org: kept DEFINE_CLK_* macros and __clk_init] Signed-off-by: Mike Turquette <mturquette@linaro.org> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Jeremy Kerr <jeremy.kerr@canonical.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Arnd Bergman <arnd.bergmann@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Jamie Iles <jamie@jamieiles.com> Cc: Richard Zhao <richard.zhao@linaro.org> Cc: Saravana Kannan <skannan@codeaurora.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Deepak Saxena <dsaxena@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca>
* clk: pass parent_rate into .set_rateShawn Guo2012-04-241-2/+3
| | | | | | | | | | | For most of .set_rate implementation, parent_rate will be used, so just like passing parent_rate into .recalc_rate, let's pass parent_rate into .set_rate too. It also updates the kernel doc for .set_rate ops. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: always pass parent_rate into .round_rateShawn Guo2012-04-241-9/+3
| | | | | | | | | The parent_rate will likely be used by most .round_rate implementation no matter whether flag CLK_SET_RATE_PARENT is set or not, so let's always pass parent_rate into .round_rate. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: basic: improve parent_names & return errorsMike Turquette2012-04-241-15/+19
| | | | | | | | | | | | | | This patch is the basic clk version of 'clk: core: copy parent_names & return error codes'. The registration functions are changed to allow the core code to copy the array of strings and allow platforms to declare those arrays as __initdata. This patch also converts all of the basic clk registration functions to return error codes which better aligns them with the existing clk.h api. Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: add "const" for clk_ops of basic clksShawn Guo2012-04-241-1/+1
| | | | | | | | The clk_ops of basic clks should have "const" to match the definition in "struct clk" and clk_register prototype. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: remove unnecessary EXPORT_SYMBOL_GPLShawn Guo2012-04-241-3/+0
| | | | | | | It makes no sense to have EXPORT_SYMBOL_GPL on static functions. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: basic clock hardware typesMike Turquette2012-03-161-0/+200
Many platforms support simple gateable clocks, fixed-rate clocks, adjustable divider clocks and multi-parent multiplexer clocks. This patch introduces basic clock types for the above-mentioned hardware which share some common characteristics. Based on original work by Jeremy Kerr and contribution by Jamie Iles. Dividers and multiplexor clocks originally contributed by Richard Zhao & Sascha Hauer. Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Mike Turquette <mturquette@ti.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Jeremy Kerr <jeremy.kerr@canonical.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Arnd Bergman <arnd.bergmann@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Jamie Iles <jamie@jamieiles.com> Cc: Richard Zhao <richard.zhao@linaro.org> Cc: Saravana Kannan <skannan@codeaurora.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Deepak Saxena <dsaxena@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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