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* clk: hi3620: add gate clock flagHaojian Zhuang2013-12-111-59/+59
| | | | | | Add missing CLK_SET_RATE_PARENT flag for gate clock. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
* clk: hi3620: fix wrong flags on dividerHaojian Zhuang2013-12-111-11/+11
| | | | | | | The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not CLK_MUX_HIWORD_MASK. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
* clk: hisilicon: add common clock supportHaojian Zhuang2013-12-045-0/+651
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is used to support the clock gate that enable/disable/status registers are seperated. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>