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| | * | clk: imx: Add 519.75MHz frequency support for imx9 pllJacky Bai2023-07-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For video pll, it may need 519.75MHz clock frequency for the LVDS display usage. So add 519.75MHz frequency config support for video pll. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230628061724.2056520-3-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * | clk: imx93: Add PDM IPG clkChancel Liu2023-07-251-1/+3
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IPG clk and MCLK of PDM share the same control gate. Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230628061724.2056520-2-ping.bai@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| * / clk: Explicitly include correct DT includesRob Herring2023-07-194-5/+2
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5 Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* / clk: imx93: Propagate correct error in imx93_clocks_probe()Geert Uytterhoeven2023-07-191-1/+1
|/ | | | | | | | | | | | | | | | | | | | smatch reports: drivers/clk/imx/clk-imx93.c:294 imx93_clocks_probe() error: uninitialized symbol 'base'. Indeed, in case of an error, the wrong (yet uninitialized) variable is converted to an error code and returned. Fix this by propagating the error code in the correct variable. Fixes: e02ba11b45764705 ("clk: imx93: fix memory leak and missing unwind goto in imx93_clocks_probe") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/9c2acd81-3ad8-485d-819e-9e4201277831@kadam.mountain Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/all/202306161533.4YDmL22b-lkp@intel.com/ Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230711150812.3562221-1-geert+renesas@glider.be Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-06-2912-45/+100
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This batch of clk driver updates contains almost no new SoC support. Instead there's a treewide patch series from Maxime that makes clk_ops::determine_rate mandatory for muxes. Beyond that core framework change we have the usual pile of clk driver updates such as migrating i2c drivers to use .probe() again or YAMLfication of clk DT bindings so we can validate DTBs. Overall the SoCs that got the most updates this time around in terms of diffstat are the Amlogic and Mediatek drivers because they added new SoC support or fixed up various drivers to have proper data. In general things look kinda quiet. I suspect the core framework change may still shake out some problems after the merge window, mostly because not everyone tests linux-next where that series has been for some number of weeks. I saw that there's at least one pending fix for Tegra that needs to be wrapped up into a proper patch. I'll try to catch those bits before the window closes so that -rc1 is bootable. More details below. Core: - Make clk_ops::determine_rate mandatory for muxes New Drivers: - Add amlogic a1 SoC family PLL and peripheral clock controller support Updates: - Handle allocation failures from kasprintf() and friends - Migrate platform clk drivers to .remove_new() - Migrate i2c clk drivers to .probe() instead of .probe_new() - Remove CLK_SET_PARENT from all Mediatek MSDC core clocks - Add infra_ao reset support for Mediatek MT8188 SoCs - Align driver_data to i2c_device_id tables in some i2c clk drivers - Use device_get_match_data() in vc5 clk driver - New Kconfig symbol name (SOC_MICROCHIP_POLARFIRE) for Microchip FPGA clock drivers - Use of_property_read_bool() to read "microchip,pic32mzda-sosc" boolean DT property in clk-pic32mzda - Convert AT91 clock dt-bindings to YAML - Remove CLK_SET_RATE_PARENT flag from LDB clocks on i.MX6SX - Keep i.MX UART clocks enabled during kernel boot if earlycon is set - Drop imx_unregister_clocks() as there are no users anymore - Switch to _safe iterator on imx_clk_scu_unregister() to avoid use after free - Add determine_rate op to the imx8m composite clock - Use device managed API for iomap and kzalloc for i.MXRT1050, i.MX8MN, i.MX8MP and i.MX93 clock controller drivers - Add missing interrupt DT property for the i.MX8M clock controller - Re-add support for Exynos4212 clock controller because we are re-introducing the SoC in the mainline - Add CONFIG_OF dependency to Samsung clk Kconfig symbols to solve some objtool warnings - Preselect PLL MIPI as TCON0 parent for Allwinner A64 SoC - Convert the Renesas clock drivers to readl_poll_timeout_atomic() - Add PWM clock on Renesas R-Car V3U - Fix PLL5 on Renesas RZ/G2L and RZ/V2L" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (149 commits) clk: fix typo in clk_hw_register_fixed_rate_parent_data() macro clk: Fix memory leak in devm_clk_notifier_register() clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes clk: mvebu: Use of_get_cpu_hwid() to read CPU ID MAINTAINERS: Add Marvell mvebu clock drivers clk: clocking-wizard: check return value of devm_kasprintf() clk: ti: clkctrl: check return value of kasprintf() clk: keystone: sci-clk: check return value of kasprintf() clk: si5341: free unused memory on probe failure clk: si5341: check return value of {devm_}kasprintf() clk: si5341: return error if one synth clock registration fails clk: cdce925: check return value of kasprintf() clk: vc5: check memory returned by kasprintf() clk: mediatek: clk-mt8173-apmixedsys: Fix iomap not released issue clk: mediatek: clk-mt8173-apmixedsys: Fix return value for of_iomap() error clk: mediatek: clk-mtk: Grab iomem pointer for divider clocks clk: keystone: syscon-clk: Add support for audio refclk dt-bindings: clock: Add binding documentation for TI Audio REFCLK dt-bindings: clock: ehrpwm: Remove unneeded syscon compatible clk: keystone: syscon-clk: Allow the clock node to not be of type syscon ...
| *-. Merge branches 'clk-imx', 'clk-microchip', 'clk-cleanup', 'clk-bindings', ↵Stephen Boyd2023-06-2610-44/+79
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'clk-ti' and 'clk-kasprintf' into clk-next - Handle allocation failures from kasprintf() and friends * clk-imx: clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe() clk: imx93: fix memory leak and missing unwind goto in imx93_clocks_probe clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probe dt-bindings: clock: imx8m: Add missing interrupt property clk: imx: clk-imxrt1050: fix memory leak in imxrt1050_clocks_probe clk: imx: composite-8m: Add imx8m_divider_determine_rate clk: imx: scu: use _safe list iterator to avoid a use after free clk: imx: drop imx_unregister_clocks clk: imx6ul: retain early UART clocks during kernel init clk: imx: imx6sx: Remove CLK_SET_RATE_PARENT from the LDB clocks * clk-microchip: dt-bindings: clocks: at91sam9x5-sckc: convert to yaml dt-bindings: clocks: atmel,at91rm9200-pmc: convert to yaml clk: microchip: Use of_property_read_bool() for boolean properties clk: microchip: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE * clk-cleanup: clk: fix typo in clk_hw_register_fixed_rate_parent_data() macro clk: Fix memory leak in devm_clk_notifier_register() clk: mvebu: Iterate over possible CPUs instead of DT CPU nodes clk: mvebu: Use of_get_cpu_hwid() to read CPU ID MAINTAINERS: Add Marvell mvebu clock drivers clk: mvebu: Use of_address_to_resource() clk: tegra: tegra124-emc: Fix potential memory leak clk: clocking-wizard: Fix Oops in clk_wzrd_register_divider() clk: bcm: rpi: Fix off by one in raspberrypi_discover_clocks() clk: sifive: Use devm_platform_ioremap_resource() * clk-bindings: dt-bindings: clock: drop unneeded quotes and use absolute /schemas path dt-bindings: rcc: stm32: Sync with u-boot copy for STM32MP13 SoC * clk-ti: clk: keystone: syscon-clk: Add support for audio refclk dt-bindings: clock: Add binding documentation for TI Audio REFCLK dt-bindings: clock: ehrpwm: Remove unneeded syscon compatible clk: keystone: syscon-clk: Allow the clock node to not be of type syscon * clk-kasprintf: clk: clocking-wizard: check return value of devm_kasprintf() clk: ti: clkctrl: check return value of kasprintf() clk: keystone: sci-clk: check return value of kasprintf() clk: si5341: free unused memory on probe failure clk: si5341: check return value of {devm_}kasprintf() clk: si5341: return error if one synth clock registration fails clk: cdce925: check return value of kasprintf() clk: vc5: check memory returned by kasprintf()
| | * | clk: imx: clk-imx8mp: improve error handling in imx8mp_clocks_probe()Yuxing Liu2023-06-121-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace of_iomap() and kzalloc() with devm_of_iomap() and devm_kzalloc() which can automatically release the related memory when the device or driver is removed or unloaded to avoid potential memory leak. In this case, iounmap(anatop_base) in line 427,433 are removed as manual release is not required. Besides, referring to clk-imx8mq.c, check the return code of of_clk_add_hw_provider, if it returns negtive, print error info and unregister hws, which makes the program more robust. Fixes: 9c140d992676 ("clk: imx: Add support for i.MX8MP clock driver") Signed-off-by: Yuxing Liu <lyx2022@hust.edu.cn> Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230503070607.2462-1-lyx2022@hust.edu.cn Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * | clk: imx93: fix memory leak and missing unwind goto in imx93_clocks_probeZhanhao Hu2023-06-121-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In function probe(), it returns directly without unregistered hws when error occurs. Fix this by adding 'goto unregister_hws;' on line 295 and line 310. Use devm_kzalloc() instead of kzalloc() to automatically free the memory using devm_kfree() when error occurs. Replace of_iomap() with devm_of_iomap() to automatically handle the unused ioremap region and delete 'iounmap(anatop_base);' in unregister_hws. Fixes: 24defbe194b6 ("clk: imx: add i.MX93 clk") Signed-off-by: Zhanhao Hu <zero12113@hust.edu.cn> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230601033825.336558-1-zero12113@hust.edu.cn Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * | clk: imx: clk-imx8mn: fix memory leak in imx8mn_clocks_probeHao Luo2023-06-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use devm_of_iomap() instead of of_iomap() to automatically handle the unused ioremap region. If any error occurs, regions allocated by kzalloc() will leak, but using devm_kzalloc() instead will automatically free the memory using devm_kfree(). Fixes: daeb14545514 ("clk: imx: imx8mn: Switch to clk_hw based API") Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Hao Luo <m202171776@hust.edu.cn> Reviewed-by: Dongliang Mu <dzm91@hust.edu.cn> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230411015107.2645-1-m202171776@hust.edu.cn Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * | clk: imx: clk-imxrt1050: fix memory leak in imxrt1050_clocks_probeKai Ma2023-06-121-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use devm_of_iomap() instead of of_iomap() to automatically handle the unused ioremap region. If any error occurs, regions allocated by kzalloc() will leak, but using devm_kzalloc() instead will automatically free the memory using devm_kfree(). Also, fix error handling of hws by adding unregister_hws label, which unregisters remaining hws when iomap failed. Fixes: 7154b046d8f3 ("clk: imx: Add initial support for i.MXRT1050 clock driver") Signed-off-by: Kai Ma <kaima@hust.edu.cn> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230418113451.151312-1-kaima@hust.edu.cn Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * | clk: imx: composite-8m: Add imx8m_divider_determine_rateAdam Ford2023-06-121-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, certain clocks are derrived as a divider from their parent clock. For some clocks, even when CLK_SET_RATE_PARENT is set, the parent clock is not properly set which can lead to some relatively inaccurate clock values. Unlike imx/clk-composite-93 and imx/clk-divider-gate, it cannot rely on calling a standard determine_rate function, because the 8m composite clocks have a pre-divider and post-divider. Because of this, a custom determine_rate function is necessary to determine the maximum clock division which is equivalent to pre-divider * the post-divider. With this added, the system can attempt to adjust the parent rate when the proper flags are set which can lead to a more precise clock value. On the imx8mplus, no clock changes are present. On the Mini and Nano, this can help achieve more accurate lcdif clocks. When trying to get a pixel clock of 31.500MHz on an imx8m Nano, the clocks divided the 594MHz down, but left the parent rate untouched which caused a calulation error. Before: video_pll 594000000 video_pll_bypass 594000000 video_pll_out 594000000 disp_pixel 31263158 disp_pixel_clk 31263158 Variance = -236842 Hz After this patch: video_pll 31500000 video_pll_bypass 31500000 video_pll_out 31500000 disp_pixel 31500000 disp_pixel_clk 31500000 Variance = 0 Hz All other clocks rates and parent were the same. Similar results on imx8mm were found. Fixes: 690dccc4a0bf ("Revert "clk: imx: composite-8m: Add support to determine_rate"") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Tested-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20230506195325.876871-1-aford173@gmail.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * | clk: imx: scu: use _safe list iterator to avoid a use after freeDan Carpenter2023-05-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This loop is freeing "clk" so it needs to use list_for_each_entry_safe(). Otherwise it dereferences a freed variable to get the next item on the loop. Fixes: 77d8f3068c63 ("clk: imx: scu: add two cells binding support") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/0793fbd1-d2b5-4ec2-9403-3c39343a3e2d@kili.mountain Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * | clk: imx: drop imx_unregister_clocksPeng Fan2023-05-182-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no user using imx_unregister_clocks, so drop it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230506090856.3599035-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * | clk: imx6ul: retain early UART clocks during kernel initAlexander Stein2023-05-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230421115517.1940990-1-alexander.stein@ew.tq-group.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * | clk: imx: imx6sx: Remove CLK_SET_RATE_PARENT from the LDB clocksFabio Estevam2023-05-181-4/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the i.MX6SX, it is common to use the LDB and LCDIF with the same parent clock, such as the IMX6SX_CLK_PLL5_VIDEO_DIV, for example. Due to the CLK_SET_RATE_PARENT flag, the LDB clock would try to set the clock parent rate, which can mess with the required clock rate calculated from the eLCDIF driver. To prevent this problem, remove the CLK_SET_RATE_PARENT flag from the LDB clocks, so that a correct clock relationship can be achieved. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230416150004.16834-1-festevam@gmail.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| * | clk: imx: scu: Switch to determine_rateMaxime Ripard2023-06-081-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iMX SCU clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The driver does implement round_rate() though, which means that we can change the rate of the clock, but we will never get to change the parent. However, It's hard to tell whether it's been done on purpose or not. Since we'll start mandating a determine_rate() implementation, let's convert the round_rate() implementation to a determine_rate(), which will also make the current behavior explicit. The round_rate() implementation being shared with other clocks, it's not removed. And if it was an oversight, the clock behaviour can be adjusted later on. Cc: Abel Vesa <abelvesa@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-58-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: imx: scu: Add a determine_rate hookMaxime Ripard2023-06-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iMX SCU mux clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidates to trigger that parent change are either the assigned-clock-parents device tree property or a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. Similarly, it doesn't look like the device tree using that clock driver uses any of the assigned-clock properties on that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the determine_rate implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Cc: Abel Vesa <abelvesa@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-28-971d5077e7d2@cerno.tech | Reported-by: kernel test robot <lkp@intel.com>: Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: imx: fixup-mux: Add a determine_rate hookMaxime Ripard2023-06-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iMX fixup mux clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidates to trigger that parent change are either the assigned-clock-parents device tree property or a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. However, the upstream device trees seem to use assigned-clock-parents on that clock to force the parent at boot time, so it's likely that the author intent was to force the parent through the device tree and prevent any reparenting but through an explicit call to clk_set_parent(). This case would be equivalent to setting the determine_rate implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. Cc: Abel Vesa <abelvesa@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-27-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * | clk: imx: busy: Add a determine_rate hookMaxime Ripard2023-06-081-0/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iMX busy clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidates to trigger that parent change are either the assigned-clock-parents device tree property or a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. Similarly, it doesn't look like the device tree using that clock driver uses any of the assigned-clock properties on that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the determine_rate implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Cc: Abel Vesa <abelvesa@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-26-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* / clk: imx: Drop inclusion of unused header <soc/imx/timer.h>Uwe Kleine-König2023-06-234-4/+0
|/ | | | | | | | The clk drivers use none of the symbols defined in <soc/imx/timer.h>. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20230328100531.879485-2-u.kleine-koenig@pengutronix.de
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-05-071-7/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A couple more patches that would be good to get into -rc1: - Revert an i.MX patch that's causing video failures because division math goes sideways - Fix a clang + W=1 build isue where FIELD_PREP() is taking a 32-bit variable instead of the usual u64 type - Fix a Kconfig bug in the StarFive JH7110 clk config that selects a reset controller when it can't be selected" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: starfive: Fix RESET_STARFIVE_JH7110 can't be selected in a specified case clk: sp7021: Adjust width of _m in HWM_FIELD_PREP() Revert "clk: imx: composite-8m: Add support to determine_rate"
| * Revert "clk: imx: composite-8m: Add support to determine_rate"Adam Ford2023-05-021-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 156e96ff2172518b6f83e97d8f11f677bc668e22. This patch was found to cause some division issues on the i.MX8MP which causes the video clocks to not properly divide when division was greate than 8. This causes video failures on disp1_pix and disp2_pix clocks. Until a better solution is found, we'll have to revert this. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20230423123828.1346511-1-aford173@gmail.com Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-04-2913-47/+430
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Nothing looks out of the ordinary in this batch of clk driver updates. There are a couple patches to the core clk framework, but they're all basically cleanups or debugging aids. The driver updates and new additions are dominated in the diffstat by Qualcomm and MediaTek drivers. Qualcomm gained a handful of new drivers for various SoCs, and MediaTek gained a bunch of drivers for MT8188. The MediaTek drivers are being modernized as well, so there are updates all over that vendor's clk drivers. There's also a couple other new clk drivers in here, for example the Starfive JH7110 SoC support is added. Outside of the two major SoC vendors though, we have the usual collection of non-critical fixes and cleanups to various clk drivers. It's good to see that we're getting more cleanups and modernization patches. Maybe one day we'll be able to properly split clk providers from clk consumers. Core: - Print an informational message before disabling unused clks New Drivers: - BCM63268 timer clock and reset controller - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and MT8195 SoCs - Mediatek MT8188 SoC clk drivers - Clock driver for Sunplus SP7021 SoC - Clk driver support for Loongson-2 SoCs - Clock driver for Skyworks Si521xx I2C PCIe clock generators - Initial Starfive JH7110 clk/reset support - Global clock controller drivers for Qualcomm SM7150, IPQ9574, MSM8917 and IPQ5332 SoCs - GPU clock controller drivers for SM6115, SM6125, SM6375 and SA8775P SoCs Updates: - Shrink size of clk_fractional_divider a little - Convert various clk drivers to devm_of_clk_add_hw_provider() - Convert platform clk drivers to remove_new() - Converted most Mediatek clock drivers to struct platform_driver - MediaTek clock drivers can be built as modules - Reimplement Loongson-1 clk driver with DT support - Migrate socfpga clk driver to of_clk_add_hw_provider() - Support for i3c clks on Aspeed ast2600 SoCs - Add clock generic devm_clk_hw_register_gate_parent_data - Add audiomix block control for i.MX8MP - Add support for determine_rate to i.MX composite-8m - Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate - Provide clock name in error message for clk-gpr-mux on get parent failure - Drop duplicate imx_clk_mux_flags macro - Register the i.MX8MP Media Disp2 Pix clock as bus clock - Add Media LDB root clock to i.MX8MP - Make i.MX8MP nand_usdhc_bus clock as non-critical - Fix the rate table for i.MX fracn-gppll - Disable HW control for the fracn-gppll in order to be controlled by register write - Add support for interger PLL in fracn-gppll - Add mcore_booted module parameter to i.MX93 provider - Add NIC, A55 and ARM PLL clocks to i.MX93 - Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents - Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP to get more accurate clock rates - Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical - Update some of the i.MX critical clocks flags to allow glitchless on-the-fly rate change. - Add I2C5 clock on Renesas R-Car V3H - Exynos850: Add CMU_G3D clock controller for the Mali GPU - Extract Exynos5433 (ARM64) clock controller power management code to common driver parts - Exynos850: make PMU_ALIVE_PCLK clock critical - Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel Selector (ISPCS), and video capture (VIN) clocks on Renesas R-Car V4H - Add video capture (VIN) clocks on Renesas R-Car V3H - Add Cortex-A53 System CPU (Z2) clocks on Renesas R-Car V3M and V3H - Support for Stromer Plus PLL on Qualcomm IPQ5332 - Add a missing reset to Qualcomm QCM2290 - Migrate Qualcomm IPQ4019 to clk_parent_data - Make USB GDSCs enter retention state when disabled on Qualcomm SM6375, MSM8996 and MSM8998 SoCs - Set floor rounding clk_ops for Qualcomm QCM2290 SDCC2 clk - Add two EMAC GDSCs on Qualcomm SC8280XP - Use shared rcg clk ops in Qualcomm SM6115 GCC - Park Qualcomm SM8350 PCIe PIPE clks when disabled - Add GDSCs to Qualcomm SC7280 LPASS audio clock controller - Add missing XO clocks to Qualcomm MSM8226 and MSM8974 - Convert some Qualcomm clk DT bindings to YAML - Reparenting fix for the clock supplying camera modules on Rockchip rk3399 - Mark more critical (bus-)clocks on Rockchip rk3588" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (290 commits) clk: qcom: gcc-sc8280xp: Add EMAC GDSCs clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers clk: rockchip: rk3588: make gate linked clocks critical clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk clk: qcom: add the GPUCC driver for sa8775p dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property clk: starfive: Avoid casting iomem pointers clk: microchip: fix potential UAF in auxdev release callback clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` clk: mediatek: fhctl: Mark local variables static clk: sifive: make SiFive clk drivers depend on ARCH_ symbols clk: uniphier: Use managed `of_clk_add_hw_provider()` clk: si5351: Use managed `of_clk_add_hw_provider()` clk: si570: Use managed `of_clk_add_hw_provider()` clk: si514: Use managed `of_clk_add_hw_provider()` clk: lmk04832: Use managed `of_clk_add_hw_provider()` ...
| * Merge branch 'clk-imx' into clk-nextStephen Boyd2023-04-2512-43/+430
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-imx: (25 commits) clk: imx: imx8ulp: update clk flag for system critical clock clk: imx: imx8ulp: Add tpm5 clock as critical gate clock clk: imx: imx8ulp: keep MU0_B clock enabled always clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents clk: imx: imx93: Add nic and A55 clk dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLK clk: imx: imx93: add mcore_booted module paratemter clk: imx: fracn-gppll: Add 300MHz freq support for imx9 clk: imx: fracn-gppll: support integer pll clk: imx: fracn-gppll: disable hardware select control clk: imx: fracn-gppll: fix the rate table clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-critical clk: imx: imx8mp: Add LDB root clock dt-bindings: clock: imx8mp: Add LDB clock entry clk: imx: imx8mp: correct DISP2 pixel clock type clk: imx: drop duplicated macro clk: imx: clk-gpr-mux: Provide clock name in error message clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate ...
| | * clk: imx: imx8ulp: update clk flag for system critical clockJacky Bai2023-04-091-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support bus fabric clock frequency changed on the fly, need to update some bus clocks'flags to make sure these clocks'frequency and parent can be changed on the fly. For these clocks, HW can make sure no glitch will be introduced when changing on the fly. In order to support DDR DFS, the HW register bit for DDR_SEL and DDR_DIV clock will be modified by TF-A. So need to update these two clock's flag to make sure that the linux kernel side can correct these clocks' SW state to reflect the actual HW state. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-6-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8ulp: Add tpm5 clock as critical gate clockJacky Bai2023-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TPM5 is used for broadcast timer purpose and registered with TIMER_OF_DECLARE. As the clock driver is not ready at that stage, so the TPM5 clock is configured in bootloader(TF-A). if we just remove the TPM5 clock from linux will introduce a risk that the TPM5's parent clock will be gated, then lead to TPM's channel control config can NOT be written into register successfully. Due to the above reason, we still need to add the TPM5 clock into linux clock but register it as a simple critical gate clock to make sure its parent is always on. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8ulp: keep MU0_B clock enabled alwaysJacky Bai2023-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keep the A35<->M33 MU0_B clock enabled always for low power communication. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8ulp: Add divider closest support to get more accurate clock rateJacky Bai2023-04-092-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a divider's parent clock has fractional part, it will hard to round out a more accurate clock rate for this divider, add the 'CLK_DIVIDER_ROUND_CLOSEST' flags for such divider to get a more accurate clock rate. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parentsPeng Fan2023-04-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XBAR_DIVBUS and AD_SLOW should set parent to XBAR_AD_DIVPLAT and XBAR_DIVBUS respectively, not the NIC_AD. otherwise we will get wrong clock rate. Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp") Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx93: Add nic and A55 clkPeng Fan2023-04-091-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A55 clock logic as below: A55_PLL ----------------->\ A55_SEL-->A55_CORE A55_CCM_ROOT--->A55_GATE->/ Add A55 CPU clk to support freq change. Add NIC CLK to reflect the clk status Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-8-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx93: add mcore_booted module paratemterPeng Fan2023-04-092-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX93, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and LPCG (clock gating) to gate clocks to peripherals. As below: anatop->ccm->lpcg->peripheral Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for LPCG and CCM, auxiliary core normally only use LPCG hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-6-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: fracn-gppll: Add 300MHz freq support for imx9Jacky Bai2023-04-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 300MHz frequency config support on i.MX93 PLL. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: fracn-gppll: support integer pllPeng Fan2023-04-092-7/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fracn gppll could be configured in FRAC or INTEGER mode during hardware design. The current driver only support FRAC mode, while this patch introduces INTEGER support. When the PLL is INTEGER pll, there is no mfn, mfd, the calculation is as below: Fvco_clk = (Fref / DIV[RDIV] ) * DIV[MFI] Fclko_odiv = Fvco_clk / DIV[ODIV] In this patch, we reuse the FRAC pll logic with some condition check to simplify the driver Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: fracn-gppll: disable hardware select controlPeng Fan2023-04-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When programming PLL, should disable Hardware control select to make PLL controlled by register, not hardware inputs through OSCPLL. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: fracn-gppll: fix the rate tablePeng Fan2023-04-091-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Fvco should be range 2.4GHz to 5GHz, the original table voilate the spec, so update the table to fix it. Fixes: c196175acdd3 ("clk: imx: clk-fracn-gppll: Add more freq config for video pll") Fixes: 044034efbeea ("clk: imx: clk-fracn-gppll: fix mfd value") Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-criticalHaibo Chen2023-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'nand_usdhc_bus' clock is only need to be enabled when usdhc or nand module is active, so change it to non-critical clock type. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230403094633.3366446-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8mp: Add LDB root clockLiu Ying2023-04-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds "media_ldb_root_clk" clock for the LDB in the MEDIAMIX subsystem. Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230403094633.3366446-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8mp: correct DISP2 pixel clock typePeng Fan2023-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The MEDIA_DISP2_CLK_ROOT use ccm_ahb_channel, it is bus type. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403094633.3366446-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: drop duplicated macroPeng Fan2023-04-031-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Drop duplicated macro definition Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403082728.3199849-1-peng.fan@oss.nxp.com
| | * clk: imx: clk-gpr-mux: Provide clock name in error messageStefan Wahren2023-03-311-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In error case the error message doesn't provide much context: imx:clk-gpr-mux: failed to get parent (-EINVAL) So additionally provide the clock name in the message, in order to simplify the further analyze. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230308184603.10049-1-stefan.wahren@i2se.com
| | * clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rateAdam Ford2023-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default the display pixel clock needs to be evenly divide down from the video_pll_out clock which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll 594000000 video_pll_bypass 594000000 video_pll_out 594000000 disp_pixel 148500000 disp_pixel_clk 148500000 Now that composite-8m supports determine_rate, we can allow disp_pixel to set the parent rate which then switches every clock in the chain to a new frequency when disp_pixel cannot evenly divide from video_pll_out. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-5-aford173@gmail.com
| | * clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rateAdam Ford2023-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default the display pixel clock needs to be evenly divide down from 594MHz which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll1 594000000 video_pll1_bypass 594000000 video_pll1_out 594000000 lcdif_pixel 148500000 Now that composite-8m supports determine_rate, we can allow lcdif_pixel to set the parent rate which then switches every clock in the chain to a new frequency when lcdif_pixel cannot evenly divide from video_pll1_out. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-4-aford173@gmail.com
| | * clk: imx: Add imx8m_clk_hw_composite_flags macroAdam Ford2023-03-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to set custom flags to imx8m_clk_hw_composite, split it off into a separate macro which can accept additional flags. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-3-aford173@gmail.com
| | * clk: imx: composite-8m: Add support to determine_rateAdam Ford2023-03-311-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to imx/clk-composite-93 and imx/clk-divider-gate, the imx8m_clk_composite_divider_ops can support determine_rate. Without this the parent clocks are set to a fixed value, and if a consumer needs a slower reate, the clock is divided, but the division is only as good as the parent clock rate. With this added, the system can attempt to adjust the parent rate if the proper flags are set which can lead to a more precise clock value. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-2-aford173@gmail.com
| | * clk: imx: imx8mp: Add audiomix block controlMarek Vasut2023-03-312-1/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike the other block control IPs in i.MX8M, the audiomix is mostly a series of clock gates and muxes. Model it as a large static table of gates and muxes with one exception, which is the PLL14xx . The PLL14xx SAI PLL has to be registered separately. Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230301163257.49005-2-marex@denx.de
| * | clk: imx: Remove values for mmask and nmask in struct clk_fractional_dividerChristophe JAILLET2023-04-051-4/+0
| |/ | | | | | | | | | | | | | | | | | | Now that fractional_divider clk computes mmask and nmask when needed, there is no more need to provide them explicitly anymore. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/187a2266c3a034a593a151d6e5e6b21118043b5d.1680423909.git.christophe.jaillet@wanadoo.fr Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* / clk: imx6ul: fix "failed to get parent" errorOleksij Rempel2023-03-201-4/+6
|/ | | | | | | | | | | | | | | | On some configuration we may get following error: [ 0.000000] imx:clk-gpr-mux: failed to get parent (-EINVAL) This happens if selector is configured to not supported value. To avoid this warnings add dummy parents for not supported values. Fixes: 4e197ee880c2 ("clk: imx6ul: add ethernet refclock mux support") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://lore.kernel.org/r/20230310164523.534571-1-o.rempel@pengutronix.de Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Reported-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: pll14xx: fix recalc_rate for negative kdivKevin Groeneveld2023-02-211-1/+1
| | | | | | | | | | | | | | | kdiv is a signed 16 bit value in the DEV_CTL1 register. Commit 53990cf9d5b4 ("clk: imx: pll14xx: consolidate rate calculation") changed the kdiv variable from a short int to just int. When the value read from the DIV_CTL1 register is assigned directly to an int the sign of the value is lost resulting in incorrect results when the value is negative. Adding a s16 cast to the register value fixes the issue. Fixes: 53990cf9d5b4 ("clk: imx: pll14xx: consolidate rate calculation") Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com> Link: https://lore.kernel.org/r/20221210203835.9714-1-kgroeneveld@lenbrook.com Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: fix compile testing imxrt1050Arnd Bergmann2023-02-104-1/+9
| | | | | | | | | | | | | | | | | | | Randconfig testing revealed multiple issues with this driver: ERROR: modpost: missing MODULE_LICENSE() in drivers/clk/imx/clk-imxrt1050.o ERROR: modpost: "imx_clk_hw_pllv3" [drivers/clk/imx/clk-imxrt1050.ko] undefined! ERROR: modpost: "imx_clk_hw_pfd" [drivers/clk/imx/clk-imxrt1050.ko] undefined! Export the necessary symbols from the core clk driver and add the license and author tags. To find this type of problem more easily in the future, also enable building on other platforms, as we do for the other i.MX clk drivers. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20221215165836.2136448-1-arnd@kernel.org Acked-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to staticTom Rix2023-02-101-1/+1
| | | | | | | | | | | | smatch reports drivers/clk/imx/clk-gpr-mux.c:73:22: warning: symbol 'imx_clk_gpr_mux_ops' was not declared. Should it be static? imx_clk_gpr_mux_ops is only used in clk-gpr-mux.c, so it should be static. Signed-off-by: Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20230205030138.1723614-1-trix@redhat.com Fixes: ee394f636ad3 ("clk: imx: add clk-gpr-mux driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-23 13:14:48 +0000