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* clk: gxbb: remove CLK_IGNORE_UNUSED from clk81Jerome Brunet2017-05-291-1/+1
| | | | | | | | | clk81 already has CLK_IS_CRITICAL so CLK_IGNORE_UNUSED is not necessary Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driverMartin Blumenstingl2017-05-291-61/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that the "cpu_clk" was carried over from the meson8b clock controller driver. On Meson GX (GXBB/GXL/GXM) the registers which are used by the cpu_clk have a different purpose (in other words: they don't control the CPU clock anymore). HHI_SYS_CPU_CLK_CNTL1 bits 31:24 are reserved according to the public S905 datasheet, while bit 23 is the "A53_trace_clk_DIS" gate (which according to the datasheet should only be used in case a silicon bug is discovered) and bits 22:20 are a divider (A53_trace_clk). The meson clk-cpu code however expects that bits 28:20 are reserved for a divider (according to the public S805 datasheet this "SCALE_DIV: This value represents an N+1 divider of the input clock."). The CPU clock on Meson GX SoCs is provided by the SCPI DVFS clock driver instead. Two examples from a Meson GXL S905X SoC: - vcpu (SCPI DVFS clock 0) rate: 1000000000 / cpu_clk rate: 708000000 - vcpu (SCPI DVFS clock 0) rate: 1512000000 / cpu_clk rate: 708000000 Unfortunately the CLKID_CPUCLK was already exported (but is currently not used) to DT. Due to the removal of this clock definition there is now a hole in the clk_hw_onecell_data (which is not a problem because this case is already handled in gxbb_clkc_probe). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: gxbb: add cts_i958 clockJerome Brunet2017-04-071-0/+21
| | | | | | | | | | | This adds the cts_i958 clock to control the clock source of the spdif output block. This mux is not explicitly mentionned in the documentation but it is critical to the spdif dai. It is used to select whether the clock source of the spdif output is cts_amclk (when data are taken from i2s buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer) Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: gxbb: add cts_mclk_i958Jerome Brunet2017-04-071-0/+52
| | | | | | | Add the spdif master clock also referred as cts_mclk_i958 Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: gxbb: add cts_amclkJerome Brunet2017-04-071-0/+67
| | | | | | | Add the i2s master clock also referred as cts_amclk Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: gxbb: protect against holes in the onecell_data arrayJerome Brunet2017-04-071-0/+4
| | | | | | | | | The clock controller is getting more complex and it might be possible, in the future, to have holes in the clk_hw_onecell_data array. Just make sure we skip those holes if it ever happens. Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson-gxbb: Add GXL/GXM GP0 VariantNeil Armstrong2017-04-041-28/+273
| | | | | | | | | | | | | The clock tree in the Amlogic GXBB and GXL/GXM SoCs is shared, but the GXL/GXM SoCs embeds a different GP0 PLL, and needs different parameters with a vendor provided reduced rate table. This patch adds the GXL GP0 variant, and adds a GXL DT compatible in order to use the GXL GP0 PLL instead of the GXBB specific one. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-4-git-send-email-narmstrong@baylibre.com
* clk: meson-gxbb: Add GP0 PLL init parametersNeil Armstrong2017-04-041-0/+13
| | | | | | | | | | | | Tha Amlogic GXBB SoC GP0 PLL needs some vendor provided parameters to be initializated in the the GP0 control registers before configuring the rate with the rate table provided parameters. GXBB GP0 PLL tweaks are also selected to respect the vendor init procedure. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-3-git-send-email-narmstrong@baylibre.com
* clk: meson-gxbb: Add MALI clocksNeil Armstrong2017-04-041-0/+139
| | | | | | | | | | | | | The Mali is clocked by two identical clock paths behind a glitch free mux to safely change frequency while running. The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate. Expose these two clocks trees using generic clocks. Finally the glitch free mux is added as "mali" clock. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490177935-9646-3-git-send-email-narmstrong@baylibre.com
* clk: meson: gxbb: mpll: use rw operationJerome Brunet2017-03-271-3/+3
| | | | | | | | | Use read/write operations for the mpll clocks instead of the read-only ones. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-7-jbrunet@baylibre.com
* clk: meson: mpll: add rw operationJerome Brunet2017-03-271-0/+30
| | | | | | | | | | | This patch adds new callbacks to the meson-mpll driver to control and set the pll rate. For this, we also need to add the enable bit and sdm enable bit. The corresponding parameters are added to mpll data structure. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-6-jbrunet@baylibre.com
* clk: gxbb: put dividers and muxes in tablesJerome Brunet2017-03-271-8/+20
| | | | | | | | | | | Until now, there was only 2 dividers and 2 muxes declared for the gxbb platform. With the ongoing work on various subsystem, including audio, this is about to change. Use the same approach as gates for dividers and muxes, putting them in tables to fix the register address at runtime. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-5-jbrunet@baylibre.com
* clk: meson: add missing const qualifiers on gate arraysJerome Brunet2017-03-271-1/+1
| | | | | | | Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-3-jbrunet@baylibre.com
* clk: gxbb: add the SAR ADC clocks and expose themMartin Blumenstingl2017-01-231-0/+48
| | | | | | | | | | | | | | | | | | | The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* Merge branch 'clk-meson-gxbb' into clk-nextMichael Turquette2016-09-021-84/+84
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| * gxbb: clk: Adjust MESON_GATE macro to be shared with meson8bAlexander Müller2016-09-011-84/+84
| | | | | | | | | | | | | | | | | | | | The macro used gxbb_ prefix for clock definitions. In order to share the macro between gxbb and meson8b, the prefix must be moved to gxbb.c. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-6-git-send-email-serveralex@gmail.com
* | Merge branch 'clk-meson-gxbb' into clk-nextStephen Boyd2016-08-151-0/+9
|\| | | | | | | | | * clk-meson-gxbb: clk: gxbb: add MMC gate clocks, and expose for DT
| * clk: gxbb: add MMC gate clocks, and expose for DTKevin Hilman2016-08-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: gxbb: use builtin_platform_driver to simplify the codeWei Yongjun2016-08-151-5/+1
|/ | | | | | | Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: meson: make gxbb explicitly non-modularPaul Gortmaker2016-07-061-14/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Kconfig currently controlling compilation of this code is: drivers/clk/meson/Kconfig:config COMMON_CLK_GXBB drivers/clk/meson/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE and ALIAS are no-op for non-modules. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-3-paul.gortmaker@windriver.com
* clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette2016-06-221-0/+954
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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