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* clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICALChristian Hewitt2018-11-081-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the Khadas VIM2 (GXM) and LePotato (GXL) board there are problems with reboot; e.g. a ~60 second delay between issuing reboot and the board power cycling (and in some OS configurations reboot will fail and require manual power cycling). Similar to 'commit c987ac6f1f088663b6dad39281071aeb31d450a8 ("clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL")' the SCPI Cortex-M4 Co-Processor seems to depend on FCLK_DIV3 being operational. Until commit 05f814402d6174369b3b29832cbb5eb5ed287059 ("clk: meson: add fdiv clock gates"), this clock was modeled and left on by the bootloader. We don't have precise documentation about the SCPI Co-Processor and its clock requirement so we are learning things the hard way. Marking this clock as critical solves the problem but it should not be viewed as final solution. Ideally, the SCPI driver should claim these clocks. We also depends on some clock hand-off mechanism making its way to CCF, to make sure the clock stays on between its registration and the SCPI driver probe. Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates") Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet2018-09-261-60/+60
| | | | | | | | | | | | | | | Putting hard-coded rates inside the parameter tables assumes that the parent is known and will never change. That's a big assumption we should not make. We have everything we need to recalculate the output rate using the parent rate and the rest of the parameters. Let's do so and drop the rates from the tables. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: clk-pll: remove od parametersJerome Brunet2018-09-261-256/+228
| | | | | | | | | | | | | | | | | | | | | Remove od parameters from pll clocks and add post dividers clocks instead. Some clock, especially the one which feature several ods, may provide output between those ods. Also, some drivers, such as the hdmi driver, may require a more detailed control of the clock dividers, compared to what CCF would perform automatically. One added benefit of removing ods is that it also greatly reduce the size of the rate parameter tables. In the future, we could possibly take the predivider 'n' out of this driver as well. To do so, we will need to understand the constraints for the PLL to lock and whether or not it depends on the input clock rate. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet2018-09-261-4/+8
| | | | | | | | | | | | | CLK_GET_RATE_NOCACHE should only be necessary when the registers controlling the rate of clock may change outside of CCF. On Amlogic, it should only be the case for the hdmi pll which is directly controlled by the display driver (WIP to fix this). The other plls should not require this flag. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: clk-pll: add enable bitJerome Brunet2018-09-261-2/+30
| | | | | | | | | | | | | | | Add the enable the bit of the pll clocks. These pll clocks may be disabled but we can't model this as an external gate since the pll needs to lock when enabled. Adding this bit allows to drop the poke of the first register of PLL. This will be useful to model the different components of the pll using generic clocks elements Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: add gen_clkJerome Brunet2018-07-091-0/+66
| | | | | | | | GEN_CLK is able to route several internal clocks to one of the SoC pads. In the future, even more clocks could be made accessible using cts_msr_clk - the clock measure block. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: stop rate propagation for audio clocksJerome Brunet2018-07-091-9/+7
| | | | | | | | | | | | | | | | | | It is actually a lot easier to setup the PLL with carefully chosen rates than relying on CCF clock propagation for this audio use case. This way, we can make sure we will always be able to provide the common audio clock rates, while having the PLL in the optimal operating range. For this, we stop the rate propagation at the mux picking the PLL and let it round to the closest matching PLL. Doing so, we can use the generic divider for the i2s clock. clk-audio-divider is no longer required. It was a (poor) attempt to use CCF rate propagation while making sure the PLL rate would be high enough to work with audio use cases. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: remove obsolete register accessJerome Brunet2018-07-091-34/+2
| | | | | | | | The legacy method to access the hhi register space is not longer used. We can safely drop it now. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICALNeil Armstrong2018-06-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Amlogic Meson GXBB & GXL platforms, the SCPI Cortex-M4 Co-Processor seems to be dependent on the FCLK_DIV2 to be operationnal. The issue occurred since v4.17-rc1 by freezing the kernel boot when the 'schedutil' cpufreq governor was selected as default : [ 12.071837] scpi_protocol scpi: SCP Protocol 0.0 Firmware 0.0.0 version domain-0 init dvfs: 4 [ 12.087757] hctosys: unable to open rtc device (rtc0) [ 12.087907] cfg80211: Loading compiled-in X.509 certificates for regulatory database [ 12.102241] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' But when disabling the MMC driver, the boot finished but cpufreq failed to change the CPU frequency : [ 12.153045] cpufreq: __target_index: Failed to change cpu frequency: -5 A bisect between v4.16 and v4.16-rc1 gave 05f814402d61 ("clk: meson: add fdiv clock gates") to be the first bad commit. This commit added support for the missing clock gates before the fixed PLL fixed dividers (FCLK_DIVx) and the clock framework basically disabled all the unused fixed dividers, thus disabled a critical clock path for the SCPI Co-Processor. This patch simply sets the FCLK_DIV2 gate as critical to ensure nobody can disable it. Fixes: 05f814402d61 ("clk: meson: add fdiv clock gates") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> [few corrections in the commit description] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: use SPDX license identifiers consistentlyJerome Brunet2018-05-181-14/+1
| | | | | | | | | Replace every license notices in drivers/clk/meson by SPDX license identifiers, as described in license-rules.rst Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: gxbb: add the video decoder clocksMaxime Jourdan2018-05-151-0/+114
| | | | | | | Add the SEL/DIV/GATE for VDEC_1 and VDEC_HEVC. Signed-off-by: Maxime Jourdan <maxi.jourdan@wanadoo.fr> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: Drop unused local variable and add staticStephen Boyd2018-03-141-2/+2
| | | | | | | | | | | | | | | | | | | Fixes the following warnings: drivers/clk/meson/meson8b.c:512:19: warning: symbol 'meson8b_mpeg_clk_div' was not declared. Should it be static? drivers/clk/meson/meson8b.c:526:19: warning: symbol 'meson8b_clk81' was not declared. Should it be static? drivers/clk/meson/meson8b.c:540:19: warning: symbol 'meson8b_cpu_in_sel' was not declared. Should it be static? drivers/clk/meson/meson8b.c:591:19: warning: symbol 'meson8b_cpu_scale_div' was not declared. Should it be static? drivers/clk/meson/meson8b.c:608:19: warning: symbol 'meson8b_cpu_scale_out_sel' was not declared. Should it be static? drivers/clk/meson/meson8b.c:626:19: warning: symbol 'meson8b_cpu_clk' was not declared. Should it be static? drivers/clk/meson/gxbb.c:392:27: warning: symbol 'gxbb_gp0_init_regs' was not declared. Should it be static? drivers/clk/meson/gxbb.c:439:27: warning: symbol 'gxl_gp0_init_regs' was not declared. Should it be static? drivers/clk/meson/axg.c:195:27: warning: symbol 'axg_gp0_init_regs' was not declared. Should it be static? drivers/clk/meson/axg.c:248:27: warning: symbol 'axg_hifi_init_regs' was not declared. Should it be static? drivers/clk/meson/meson8b.c: In function 'meson8b_clkc_probe': drivers/clk/meson/meson8b.c:1052:14: warning: unused variable 'clk' [-Wunused-variable] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: meson: clean-up clk81 clocksJerome Brunet2018-03-131-4/+2
| | | | | | | | | | | | | | | | | | | | | clk81 is a composite clock which parents all the peripheral clocks of the platform. It is a critical clock which is used as provided by the bootloader. We don't want to change its rate or reparent it, ever. Remove the CLK_IGNORE_UNUSED on the mux and divider. These clock can't gate so the flag is useless, and the gate is already critical, so the clock won't ever be unused. Remove CLK_SET_RATE_NO_REPARENT from mux, it is useless since the mux is read-only. Remove CLK_SET_RATE_PARENT from the gate and divider and use ro_ops for the divider. A peripheral clock should not try to change the rate of clk81. Stopping the rate propagation is good way to make sure such request would be ignored. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: add fdiv clock gatesJerome Brunet2018-03-131-10/+90
| | | | | | | | | | | Fdiv fixed dividers clocks of the fixed_pll can actually gate independently. We never had an issue so far because these clocks were provided 'enabled' by the bootloader. Add these gates to enable/disable the clocks when required. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: add mpll pre-dividerJerome Brunet2018-03-131-3/+20
| | | | | | | | | | mpll clocks parent can actually be divided by 1 or 2. So far, this divider has always been set to 1, so the calculation was correct. Now that we know it exists, model the tree correctly. If we ever get a platform where the divider is different, we won't get into trouble Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: add gp0 frac parameter for axg and gxlJerome Brunet2018-03-131-1/+6
| | | | | | | | | Add the frac parameter for the gp0 pll of the axg and gxl. This allows to achieve rates between the fixed settings provided by the table. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: remove special gp0 lock loopJerome Brunet2018-03-131-1/+0
| | | | | | | | | | | | | | After testing, it appears that the gxl (and axg) does not require the special locking/reset loop which was initially added for it. All the values present in the gxl table can locked with the simple lock checking loop. The change switches the gxl and axg gp0 back to the simple lock checking loop and removes the code no longer required. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: poke pll CNTL lastJerome Brunet2018-03-131-2/+2
| | | | | | | | | | | | Poking CNTL first may take the PLL out of reset while we are still applying the initial settings, including the filter values initialization. This is the case for the axg and gxl gp0 pll. Doing this poke last ensures the pll stays in reset while the initial settings are applied. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: use hhi syscon if availableJerome Brunet2018-03-131-11/+28
| | | | | | | | | | | | | | | On gxbb and axg, try to get the hhi regmap from the parent DT node, which should be the HHI system controller once the necessary changes have been made in amlogic's DTs Until then, if getting regmap through the system controller fails, the clock controller will fall back to the old way, requesting memory region directly and then registering the regmap itself. This should allow a smooth transition to syscon Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: split divider and gate part of mpllJerome Brunet2018-03-131-21/+57
| | | | | | | | | | | | | | The mpll clock is a kind of fractional divider which can gate. When the RW operation have been added, enable/disable ops have been mistakenly inserted in this driver. These ops are essentially a poor copy/paste of the generic gate ops. This change removes the gate ops from the mpll driver and inserts a generic gate clock on each mpll divider, simplifying the mpll driver and reducing code duplication. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: migrate plls clocks to clk_regmapJerome Brunet2018-03-131-185/+239
| | | | | | | | | | | | | | | | | | Rework meson pll driver to use clk_regmap and move meson8b, gxbb and axg's clock using meson_clk_pll to clk_regmap. This rework is not just about clk_regmap, there a serious clean-up of the driver code: * Add lock and reset field: Previously inferred from the n field. * Simplify the reset logic: Code seemed to apply reset differently but in fact it was always the same -> assert reset, apply params, de-assert reset. The 2 lock checking loops have been kept for now, as they seem to be necessary. * Do the sequence of init register pokes only at .init() instead of in .set_rate(). Redoing the init on every set_rate() is not necessary Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: migrate the audio divider clock to clk_regmapJerome Brunet2018-03-131-21/+9
| | | | | | | | Rework meson audio divider driver to use clk_regmap and move gxbb clock using meson_clk_audio_divider to clk_regmap. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: migrate mplls clocks to clk_regmapJerome Brunet2018-03-131-84/+77
| | | | | | | | Rework meson mpll driver to use clk_regmap and move meson8b, gxbb and axg clocks using meson_clk_mpll to clk_regmap Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: migrate muxes to clk_regmapJerome Brunet2018-03-131-160/+150
| | | | | | | | Move meson8b, gxbb and axg clocks using clk_mux to clk_regmap Also remove a few useless tables in the process Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: migrate dividers to clk_regmapJerome Brunet2018-03-131-109/+108
| | | | | | | Move meson8b, gxbb and axg clocks using clk_divider to clk_regmap Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: migrate gates to clk_regmapJerome Brunet2018-03-131-129/+137
| | | | | | | Move meson8b, gxbb and axg clocks using clk_gate to clk_regmap Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: add regmap to the clock controllersJerome Brunet2018-03-131-10/+23
| | | | | | | | | | | | | | This change registers a regmap in meson8b, gxbb and axg controllers. The clock are still accessing their registers directly through iomem. Once all clocks handled by these controllers have been move to regmap, the regmap register will be removed and replaced with a syscon request. This is needed because other drivers, such as the HDMI driver, need to access the HHI register region Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: remove obsolete commentsJerome Brunet2018-03-131-6/+0
| | | | | | | | | | | | | Over time things changes in CCF and issues have been fixed in meson controllers. Now, clk81 is decently modeled by read-only PLLs, a mux, a divider and a gate. We can remove the FIXME comments related to clk81. Also remove the comment about devm_clk_hw_register, as there is apparently nothing wrong with it. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: only one loop index is necessary in probeJerome Brunet2018-03-131-7/+6
| | | | | | | | | | We don't need several loop index variables in the probe function This is far from being critical but since we are doing a vast rework of meson clock controllers, now is the time to lower the entropy a bit Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: use devm_of_clk_add_hw_providerJerome Brunet2018-03-131-2/+3
| | | | | | | | | | | | | There is no remove callbacks in meson's clock controllers and of_clk_del_provider is never called if of_clk_add_hw_provider has been executed, introducing a potential memory leak. Fixing this by the using the devm variant. In reality, the leak would never happen since these controllers are never unloaded once in use ... still, this is worth cleaning. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: use dev pointer where possibleJerome Brunet2018-03-131-1/+1
| | | | | | | | | The 'dev' pointer is directly available in gxbb and axg clock controller, so consistently use it instead of going the through the 'pdev' pointer once in while Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* clk: meson: gxbb: add the fractional part of the fixed_pllJerome Brunet2018-02-121-0/+5
| | | | | | | | | | The fixed_pll of gxbb and gxl also has a fractional parameter. This has not been a problem so far because the fractional part is actually set to 0 on these platforms, so the rate remains correct when it is ignored. Still, it is better represent the pll the way it is, so add the frac parameter now Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: fix rate calculation of plls with a fractional partJerome Brunet2018-02-121-1/+13
| | | | | | | | | | | | | | The rate of the parent should not be multiplied by 2 when the pll has a fractional part. This is making the rate calculation of the gxl_hdmi_pll wrong (and others as well). This multiplication is specific to the hdmi_pll of gxbb and is most likely due to a multiplier sitting in front of this particular pll. Add a fixed factor clock in front on the gxbb pll and remove this constant from the calculation to fix the problem Fixes: 4a47295144dd ("clk: meson: fractional pll support") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: add the gxl hdmi pllJerome Brunet2018-02-121-2/+48
| | | | | | | | | | | | The hdmi pll used in the gxl family is actually different from the gxbb one. The register layout is completely different, which explain why the hdmi pll rate has always been rubbish on the gxl family. Adding the correct register field is the first part of the fix to get a correct rate out the hdmi pll Fixes: 0d48fc558d01 ("clk: meson-gxbb: Add GXL/GXM GP0 Variant") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: add od3 to the pll driverJerome Brunet2018-02-121-0/+5
| | | | | | | | | Some meson plls, such as the hdmi pll, are using a 3rd od parameter, which is yet another "power of 2" post divider. Add it to fix the calculation of the hdmi_pll rate Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: remove useless pll rate params tablesJerome Brunet2018-02-121-94/+0
| | | | | | | | | Read-only plls don't need param table to recalculate the rate. Providing them with a param table is just a waste of memory. Remove the useless tables from sys_pll on gxbb and axg. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: make the spinlock naming more specificYixun Lan2017-12-141-56/+56
| | | | | | | | | Make the spinlock more specific, so better for lockdep debugging and ctags/grep. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocksJerome Brunet2017-12-081-13/+3
| | | | | | | | | | Remove CLK_IGNORE_UNUSED from mmc clocks. This was only needed while the mmc driver incorrectly used the xtal as source instead of the mmc clock. Now, the driver takes the correct clock, CCF is aware that the clock is being used and we can remove this flag. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com>
* clk: meson: gxbb: fix wrong clock for SARADC/SANAYixun Lan2017-11-271-2/+2
| | | | | | | | | | | | | | | | | According to the datasheet, in Meson-GXBB/GXL series, The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. Test passed at gxl-s905x-p212 board. The following published datasheets are wrong and should be updated [1] GXBB v1.1.4 [2] GXL v0.3_20170314 Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Tested-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* clk: meson: gxbb: Add VPU and VAPB clocks dataNeil Armstrong2017-10-201-0/+292
| | | | | | | | | | | | The Amlogic Meson GX SoCs needs these two clocks to power up the VPU power domain. These two clocks are similar to the MALI clocks by having a glitch-free mux and two similar clocks with gate, divider and muxes. Acked-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: removed the CLK_IGNORE_UNUSED on muxes and dividers] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* Merge tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson into ↵Stephen Boyd2017-08-231-4/+185
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next Pull Amlogic clock driver updates from Neil Armstrong: * meson8b: add the reset controller to the clkc * meson: expose all clk ids * gxbb-aoclk: Add CEC 32k clock * gxbb: add mmc input 0 clocks * meson: fix protection against undefined clks * gxbb: fix audio divider flags * tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson: clk: meson: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb-aoclk: Switch to regmap for register access dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings clk: meson: gxbb: Add sd_emmc clk0 clocks clk: meson: gxbb: fix clk_mclk_i958 divider flags clk: meson: gxbb: fix meson cts_amclk divider flags clk: meson: meson8b: register the built-in reset controller dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock clk: meson: gxbb: Add sd_emmc clk0 clkids clk: meson-gxbb: expose almost every clock in the bindings clk: meson8b: expose every clock in the bindings clk: meson: gxbb: fix protection against undefined clks clk: meson: meson8b: fix protection against undefined clks dt-bindings: clock: meson8b: describe the embedded reset controller
| * clk: meson: gxbb: Add sd_emmc clk0 clocksJerome Brunet2017-08-041-0/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Input source 0 of the mmc controllers is not directly xtal, as currently described in DT. Each controller is fed by a composite clock (the usual mux, divider and gate). The muxes inputs are the xtal (default) and the fclk_div clocks. These parents, along with the divider, should be able to provide the necessary rates for mmc and nand operation. The input muxes should also be able to take mpll2, mpll3 and gp0_pll but these are precious clocks, needed for other usage. It is better if the mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is not listed among the possible parents. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * clk: meson: gxbb: fix clk_mclk_i958 divider flagsJerome Brunet2017-08-041-3/+4
| | | | | | | | | | | | | | | | | | CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 3c277c247eab ("clk: meson: gxbb: add cts_mclk_i958") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * clk: meson: gxbb: fix meson cts_amclk divider flagsJerome Brunet2017-08-041-1/+2
| | | | | | | | | | | | | | | | | | CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags while it should have been in the divider flags Fixes: 4087bd4b2170 ("clk: meson: gxbb: add cts_amclk") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * clk: meson: gxbb: fix protection against undefined clksJerome Brunet2017-08-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | gxbb clock driver gracefully handles case where the clkid is defined but the clock hw pointer is not provided, as long as it is not at the end of the hw_onecell_data array. This patch ensure that the last entries are defined as well to handle this particular case. Fixes: a70c6e06ed7c ("clk: meson: gxbb: protect against holes in the onecell_data array") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet2017-08-011-0/+5
|/ | | | | | | | | mpll0 clock is special compared to the other mplls. It needs another bit (ssen) to be set to activate the fractional part the mpll divider Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ↵Stephen Boyd2017-06-161-5/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next Pull Amlogic clk driver updates from Jerome Brunet: * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) * Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 * tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson: clk: meson: gxbb: add all clk81 parents clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks
| * clk: meson: gxbb: add all clk81 parentsJerome Brunet2017-06-161-5/+8
| | | | | | | | | | | | | | Remove the FIXME on clk81 mux and add all the documented parents Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
* | clk: meson-gxbb: Add const to some parent name arraysStephen Boyd2017-06-021-3/+3
|/ | | | | | | | These can be marked as const * const. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: meson-gxbb: Add EE 32K Clock for CECNeil Armstrong2017-05-291-0/+54
| | | | | | | | | | | | | | | | | | | | On Amlogic GX SoCs, there is two CEC controllers : - An Amlogic CEC custom in the AO domain - The Synopsys HDMI-TX Controller in the EE domain Each of these controllers needs a 32.768KHz clock, but there is two paths : - In the EE domain, the "32k_clk" this patchs is adding - In the AO domain, with a more complex dual divider more precise setup The AO 32K clock support will be pushed later in the corresponding gxbb-aoclk driver when the AE CEC driver is ready. The EE 32k_clk must be pushed earlier since mainline support for CEC in the Synopsys HDMI-TX controller is nearby. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [Rebased patch on top of last changes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-23 23:46:39 +0000