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* clk: define to_clk_regmap() as inline functionArnd Bergmann2020-10-281-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nesting container_of() causes warnings with W=2, which is annoying if it happens in headers and fills the build log like: In file included from drivers/clk/qcom/clk-alpha-pll.c:6: drivers/clk/qcom/clk-alpha-pll.c: In function 'clk_alpha_pll_hwfsm_enable': include/linux/kernel.h:852:8: warning: declaration of '__mptr' shadows a previous local [-Wshadow] 852 | void *__mptr = (void *)(ptr); \ | ^~~~~~ drivers/clk/qcom/clk-alpha-pll.c:155:31: note: in expansion of macro 'container_of' 155 | #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ | ^~~~~~~~~~~~ drivers/clk/qcom/clk-regmap.h:27:28: note: in expansion of macro 'container_of' 27 | #define to_clk_regmap(_hw) container_of(_hw, struct clk_regmap, hw) | ^~~~~~~~~~~~ drivers/clk/qcom/clk-alpha-pll.c:155:44: note: in expansion of macro 'to_clk_regmap' 155 | #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ | ^~~~~~~~~~~~~ drivers/clk/qcom/clk-alpha-pll.c:254:30: note: in expansion of macro 'to_clk_alpha_pll' 254 | struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); | ^~~~~~~~~~~~~~~~ include/linux/kernel.h:852:8: note: shadowed declaration is here 852 | void *__mptr = (void *)(ptr); \ | ^~~~~~ Redefine two copies of the to_clk_regmap() macro as inline functions to avoid a lot of these. Fixes: ea11dda9e091 ("clk: meson: add regmap clocks") Fixes: 085d7a455444 ("clk: qcom: Add a regmap type clock struct") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20201026161411.3708639-1-arnd@kernel.org Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2020-10-2213-29/+2197
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This contains no changes to the core framework. It is a collection of various clk driver updates. The biggest driver updates in terms of lines of code is the Allwinner driver, closely followed by the Qualcomm and Mediatek drivers. All of those hit high because we add so many lines of clk data. Coming in fourth place is i.MX which also adds a bunch of clk data. This accounts for the new driver additions this time around. Otherwise the patches are lots of little cleanups and fixes for various clk drivers that have baked in linux-next for a while. I suppose one highlight or theme is that more clk drivers are being updated to work as modules, which is interesting to see such critical SoC infrastructure work as a loadable module. New Drivers: - Support qcom SM8150/SM8250 video and display clks - Support Mediatek MT8167 clks - Add clock for CRC block found on vf610 SoCs - Add support for the Renesas R-Car V3U (R8A779A0) SoC - Add support for the VSP for Resizing clock on Renesas RZ/G1H - Support Allwinner A100 SoC clks Removed Drivers: - Remove i.MX21 clock driver, as i.MX21 platform support is being dropped Updates: - Change how qcom's display port clks work - Small non-critical fixes for TI clk driver - Remove various unused variables in clk drivers - Allow Rockchip clk driver to be a module - Remove most __clk_lookup() calls in Samsung drivers (yay!) - Support building i.MX ARMv8 platforms clock driver as module - Some kerneldoc fixes here and there - A couple of minor i.MX clk data corrections - Update audio clock inverter and fdiv2 flag on Amlogic g12 - Make amlogic clk drivers configurable in Kconfig - Fix Renesas VSP clock names to match corrected hardware documentation - Sigma-delta modulation on Allwinner R40 - Various fixes for at91 clk driver - Use semicolons instead of commas in some places - Mark some variables const so they can move to RO memory" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (102 commits) clk: imx8mq: Fix usdhc parents order clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on clk: Restrict CLK_HSDK to ARC_SOC_HSDK clk: at91: sam9x60: support only two programmable clocks clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL clk: ingenic: Use readl_poll_timeout instead of custom loop clk: ingenic: Use to_clk_info() macro for all clocks clk: bcm2835: add missing release if devm_clk_hw_register fails clk: at91: clk-sam9x60-pll: remove unused variable clk: at91: clk-main: update key before writing AT91_CKGR_MOR clk: at91: remove the checking of parent_name clk: clk-prima2: fix return value check in prima2_clk_init() clk: mmp2: Fix the display clock divider base clk: pxa: Constify static struct clk_ops clk: baikal-t1: Mark Ethernet PLL as critical clk: qoriq: modify MAX_PLL_DIV to 32 clk: axi-clkgen: Set power bits for fractional mode clk: axi-clkgen: Add support for fractional dividers ...
| * clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already onStephen Boyd2020-10-201-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the GDSC is enabled out of boot but doesn't have the retain ff bit set we will get confusing results where the registers that are powered by the GDSC lose their contents on the first power off of the GDSC but thereafter they retain their contents. This is because gdsc_init() fails to make sure the RETAIN_FF bit is set when it probes the GDSC the first time and thus powering off the GDSC causes the register contents to be reset. We do set the RETAIN_FF bit the next time we power on the GDSC, see gdsc_enable(), so that subsequent GDSC power off's don't lose register contents state. Forcibly set the bit at device probe time so that the kernel's assumed view of the GDSC is consistent with the state of the hardware. This fixes a problem where the audio PLL doesn't work on sc7180 when the bootloader leaves the lpass_core_hm GDSC enabled at boot (e.g. to make a noise) but critically doesn't set the RETAIN_FF bit. Cc: Douglas Anderson <dianders@chromium.org> Cc: Taniya Das <tdas@codeaurora.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Fixes: 173722995cdb ("clk: qcom: gdsc: Add support to enable retention of GSDCR") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20201017020137.1251319-1-sboyd@kernel.org Reviewed-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org>
| * clk: qcom: Add display clock controller driver for SM8150 and SM8250Jonathan Marek2020-10-133-0/+1117
| | | | | | | | | | | | | | | | | | Add support for the display clock controller found on SM8150 and SM8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Link: https://lore.kernel.org/r/20200927190653.13876-3-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: add video clock controller driver for SM8250Jonathan Marek2020-10-133-0/+379
| | | | | | | | | | | | | | | | | | | | Add support for the video clock controller found on SM8250 based devices. Derived from the downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200923160635.28370-6-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: add video clock controller driver for SM8150Jonathan Marek2020-10-133-0/+286
| | | | | | | | | | | | | | | | | | | | Add support for the video clock controller found on SM8150 based devices. Derived from the downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200923160635.28370-5-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCsKonrad Dybcio2020-10-131-1/+387
| | | | | | | | | | | | | | | | | | | | | | | | This change adds GDSCs, resets and most of the missing clocks to the msm8994 GCC driver. The remaining ones are of local_vote_clk and gate_clk type, which are not yet supported upstream. Also reorder them to match the original downstream driver. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20201005145855.149206-1-konradybcio@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk/qcom: fix spelling typoWang Qing2020-10-131-5/+5
| | | | | | | | | | | | | | | | Modify the comment typo: "compliment" -> "complement". Signed-off-by: Wang Qing <wangqing@vivo.com> Link: https://lore.kernel.org/r/1600930506-394-1-git-send-email-wangqing@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gcc-sdm660: Fix wrong parent_mapKonrad Dybcio2020-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | This was likely overlooked while porting the driver upstream. Reported-by: Pavel Dubrova <pashadubrova@gmail.com> Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200922120909.97203-1-konradybcio@gmail.com Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: dispcc: Update DP clk ops for phy designStephen Boyd2020-09-222-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk. This function should return the rate that can be achieved by the pixel clk in 'struct clk_rate_request::rate' and match the logic similar to what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead the code merely bubbles the rate request up to the parent of the pixel clk and doesn't try to do a rational approximation of the rate that would be achieved by picking some m/n value for the RCG. Let's change this logic so that we can assume the parent clk frequency is fixed (it is because it's the VCO of the DP PLL that is configured based on the link rate) and so that we can calculate what the m/n value will be and adjust the req->rate appropriately. Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200916231202.3637932-10-swboyd@chromium.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gcc-msm8939: remove defined but not used variablesJason Yan2020-09-221-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This addresses the following gcc warning with "make W=1": drivers/clk/qcom/gcc-msm8939.c:610:32: warning: ‘gcc_xo_gpll6_gpll0a_map’ defined but not used [-Wunused-const-variable=] static const struct parent_map gcc_xo_gpll6_gpll0a_map[] = { ^~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/qcom/gcc-msm8939.c:598:32: warning: ‘gcc_xo_gpll6_gpll0_map’ defined but not used [-Wunused-const-variable=] static const struct parent_map gcc_xo_gpll6_gpll0_map[] = { ^~~~~~~~~~~~~~~~~~~~~~ Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Link: https://lore.kernel.org/r/20200911013722.1459387-1-yanaijie@huawei.com Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: ipq8074: make pcie0_rchng_clk_src staticJason Yan2020-09-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This addresses the following sparse warning: drivers/clk/qcom/gcc-ipq8074.c:4325:17: warning: symbol 'pcie0_rchng_clk_src' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Link: https://lore.kernel.org/r/20200921142750.875142-1-yanaijie@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: lpass: Correct goto target in lpass_core_sc7180_probe()Jing Xiangfeng2020-09-101-3/+4
|/ | | | | | | | | | | lpass_core_sc7180_probe() misses to call pm_clk_destroy() and pm_runtime_disable() in error paths. Correct goto target to fix it. This issue is found by code inspection. Signed-off-by: Jing Xiangfeng <jingxiangfeng@huawei.com> Link: https://lore.kernel.org/r/20200827141629.101802-1-jingxiangfeng@huawei.com Fixes: edab812d802d ("clk: qcom: lpass: Add support for LPASS clock controller for SC7180") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clkKonrad Dybcio2020-07-271-0/+3
| | | | | | | | | | Add missing halt_check, hwcg_reg and hwcg_bit properties. These were likely omitted when porting the driver upstream. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200726111215.22361-9-konradybcio@gmail.com Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: gcc-sdm660: Add missing modem resetKonrad Dybcio2020-07-271-0/+1
| | | | | | | | | | This will be required in order to support the modem upstream. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200726111215.22361-2-konradybcio@gmail.com Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: lpass: Add support for LPASS clock controller for SC7180Taniya Das2020-07-243-0/+486
| | | | | | | | | | The Low Power Audio subsystem clocks are required for Audio client to be able to request for the clocks and power domains. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1595606878-2664-5-git-send-email-tdas@codeaurora.org [sboyd@kernel.org: Drop unused ret in probe function] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: gcc: Add support for GCC LPASS clock for SC7180Taniya Das2020-07-241-0/+14
| | | | | | | | | Add the GCC lpass clock which is required to access the LPASS core clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1595606878-2664-4-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: gdsc: Add support to enable retention of GSDCRTaniya Das2020-07-242-0/+13
| | | | | | | | | | Add support for the RETAIN_FF_ENABLE feature which enables the usage of retention registers. These registers maintain their state after disabling and re-enabling a GDSC. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1595606878-2664-2-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Export gdsc_gx_do_nothing_enable() to modulesStephen Boyd2020-07-241-0/+2
| | | | | | | | | | A clk driver can be a module but the gdsc code is in the common module. Export this symbol so that allmodconfig builds keep working. Cc: Jonathan Marek <jonathan@marek.ca> Fixes: 0638226dd095 ("clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc drivers") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200724094025.3261266-1-sboyd@kernel.org
* clk: qcom: Add graphics clock controller driver for SM8250Jonathan Marek2020-07-243-0/+357
| | | | | | | | | | | | | Add support for the graphics clock controller found on SM8250 based devices. This is initially copied from the downstream kernel, but has been modified to more closely match the upstream sc7180 driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-12-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add graphics clock controller driver for SM8150Jonathan Marek2020-07-243-0/+329
| | | | | | | | | | | | | Add support for the graphics clock controller found on SM8150 based devices. This is initially copied from the downstream kernel, but has been modified to more closely match the upstream sc7180 driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-11-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: add common gdsc_gx_do_nothing_enable for gpucc driversJonathan Marek2020-07-244-52/+28
| | | | | | | | | | All gpucc drivers need this, so move it to common code instead of duplicating it in every gpucc driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-10-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: gcc: remove unnecessary vco_table from SM8150Jonathan Marek2020-07-241-10/+0
| | | | | | | | | | The fixed alpha pll ops only use it for clamping in round_rate, which is unnecessary. This is consistent with SM8250 GCC not using vco_table. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-6-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: clk-alpha-pll: use the right PCAL_DONE value for lucid pllJonathan Marek2020-07-242-3/+27
| | | | | | | | | Lucid PCAL_DONE is different from trion. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-5-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: clk-alpha-pll: same regs and ops for trion and lucidJonathan Marek2020-07-243-51/+32
| | | | | | | | | | | | | | | Fixed ops were already identical, this adds support for non-fixed ops by sharing between trion and lucid. This also changes the names for trion ops to be consistent with the rest. Note LUCID_PCAL_DONE is renamed to TRION_PCAL_DONE because it is wrong for lucid, LUCID_PCAL_DONE should be BIT(27). Next patch will address this. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-4-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: clk-alpha-pll: remove unused/incorrect PLL_CAL_VALJonathan Marek2020-07-241-2/+0
| | | | | | | | | | 0x44 isn't a register offset, it is the value that goes into CAL_L_VAL. Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-3-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: gcc: fix sm8150 GPU and NPU clocksJonathan Marek2020-07-241-2/+6
| | | | | | | | | | | | Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it should be a 500us delay and not skip, however this matches what was done for other clocks that had 500us delay in downstream. Fixes: f73a4230d5bb ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20200709135251.643-2-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845Taniya Das2020-07-212-3/+3
| | | | | | | | | | | | | | | | | | | | | | The display gpll0 branch clock inside GCC needs to always be enabled. Otherwise the AHB clk (disp_cc_mdss_ahb_clk_src) for the display clk controller (dispcc) will stop clocking while sourcing from gpll0 when this branch inside GCC is turned off during unused clk disabling. We can never turn this branch off because the AHB clk for the display subsystem is needed to read/write any registers inside the display subsystem including clk related ones. This makes this branch a really easy way to turn off AHB access to the display subsystem and cause all sorts of mayhem. Let's just make the clk ops keep the clk enabled forever and ignore any attempts to disable this clk so that dispcc accesses keep working. Signed-off-by: Taniya Das <tdas@codeaurora.org> Reported-by: Evan Green <evgreen@chromium.org> Link: https://lore.kernel.org/r/1594796050-14511-1-git-send-email-tdas@codeaurora.org Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") [sboyd@kernel.org: Fill out commit text more] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* ipq806x: gcc: add support for child probeAnsuel Smith2020-07-211-1/+1
| | | | | | | | | | Add support for child probing needed for tsens driver that share the same regs of gcc for this platform. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Link: https://lore.kernel.org/r/20200716022817.30439-2-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' staticWei Yongjun2020-07-201-1/+1
| | | | | | | | | | | | | | | | The sparse tool complains as follows: drivers/clk/qcom/clk-cpu-8996.c:341:19: warning: symbol 'cpu_msm8996_clks' was not declared. Should it be static? This variable is not used outside of clk-cpu-8996.c, so this commit marks it static. Fixes: 03e342dc45c9 ("clk: qcom: Add CPU clock driver for msm8996") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200714142155.35085-1-weiyongjun1@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: smd: Add support for MSM8992/4 rpm clocksKonrad Dybcio2020-07-111-0/+171
| | | | | | | | | | Add rpm smd clocks, PMIC and bus clocks which are required on MSM8992, MSM8994 (and APQ variants) for clients to vote on. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623230018.303776-1-konradybcio@gmail.com [sboyd@kernel.org: Fixed up binding numbers] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: ipq8074: Add missing clocks for pcieSivaprakash Murugesan2020-07-111-0/+60
| | | | | | | | | | | Add missing clocks and resets for pcie port0 of ipq8074 devices. Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1593940680-2363-5-git-send-email-sivaprak@codeaurora.org [sboyd@kernel.org: Make freq table static const] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add CPU clock driver for msm8996Loic Poulain2020-07-104-0/+554
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each of the CPU clusters (Power and Perf) on msm8996 are clocked via 2 PLLs, a primary and alternate. There are also 2 Mux'es, a primary and secondary all connected together as shown below +-------+ XO | | +------------------>0 | | | PLL/2 | SMUX +----+ +------->1 | | | | | | | +-------+ | +-------+ | +---->0 | | | | +---------------+ | +----------->1 | CPU clk |Primary PLL +----+ PLL_EARLY | | +------> | +------+-----------+ +------>2 PMUX | +---------------+ | | | | | +------+ | +-->3 | +--^+ ACD +-----+ | +-------+ +---------------+ +------+ | |Alt PLL | | | +---------------------------+ +---------------+ PLL_EARLY The primary PLL is what drives the CPU clk, except for times when we are reprogramming the PLL itself (for rate changes) when we temporarily switch to an alternate PLL. A subsequent patch adds support to switch between primary and alternate PLL during rate changes. The primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. So for frequencies above 600MHz we follow the following path Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between 300MHz and 600MHz we follow Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk ACD stands for Adaptive Clock Distribution and is used to detect voltage droops. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Rajendra Nayak: Initial RFC - https://lkml.org/lkml/2016/9/29/84 Signed-off-by: Ilia Lin <ilialin@codeaurora.org> Ilia Lin: - reworked clock registering - Added clock-tree diagram - non-builtin support - clock notifier on rate change - https://lkml.org/lkml/2018/5/24/123 Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Loic Poulain: - fixed driver remove / clk deregistering - Removed useless memory barriers - devm usage when possible - Fixed Kconfig depends Link: https://lore.kernel.org/r/1593766185-16346-3-git-send-email-loic.poulain@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Fix return value check in apss_ipq6018_probe()Wei Yongjun2020-06-291-2/+2
| | | | | | | | | | | | In case of error, the function dev_get_regmap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200628023055.50608-1-weiyongjun1@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: smd: Add support for MSM8936 rpm clocksVincent Knecht2020-06-221-0/+50
| | | | | | | | Add missing definition of rpm clk for msm8936 soc (also used by msm8939) Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20200613072745.1249003-2-vincent.knecht@mailoo.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: smd: Add support for SDM660 rpm clocksKonrad Dybcio2020-06-221-0/+76
| | | | | | | | | Add rpm smd clocks, PMIC and bus clocks which are required on SDM630/660 (and APQ variants) for clients to vote on. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200622090252.36568-1-konradybcio@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add ipq6018 apss clock controllerSivaprakash Murugesan2020-06-223-0/+118
| | | | | | | | | | | | | The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL and xo which are connected to a mux and enable block. Add support for the mux and enable block which feeds the CPU on ipq6018 devices. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1592800092-20533-5-git-send-email-sivaprak@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: qcom: Add ipq apss pll driverSivaprakash Murugesan2020-06-223-0/+104
| | | | | | | | | | The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL. Add support for the apss pll found on ipq based devices which can support CPU frequencies above 1Ghz. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1592800092-20533-3-git-send-email-sivaprak@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2020-06-1010-40/+4263
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time around we have four lines of diff in the core framework, removing a function that isn't used anymore. Otherwise the main new thing for the common clk framework is that it is selectable in the Kconfig language now. Hopefully this will let clk drivers and clk consumers be testable on more than the architectures that support the clk framework. The goal is to introduce some Kunit tests for the framework. Outside of the core framework we have the usual set of various driver updates and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the largest addition this time around in terms of lines of code. After that the x86 (Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or upcoming SoCs. After that the dirstat shows the usual suspects working on their SoC support by fixing minor bugs, correcting data and converting some of their DT bindings to YAML. Core: - Allow the COMMON_CLK config to be selectable New Drivers: - Clk driver for Baikal-T1 SoCs - Mediatek MT6765 clock support - Support for Intel Agilex clks - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for the new Renesas RZ/G1H (R8A7742) SoC - Add support for Qualcomm's MSM8939 Generic Clock Controller Updates: - Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips - Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - A single minor rounding fix for the legacy Allwinner clock support - A few patches from Abel Vesa as preparation of adding audiomix clock support on i.MX - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3 drivers - Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on aarch64 hardware - A series from Peng Fan to improve i.MX8M clock drivers, using composite clock for core and bus clk slice - Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined bit rates - A couple changes for EMC frequency scaling on Tegra210 - Support for CPU frequency scaling on Tegra20/Tegra30 - New clk gate for CSI test pattern generator on Tegra210 - Regression fixes for Samsung exynos542x and exynos5433 SoCs - Use of fallthrough; attribute for Samsung s3c24xx - Updates and fixup HDMI and video clocks on Meson8b - Fixup reset polarity on Meson8b - Fix GPU glitch free mux switch on Meson gx and g12 - A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2 - Two more conversions of Renesas DT bindings to json-schema - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits) clk: mediatek: Remove ifr{0,1}_cfg_regs structures clk: baikal-t1: remove redundant assignment to variable 'divider' clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible" dt-bindings: clock: Add a missing include to MMP Audio Clock binding dt: Add bindings for IDT VersaClock 5P49V5925 clk: vc5: Add support for IDT VersaClock 5P49V6965 clk: Add Baikal-T1 CCU Dividers driver clk: Add Baikal-T1 CCU PLLs driver dt-bindings: clk: Add Baikal-T1 CCU Dividers binding dt-bindings: clk: Add Baikal-T1 CCU PLLs binding clk: mediatek: assign the initial value to clk_init_data of mtk_mux clk: mediatek: Add MT6765 clock support clk: mediatek: add mt6765 clock IDs dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC CLK: HSDK: CGU: add support for 148.5MHz clock CLK: HSDK: CGU: support PLL bypassing CLK: HSDK: CGU: check if PLL is bypassed first clk: clk-si5341: Add support for the Si5345 series ...
| * clk: qcom: Add missing msm8998 ufs_unipro_core_clk_srcJeffrey Hugo2020-05-281-0/+27
| | | | | | | | | | | | | | | | | | | | ufs_unipro_core_clk_src is required to allow UFS to clock scale for power savings. Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20200528142205.44003-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock ControllerBryan O'Donoghue2020-05-263-0/+3997
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the MSM8939 GCC. The MSM8939 is based on the MSM8916. MSM8939 is compatible in several ways with MSM8916 but, has additional functional blocks added which require additional PLL sources. In some cases functional blocks from the MSM8916 have different clock sources or different supported frequencies. Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-arm-msm@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Co-developed-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vincent Knecht <vincent.knecht@mailoo.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lkml.kernel.org/r/20200517131348.688405-3-bryan.odonoghue@linaro.org Tested-by: Konrad Dybcio <konradybcio@gmail.com> [sboyd@kernel.org: Drop ret in probe function to remove unused variable] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gcc: Add support for Secure control source clockTaniya Das2020-05-261-0/+21
| | | | | | | | | | | | | | | | | | The secure controller driver requires to request for various frequencies on the source clock, thus add support for the same. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1589709861-27580-4-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gcc: Add support for a new frequency for SC7180Taniya Das2020-05-261-36/+37
| | | | | | | | | | | | | | | | | | | | | | There is a requirement to support 51.2MHz from GPLL6 for qup clocks, thus update the frequency table and parent data/map to use the GPLL6 source PLL. Fixes: 17269568f7267 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1589709861-27580-2-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gcc: Add missing UFS clocks for SM8150Vinod Koul2020-05-141-0/+84
| | | | | | | | | | | | | | | | | | | | Add the missing ufs card and ufs phy clocks for SM8150. They were missed in earlier addition of clock driver. Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200513065420.32735-2-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gcc: Add GPU and NPU clocks for SM8150Vinod Koul2020-05-141-0/+64
| | | | | | | | | | | | | | | | | | | | Add the GPU and NPU clocks for SM8150. They were missed in earlier addition of clock driver. Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200513065420.32735-1-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdscBjorn Andersson2020-05-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The GPU_GX GDSC depends on both GPU GDSC being enabled and that the VDD_GX rail is powered, so update the description of the node to cover these requirements. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20200417070044.1376212-3-bjorn.andersson@linaro.org Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: gdsc: Handle GDSC regulator suppliesBjorn Andersson2020-05-142-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain GDSCs, such as the GPU_GX on MSM8996, requires that the upstream regulator supply is powered in order to be turned on. It's not guaranteed that the bootloader will leave these supplies on and the driver core will attempt to enable any GDSCs before allowing the individual drivers to probe defer on the PMIC regulator driver not yet being present. So the gdsc driver needs to be made aware of supplying regulators and probe defer on their absence, and it needs to enable and disable the regulator accordingly. Voltage adjustments of the supplying regulator are deferred to the client drivers themselves. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20200417070044.1376212-2-bjorn.andersson@linaro.org Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: qcom: msm8916: Fix the address location of pll->config_regBryan O'Donoghue2020-04-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the process of debugging a processor derived from the msm8916 which we found the new processor was not starting one of its PLLs. After tracing the addresses and writes that downstream was doing and comparing to upstream it became obvious that we were writing to a different register location than downstream when trying to configure the PLL. This error is also present in upstream msm8916. As an example clk-pll.c::clk_pll_recalc_rate wants to write to pll->config_reg updating the bit-field POST_DIV_RATIO. That bit-field is defined in PLL_USER_CTL not in PLL_CONFIG_CTL. Taking the BIMC PLL as an example lm80-p0436-13_c_qc_snapdragon_410_processor_hrd.pdf 0x01823010 GCC_BIMC_PLL_USER_CTL 0x01823014 GCC_BIMC_PLL_CONFIG_CTL This pattern is repeated for gpll0, gpll1, gpll2 and bimc_pll. This error is likely not apparent since the bootloader will already have initialized these PLLs. This patch corrects the location of config_reg from PLL_CONFIG_CTL to PLL_USER_CTL for all relevant PLLs on msm8916. Fixes commit 3966fab8b6ab ("clk: qcom: Add MSM8916 Global Clock Controller support") Cc: Georgi Djakov <georgi.djakov@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lkml.kernel.org/r/20200329124116.4185447-1-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: gcc: Fix parent for gpll0_out_evenVinod Koul2020-05-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Documentation says that gpll0 is parent of gpll0_out_even, somehow driver coded that as bi_tcxo, so fix it Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") Reported-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200521052728.2141377-1-vkoul@kernel.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: sm8250 gcc depends on QCOM_GDSCJonathan Marek2020-05-261-0/+1
|/ | | | | | | | | | The driver will always fail to probe without QCOM_GDSC, so select it. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lkml.kernel.org/r/20200523040947.31946-1-jonathan@marek.ca Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Fixes: 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-12 13:09:09 +0000