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* clk: qcom: gcc-x1e80100: Replace of_device.h with explicit includesStephen Rothwell2024-01-191-1/+2
| | | | | | | | | | | | | | | | | The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. of_device.h isn't needed, but mod_devicetable.h and platform_device.h were implicitly included. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20231211160510.0aef871b@canb.auug.org.au [robh: Redo commit msg] Signed-off-by: Rob Herring <robh@kernel.org>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2024-01-1219-63/+19232
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Only a couple new SoCs have support added this time, primarily for Qualcomm SM8650 based on the diffstat. Otherwise this is a collection of non-critical fixes and cleanups to various clk drivers and their DT bindings. Nothing is changed in the core clk framework this time, although there's a patch to fix a basic clk type initialization function. In general, this pile looks to be on the smaller side. New Drivers: - Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Mediatek MT7988 SoC clocks Updates: - Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP - Support for stm32mp25 clks - Add glitch free PLL setting support to si5351 clk driver - Add DSI clocks on Amlogic g12/sm1 - Add CSI and ISP clocks on Amlogic g12/sm1 - Document bindings for i.MX93 ANATOP clock driver - Free clk_node in i.MX SCU driver for resource with different owner - Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15 - Fix the name of the fvco in i.MX pll14xx by renaming it to fout - Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs - Reuse reset functionality in the Renesas RZ/G2L clock driver - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 - Cleanup variable init in Allwinner nkm module - Convert various DT bindings to YAML - A few kernel-doc fixes for Samsung SoC clock controllers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings ...
| * clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL configKonrad Dybcio2023-12-191-0/+8
| | | | | | | | | | | | | | | | | | These values were missing. Add them. Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231219-topic-8650_clks-v1-2-5672bfa0eb05@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL configKonrad Dybcio2023-12-191-0/+2
| | | | | | | | | | | | | | | | | | These values were missing. Add them. Fixes: 8676fd4f3874 ("clk: qcom: add the SM8650 GPU Clock Controller driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231219-topic-8650_clks-v1-1-5672bfa0eb05@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: dispcc-sm8550: Use the correct PLL configuration functionKonrad Dybcio2023-12-191-2/+2
| | | | | | | | | | | | | | | | | | | | To ensure that all fields (particularly CAL_L and CAL_L_RINGOSC) are filled properly, use the correct prepare function for OLE PLLs. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-9-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: dispcc-sm8550: Update disp PLL settingsKonrad Dybcio2023-12-191-0/+8
| | | | | | | | | | | | | | | | | | | | The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-8-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: gpucc-sm8550: Update GPU PLL settingsKonrad Dybcio2023-12-191-3/+3
| | | | | | | | | | | | | | | | | | | | The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: bfae40744b33 ("clk: qcom: gpucc-sm8550: Add support for graphics clock controller") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-7-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: gcc-sm8550: Mark RCGs shared where applicableKonrad Dybcio2023-12-191-43/+43
| | | | | | | | | | | | | | | | | | The vast majority of shared RCGs were not marked as such. Fix it. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-6-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCsKonrad Dybcio2023-12-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Following other recent Qualcomm platforms, describe this register and the corresponding mask for the PCIe (and _phy) GDSCs. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-5-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votableKonrad Dybcio2023-12-191-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe GDSCs on most Qualcomm platforms expect the OS to always consider collapse requests as successful. This also concerns SM8550. Add the VOTABLE flag to the GDSCs in question to comply with these expectations. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-4-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flagKonrad Dybcio2023-12-191-8/+8
| | | | | | | | | | | | | | | | | | | | All of the 8550's GCC GDSCs can and should use the retain registers so as not to lose their state when entering lower power modes. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-3-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: camcc-sc8280xp: Prevent error pointer dereferenceDan Carpenter2023-12-151-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | If "regmap" is an error pointer then calling regmap_update_bits() will crash. We only need to call regmap_update_bits() if we had written to it earlier. Fixes: ff93872a9c61 ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/210d48ce-6ebc-4a6b-b30f-866d10d41a16@moroto.mountain Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: videocc-sm8150: Add runtime PM supportSatya Priya Kakitapalli2023-12-151-2/+18
| | | | | | | | | | | | | | | | | | | | Add runtime PM support to ensure the supply rails are enabled when necessary. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-4-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: videocc-sm8150: Add missing PLL config propertySatya Priya Kakitapalli2023-12-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | When the driver was ported upstream, PLL test_ctl_hi1 register value was omitted. Add it to ensure the PLLs are fully configured. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-3-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: videocc-sm8150: Update the videocc resetsSatya Priya Kakitapalli2023-12-151-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add all the available resets for the video clock controller on sm8150. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-2-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: rpmh: Add support for X1E80100 rpmh clocksRajendra Nayak2023-12-071-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the RPMH clocks present in X1E80100 SoC Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-5-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: Add Global Clock controller (GCC) driver for X1E80100Rajendra Nayak2023-12-073-0/+6818
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the global clock controller found on X1E80100 based devices. Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-3-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000Imran Shaik2023-12-073-0/+2466
| | | | | | | | | | | | | | | | | | Add ECPRI Clock Controller (ECPRICC) support for QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231123064735.2979802-4-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: branch: Add mem ops support for branch2 clocksTaniya Das2023-12-072-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | Add the support for mem ops implementation to handle the sequence of enable/disable of the memories in ethernet PHY, prior to enable/disable of the respective clocks, which helps retain the respecive block's register contents. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231123064735.2979802-3-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: gpucc-sm8150: Update the gpu_cc_pll1 configSatya Priya Kakitapalli2023-12-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | Update the test_ctl_hi_val and test_ctl_hi1_val of gpu_cc_pll1 as per latest HW recommendation. Fixes: 0cef71f2ccc8 ("clk: qcom: Add graphics clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231122042814.4158076-1-quic_skakitap@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: rpmh: add clocks for SM8650Neil Armstrong2023-12-071-0/+34
| | | | | | | | | | | | | | | | | | | | Add RPMH Clocks for the SM8650 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-11-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: add the SM8650 GPU Clock Controller driverNeil Armstrong2023-12-073-0/+670
| | | | | | | | | | | | | | | | | | Add Graphics Clock Controller (GPUCC) support for SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-10-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: add the SM8650 Display Clock Controller driverNeil Armstrong2023-12-073-0/+1821
| | | | | | | | | | | | | | | | | | Add Display Clock Controller (DISPCC) support for SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-9-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: add the SM8650 TCSR Clock Controller driverNeil Armstrong2023-12-073-0/+191
| | | | | | | | | | | | | | | | | | | | Add TCSR Clock Controller support for SM8650 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-8-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: add the SM8650 Global Clock Controller driver, part 2Neil Armstrong2023-12-073-0/+345
| | | | | | | | | | | | | | | | | | Add Global Clock Controller (GCC) driver plumbing for the SM8650 platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-7-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: add the SM8650 Global Clock Controller driver, part 1Neil Armstrong2023-12-071-0/+3514
| | | | | | | | | | | | | | | | | | | | Add Global Clock Controller (GCC) tables for the SM8650 platform, the driver plumbing will be added afterwards. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-6-761a6fadb4c0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: gcc-msm8939: Add missing CSI2 related clocksVincent Knecht2023-12-071-3/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When adding in the indexes for this clock-controller we missed GCC_CAMSS_CSI2_AHB_CLK, GCC_CAMSS_CSI2_CLK, GCC_CAMSS_CSI2PHY_CLK, GCC_CAMSS_CSI2PIX_CLK and GCC_CAMSS_CSI2RDI_CLK. Add them in now and rename ftbl_gcc_camss_csi0_1_clk to account for csi2 also using it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org> Link: https://lore.kernel.org/r/20231029061948.505883-2-vincent.knecht@mailoo.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCCBryan O'Donoghue2023-12-073-0/+3054
| | | | | | | | | | | | | | | | | | Add the sc8280xp CAMCC driver which follows the sdm845 CAMCC lineage with additional CCI and IFE blocks and more granular clock parentage. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231026105345.3376-4-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| * clk: qcom: apss-ipq-pll: add support for IPQ5018Gokul Sriram Palanisamy2023-12-021-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | IPQ5018 APSS PLL is of type Stromer. Reuse Stromer Plus PLL offsets, add configuration values and the compatible. Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230925102826.405446-3-quic_gokulsri@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: Fix SM_CAMCC_8550 dependenciesJagadeesh Kona2023-11-271-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | SM_GCC_8550 depends on ARM64 but it is selected by SM_CAMCC_8550, which should have the same dependencies as SM_GCC_8550 to avoid the below Kconfig warning reported by kernel test robot. WARNING: unmet direct dependencies detected for SM_GCC_8550 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n]) Selected by [y]: - SM_CAMCC_8550 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] Fixes: ccc4e6a061a2 ("clk: qcom: camcc-sm8550: Add camera clock controller driver for SM8550") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202311062309.XugQH7AH-lkp@intel.com/ Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Link: https://lore.kernel.org/r/20231107064545.13120-1-quic_jkona@quicinc.com Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* Merge branch 'clk-cleanup' into clk-nextStephen Boyd2023-10-306-48/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-cleanup: clk: si521xx: Increase stack based print buffer size in probe clk: Use device_get_match_data() clk: cdce925: Extend match support for OF tables clk: si570: Simplify probe clk: si5351: Simplify probe clk: rs9: Use i2c_get_match_data() instead of device_get_match_data() clk: clk-si544: Simplify probe() and is_valid_frequency() clk: si521xx: Use i2c_get_match_data() instead of device_get_match_data() clk: npcm7xx: Fix incorrect kfree clk: at91: remove unnecessary conditions clk: ti: fix double free in of_ti_divider_clk_setup() clk: keystone: pll: fix a couple NULL vs IS_ERR() checks clk: ralink: mtmips: quiet unused variable warning clk: gate: fix comment typo and grammar clk: asm9620: Remove 'hw' local variable that isn't checked
| * clk: Use device_get_match_data()Rob Herring2023-10-236-48/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use preferred device_get_match_data() instead of of_match_device() to get the driver match data. With this, adjust the includes to explicitly include the correct headers. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231006213959.334439-1-robh@kernel.org Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #msm part Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # Samsung Acked-by: David Lechner <david@lechnology.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock providerKathiravan Thirumoorthy2023-10-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the kernel is booting up, APSS PLL will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured and select the rate based on the opp table and the source will be changed to APSS_PLL_EARLY. Without this patch, CPU Freq driver reports that CPU is running at 24MHz instead of the 800MHz. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-7-c8ceb1a37680@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocksKathiravan Thirumoorthy2023-10-211-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | GPLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-5-c8ceb1a37680@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocksKathiravan Thirumoorthy2023-10-211-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks. ---- Changes in V2: - No changes Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574") Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-4-c8ceb1a37680@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocksKathiravan Thirumoorthy2023-10-211-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks. ---- Changes in V2: - New patch Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-3-c8ceb1a37680@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocksKathiravan Thirumoorthy2023-10-211-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL clocks. Cc: stable@vger.kernel.org Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-2-c8ceb1a37680@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocksKathiravan Thirumoorthy2023-10-211-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL clocks. Cc: stable@vger.kernel.org Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-1-c8ceb1a37680@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: gcc-ipq6018: add QUP6 I2C clockRobert Marko2023-10-211-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | QUP6 I2C clock is listed in the dt bindings but it was never included in the GCC driver. So lets add support for it, it is marked as criticial as it is used by RPM to communicate to the external PMIC over I2C so this clock must not be disabled. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231021115545.229060-1-robimarko@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pllVaradarajan Narayanan2023-10-211-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stromer Plus PLL found on IPQ53xx doesn't support dynamic frequency scaling. To achieve the same, we need to park the APPS PLL source to GPLL0, re configure the PLL and then switch the source to APSS_PLL_EARLY. To support this, register a clock notifier to get the PRE_RATE and POST_RATE notification. Change the APSS PLL source to GPLL0 when PRE_RATE notification is received, then configure the PLL and then change back the source to APSS_PLL_EARLY. Additionally, not all SKUs of IPQ53xx support scaling. Hence, do the above to the SKUs that support scaling. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/49422d258d67d33a2547fbb7f4f6e72d489c2301.1697781921.git.quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_configVaradarajan Narayanan2023-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The earlier 'l' value of 0x3e is for 1.5GHz. Not all SKUs support this frequency. Hence set it to 0x2d to get 1.1GHz which is supported in all SKUs. The frequency can still increase above this initial configuration made here when the cpufreq driver picks a different OPP. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Fixes: c7ef7fbb1ccf ("clk: qcom: apss-ipq-pll: add support for IPQ5332") Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/00e6be6cb9cee56628123a64ade118d0a752018b.1697781921.git.quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pllVaradarajan Narayanan2023-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The set rate and determine rate operations are different between Stromer and Stromer Plus PLLs. Since the programming sequence is different, the PLLs dont get configured properly and random, inexplicable crash/freeze is seen. Hence, use stromer plus ops for ipq_pll_stromer_plus. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Fixes: c7ef7fbb1ccf ("clk: qcom: apss-ipq-pll: add support for IPQ5332") Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/c86ecaa23dc4f39650bcf4a3bd54a617a932e4fd.1697781921.git.quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: clk-alpha-pll: introduce stromer plus opsVaradarajan Narayanan2023-10-212-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | Stromer plus APSS PLL does not support dynamic frequency scaling. To switch between frequencies, we have to shut down the PLL, configure the L and ALPHA values and turn on again. So introduce the separate set of ops for Stromer Plus PLL. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/2affa6c63ff0c4342230623a7d4eef02ec7c02d4.1697781921.git.quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEMVaradarajan Narayanan2023-10-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The config IPQ_APSS_6018 should depend on QCOM_SMEM, to avoid the following error reported by 'kernel test robot' loongarch64-linux-ld: drivers/clk/qcom/apss-ipq6018.o: in function `apss_ipq6018_probe': >> apss-ipq6018.c:(.text+0xd0): undefined reference to `qcom_smem_get_soc_id' Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller") Reported-by: kernel test robot <yujie.liu@intel.com> Closes: https://lore.kernel.org/r/202310181650.g8THtfsm-lkp@intel.com/ Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/f4c4d65a7cb71e807d6d472c63c7718408c8f5f0.1697781921.git.quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: videocc-sm8550: switch to clk_lucid_ole_pll_configureDmitry Baryshkov2023-10-211-6/+4
| | | | | | | | | | | | | | | | | | | | | | Instead of manually specifying the RINGOSC_CAL_L and CAL_L values in the alpha_pll_config.l field, use the proper clk_lucid_ole_pll_configure() function to configure the PLL. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231016084356.1301854-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configureDmitry Baryshkov2023-10-211-6/+4
| | | | | | | | | | | | | | | | | | | | | | Instead of manually specifying the RINGOSC_CAL_L and CAL_L values in the alpha_pll_config.l field, use the proper clk_lucid_ole_pll_configure() function to configure the PLL. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231016084356.1301854-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: Replace of_device.h with explicit includesRob Herring2023-10-213-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other and pull in various other headers. In preparation to fix this, adjust the includes for what is actually needed. of_device.h isn't needed, but mod_devicetable.h and platform_device.h were implicitly included by it. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231010205710.1585232-1-robh@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnectKonrad Dybcio2023-10-211-4/+12
| | | | | | | | | | | | | | | | | | | | | | As it turns out, it's yet another interconnect bus clock. Move it there. See [1] for reference. [1] https://android.googlesource.com/kernel/msm-extra/devicetree/+/02f8c342b23c20a5cf967df649814be37a08227c%5E%21/#F0 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230726-topic-icc_coeff-v4-10-c04b60caa467@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: cbf-msm8996: Convert to platform remove callback returning voidUwe Kleine-König2023-10-211-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Eventually after all drivers are converted, .remove_new() is renamed to .remove(). qcom_msm8996_cbf_icc_remove() returned zero unconditionally. After changing this function to return void instead, the driver can be converted trivially to use .remove_new(). Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230911151548.672485-1-u.kleine-koenig@pengutronix.de Signed-off-by: Bjorn Andersson <andersson@kernel.org>
* | clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_srcDanila Tikhonov2023-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg didn't update its configuration" error. Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") Tested-by: Arseniy Velikanov <adomerlee@gmail.com> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230913175612.8685-1-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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