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path: root/drivers/clk/renesas
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* clk: renesas: rcar-gen3: Add RPC clocksSergei Shtylyov2019-02-052-0/+105
* clk: renesas: rcar-gen3: Add spinlockSergei Shtylyov2019-01-251-0/+8
* clk: renesas: rcar-gen3: Factor out cpg_reg_modify()Sergei Shtylyov2019-01-251-18/+20
* clk: renesas: r8a774c0: Correct parent clock of DUGeert Uytterhoeven2019-01-241-2/+2
* clk: renesas: r8a774a1: Add missing CANFD clockFabrizio Castro2019-01-211-0/+2
* clk: renesas: r8a774c0: Add missing CANFD clockFabrizio Castro2019-01-211-0/+4
* Merge branch 'clk-of' into clk-nextStephen Boyd2018-12-141-1/+1
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| * clk: Use of_node_name_eq for node name comparisonsRob Herring2018-12-141-1/+1
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*-. | Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and '...Stephen Boyd2018-12-149-34/+58
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| * | Merge tag 'clk-renesas-for-v4.21-tag2' of git://git.kernel.org/pub/scm/linux/...Stephen Boyd2018-12-078-33/+46
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| | * | clk: renesas: rcar-gen3: Add HS400 quirk for SD clockNiklas Söderlund2018-12-071-7/+26
| | * | clk: renesas: rcar-gen3: Add documentation for SD clocksNiklas Söderlund2018-12-071-5/+5
| | * | clk: renesas: rcar-gen3: Set state when registering SD clocksNiklas Söderlund2018-12-071-12/+4
| | * | clk: renesas: r8a77995: Simplify PLL3 multiplier/dividerGeert Uytterhoeven2018-12-041-2/+2
| | * | clk: renesas: r8a77995: Add missing CPEX clockGeert Uytterhoeven2018-12-041-1/+2
| | * | clk: renesas: r8a77995: Remove non-existent SSP clocksGeert Uytterhoeven2018-12-041-1/+0
| | * | clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocksGeert Uytterhoeven2018-12-041-3/+0
| | * | clk: renesas: r8a77995: Correct parent clock of DUGeert Uytterhoeven2018-12-041-2/+2
| | * | clk: renesas: r8a77990: Correct parent clock of DUTakeshi Kihara2018-12-041-2/+2
| | * | clk: renesas: r8a77970: Add CPEX clockGeert Uytterhoeven2018-12-041-0/+1
| | * | clk: renesas: r8a77965: Add CPEX clockGeert Uytterhoeven2018-12-041-0/+1
| | * | clk: renesas: r8a7796: Add CPEX clockGeert Uytterhoeven2018-12-041-0/+1
| | * | clk: renesas: r8a7795: Add CPEX clockGeert Uytterhoeven2018-12-041-0/+1
| | * | clk: renesas: r8a774a1: Add CPEX clockGeert Uytterhoeven2018-12-041-0/+1
| * | | clk: renesas: Mark rza2_cpg_clk_register staticStephen Boyd2018-11-291-1/+1
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| * | clk: renesas: r7s9210: Add USB clocksChris Brandt2018-11-131-0/+2
| * | clk: renesas: r8a77970: Add RPC clocksSergei Shtylyov2018-11-051-0/+4
| * | clk: renesas: r7s9210: Add SDHI clocksChris Brandt2018-11-051-0/+5
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* / clk: renesas: Remove usage of CLK_IS_BASICStephen Boyd2018-12-105-8/+8
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* Merge branch 'clk-renesas' into clk-nextStephen Boyd2018-10-1818-168/+1333
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| * clk: renesas: r7s9210: Add SPI clocksChris Brandt2018-09-281-0/+3
| * clk: renesas: r7s9210: Move table update to separate functionChris Brandt2018-09-261-45/+50
| * clk: renesas: r7s9210: Convert some clocks to earlyChris Brandt2018-09-261-6/+26
| * clk: renesas: cpg-mssr: Add early clock supportChris Brandt2018-09-262-21/+89
| * clk: renesas: r8a77970: Add TPU clockSergei Shtylyov2018-09-251-0/+1
| * clk: renesas: r8a77990: Fix incorrect PLL0 divider in commentGeert Uytterhoeven2018-09-251-2/+2
| * clk: renesas: cpg-mssr: Add r8a774c0 supportFabrizio Castro2018-09-195-0/+299
| * clk: renesas: r8a7743: Add r8a7744 supportBiju Das2018-09-193-2/+18
| * clk: renesas: cpg-mssr: Add R7S9210 supportChris Brandt2018-09-115-12/+277
| * clk: renesas: r8a77970: Add TMU clocksSergei Shtylyov2018-09-111-0/+5
| * clk: renesas: r8a77970: Add CMT clocksSergei Shtylyov2018-09-111-0/+4
| * clk: renesas: r9a06g032: Fix UART34567 clock ratePhil Edworthy2018-09-111-1/+2
| * clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHISergei Shtylyov2018-09-032-2/+67
| * clk: renesas: r8a77980: Add CMT clocksSergei Shtylyov2018-09-031-0/+4
| * clk: renesas: r8a77990: Add missing I2C7 clockGeert Uytterhoeven2018-08-311-0/+1
| * clk: renesas: r8a77965: Add FDP clockHoan Nguyen An2018-08-281-0/+1
| * clk: renesas: cpg-mssr: Add r8a774a1 supportBiju Das2018-08-275-0/+336
| * clk: renesas: r8a77965: Add SATA clockTakeshi Kihara2018-08-271-0/+1
| * clk: renesas: r8a77980: Add RCLK for watchdog timerGeert Uytterhoeven2018-08-271-0/+4
| * clk: renesas: rcar-gen3: Add support for mode pin clock selectionGeert Uytterhoeven2018-08-272-10/+13
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 19:20:45 +0000