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* | clk: renesas: rzg2l: Add read only versions of the clk macrosPhil Edworthy2022-05-053-6/+12
| | | | | | | | | | | | | | | | This just makes the clk tables easier to read. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-7-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy2022-05-053-22/+19
| | | | | | | | | | | | | | | | | | | | | | We only ever use ARRAY_SIZE() to populate the number of parents, so move this into the macro to always detect it automatically. This also makes the tables of clocks a little simpler. Similarly for the DEF_SD_MUX macro. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-6-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven2022-05-051-1/+1
| | | | | | | | | | | | | | | | | | Fix a typo in the name of the "ostm1_pclk" clock. This change has no run-time impact. Fixes: 161450134ae9bab3 ("clk: renesas: r9a07g044: Add OSTM clock and reset entries") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be
* | clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das2022-05-051-0/+6
| | | | | | | | | | | | | | | | Add clock and reset entries for ADC block in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das2022-05-051-0/+6
| | | | | | | | | | | | | | | | Add TSU clock and reset entry to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das2022-05-051-0/+9
| | | | | | | | | | | | | | | | Add RSPI{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus ↵Biju Das2022-05-051-0/+18
| | | | | | | | | | | | | | | | | | | | Controller Add clock and reset entries for SPI Multi I/O Bus Controller. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das2022-05-051-1/+16
| | | | | | | | | | | | | | | | Add DSI clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das2022-05-051-1/+8
| | | | | | | | | | | | | | | | Add LCDC clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g044: Add M4 Clock supportBiju Das2022-05-051-1/+18
| | | | | | | | | | | | | | | | Add support for M4 clock which is sourced from pll2_533_div2. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g044: Add M3 Clock supportBiju Das2022-05-051-1/+4
| | | | | | | | | | | | | | | | | | Add support for M3 clock which is sourced from DSI divider connected to PLL5_4 mux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das2022-05-051-1/+4
| | | | | | | | | | | | | | | | Add support for {M2, M2_DIV2} clocks which is sourced from pll3_533. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g044: Add M1 clock supportBiju Das2022-05-051-1/+10
| | | | | | | | | | | | | | | | Add support for M1 clock which is sourced from FOUTPOSTDIV. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: rzg2l: Add DSI divider clk supportBiju Das2022-05-052-0/+136
| | | | | | | | | | | | | | | | | | | | | | M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB) This patch add support for DSI divider clk by combining DSIDIVA and DSIDIVB. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das2022-05-052-0/+103
| | | | | | | | | | | | | | | | | | Add PLL5_4 clk mux support to select clock from clock sources FOUTPOSTDIV and FOUT1PH0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das2022-05-052-0/+235
| | | | | | | | | | | | | | | | | | | | | | | | PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules. The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced from DSI divider which is connected to PLL5_4 MUX. This patch adds support for generating FOUTPOSTDIV clk. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda2022-04-295-0/+231
| | | | | | | | | | | | | | | | Initial CPG support for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4Yoshihiro Shimoda2022-04-294-16/+24
| | | | | | | | | | | | | | | | R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220425064201.459633-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das2022-04-281-0/+10
| | | | | | | | | | | | | | | | Add WDT{0,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das2022-04-281-0/+9
| | | | | | | | | | | | | | | | Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das2022-04-281-0/+5
| | | | | | | | | | | | | | | | Add clock and reset entries for CANFD in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das2022-04-281-0/+12
| | | | | | | | | | | | | | | | Add clock/reset entries for USB PHY control, USB2.0 host and device. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das2022-04-281-0/+20
| | | | | | | | | | | | | | | | Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das2022-04-281-0/+12
| | | | | | | | | | | | | | | | Add I2C{0,1,2,3} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a06g032: Fix the RTC hclock descriptionMiquel Raynal2022-04-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It needs to be un-gated, but also a reset must be released and an idle flag should also be disabled. The driver already supports all these operations, so update the description of the RTC hclock to fit these requirements. Fixes: 4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220421090016.79517-3-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r8a779f0: Add UFS clockYoshihiro Shimoda2022-04-251-0/+1
| | | | | | | | | | | | | | | | | | Add the module clock used by the UFS host controller on the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220411124932.3765571-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add SDHI clock and reset entriesBiju Das2022-04-131-0/+35
| | | | | | | | | | | | | | | | | | Add SDHI{0,1} mux, clock and reset entries to CPG driver Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402074626.25624-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add GbEthernet clock/resetBiju Das2022-04-131-0/+10
| | | | | | | | | | | | | | | | | | Add ETH{0,1} clock/reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402074626.25624-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add ethernet clock sourcesBiju Das2022-04-131-0/+13
| | | | | | | | | | | | | | | | | | | | Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402074626.25624-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: r9a07g043: Add GPIO clock and reset entriesBiju Das2022-04-131-0/+5
| | | | | | | | | | | | | | | | | | Add GPIO clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402074626.25624-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: Add support for RZ/G2UL SoCBiju Das2022-04-135-1/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are not present on RZ/G2UL. This patch adds minimal clock and reset entries required to boot the system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* | clk: renesas: Move RPC core clocksGeert Uytterhoeven2022-04-1312-57/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | The RPC and RPCD2 core clocks were added to the sections for internal core clocks, while they are core clock outputs, visible from DT. Move them to the correct sections. Rename the ".rpc" clock on R-Car S4 to "rpc". Fixup nearby whitespace to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be
* | clk: renesas: rzg2l: Simplify multiplication/shift logicGeert Uytterhoeven2022-04-131-1/+1
| | | | | | | | | | | | | | | | | | "a * (1 << b)" == "a << b". No change in generated code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/71e1cf2e30fb2d7966fc8ec6bab23eb7e24aa1c4.1645460687.git.geert+renesas@glider.be
* | clk: renesas: r8a77995: Add RPC clocksGeert Uytterhoeven2022-04-112-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Describe the various clocks used by the SPI Multi I/O Bus Controller (RPC-IF) on the R-Car D3 SoC: RPCSRC internal clock, RPC{,D2} clocks derived from it, and RPC-IF module clock. The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car E3, but uses a different pre-divider for the PLL0 parent. Add a new macro to describe it, reusing the existing clock type for R-Car E3. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/3fd1e886b7737cd0e199603bae81d01be9dcf3aa.1648546700.git.geert+renesas@glider.be
* | clk: renesas: r8a77990: Add RPC clocksGeert Uytterhoeven2022-04-111-0/+9
| | | | | | | | | | | | | | | | | | | | Describe the various clocks used by the SPI Multi I/O Bus Controller (RPC-IF) on the R-Car E3 SoC: RPCSRC internal clock, RPC{,D2} clocks derived from it, and RPC-IF module clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/3295013f27f1e4b8fbf3f79b950d65157ea95ef2.1648546700.git.geert+renesas@glider.be
* | clk: renesas: rzg2l: Remove unused notifiersPhil Edworthy2022-04-041-2/+0
|/ | | | | | | | notifiers is not used. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220304143241.8523-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779f0: Add PFC clockGeert Uytterhoeven2022-02-221-0/+1
| | | | | | | | | | | Add the module clock used by the Pin Function (PFC/GPIO) controller on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/4ef3d3dfe714ad75112e4886efea0b66e40a33bc.1645457502.git.geert+renesas@glider.be
* clk: renesas: r8a779f0: Add I2C clocksGeert Uytterhoeven2022-02-221-0/+6
| | | | | | | | | | | Add the module clocks used by the I2C Bus Interfaces on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/e4dcee5f6f521dccd7ac7f2fb6c86cfe4a24d032.1643898820.git.geert+renesas@glider.be
* clk: renesas: r8a779f0: Add WDT clockGeert Uytterhoeven2022-02-221-0/+9
| | | | | | | | | | | Add the module clock used by the RCLK Watchdog Timer (RWDT) on the Renesas R-Car S4-8 (r8a779f0) SoC. Mark it as a critical clock, to ensure uninterrupted watchdog operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/8d9b280065a663f2cf31db7b21a010aa781a0af1.1642525158.git.geert+renesas@glider.be
* clk: renesas: r8a779f0: Fix RSW2 clock dividerGeert Uytterhoeven2022-02-221-1/+1
| | | | | | | | | | | | | | According to Section 8.1.2 Figure 8.1.1 ("Block Diagram of CPG"), Note 22 ("RSW2 divider"), and Table 8.1.4d ("Lists of CPG clocks generated from CPGMA1"), the RSwitch2 and PCI Express clock is generated from PLL5 by dividing by two, followed by the RSW2 divider. As PLL5 runs at 3200 MHz, and RSW2 is fixed to 320 MHz, the RSW2 divider must be 5. Correct the parent and the fixed divider. Fixes: 24aaff6a6ce4c4de ("clk: renesas: cpg-mssr: Add support for R-Car S4-8") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/d6a406f31e6f02f892e0253f4e8a9a2f68fd652e.1641566003.git.geert+renesas@glider.be
* clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoCBiju Das2022-02-105-191/+250
| | | | | | | | | | | | | | | | The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779a0: Add CANFD module clockUlrich Hecht2022-01-241-0/+1
| | | | | | | | Adds "canfd0" to mod clocks. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20220111162231.10390-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3Lad Prabhakar2022-01-241-2/+2
| | | | | | | | | | | | | | | As per the HW manual (Rev.1.00 Sep, 2021) PLL2 and PLL3 should be 1600 MHz, but with current multiplier and divider values this resulted to 1596 MHz. This patch updates the multiplier and divider values for PLL2 and PLL3 so that we get the exact (1600 MHz) values. Fixes: 17f0ff3d49ff1 ("clk: renesas: Add support for R9A07G044 SoC") Suggested-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211223093223.4725-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a7799[05]: Add MLP clocksNikita Yushchenko2022-01-242-0/+2
| | | | | | | | | | | | | | Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs. Similar to other R-Car Gen3 SoC, exact information on the parents of MLP clocks on E3 and D3 is not available. However, since the parents of these clocks are not anyhow software-controllable, the only harm from this is inexact information exported via debugfs. So just keep the parent set in the same way as with other Gen3 SoCs. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Link: https://lore.kernel.org/r/20211225193957.2195012-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r8a779f0: Add SYS-DMAC clocksYoshihiro Shimoda2022-01-241-0/+2
| | | | | | | | Add SYS-DMAC clocks on r8a779f0. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211221052423.597283-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a07g044: Add GPU clock and reset entriesBiju Das2021-12-081-0/+9
| | | | | | | | | Add GPU clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a07g044: Add mux and divider for G clockBiju Das2021-12-082-0/+10
| | | | | | | | | | | | | G clock is sourced from PLL3 and PLL6. The output of the mux is connected to divider. This patch adds a mux and divider for getting different rates from this clock sources. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macroBiju Das2021-12-081-2/+2
| | | | | | | | | | Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree mentioned in the hardware manual(Rev.1.00 Sep, 2021). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211203115154.31864-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: cpg-mssr: Add support for R-Car S4-8Yoshihiro Shimoda2021-12-085-0/+196
| | | | | | | | | | Initial CPG support for R-Car S4-8 (r8a779f0). Inspired by patches in the BSP by LUU HOAI. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-10-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
* clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driverYoshihiro Shimoda2021-12-087-341/+437
| | | | | | | | | | | | | According to the official website [1], the R-Car V3U SoC is based on the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPG driver. [1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-9-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-17 09:42:58 +0000