summaryrefslogtreecommitdiffstats
path: root/drivers/clk/socfpga/clk-gate-a10.c
Commit message (Collapse)AuthorAgeFilesLines
* clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handlingMarco Pagani2023-03-211-7/+19
| | | | | | | | | | | | | | | The function of_clk_add_provider() has been deprecated, so use its suggested replacement of_clk_add_hw_provider() instead. Since of_clk_add_hw_provider() can fail, like of_clk_add_provider(), check its return value and do the error handling. The indentation of the init function parameters has been aligned to match open parenthesis as suggested by checkpatch. Signed-off-by: Marco Pagani <marpagan@redhat.com> Link: https://lore.kernel.org/r/20221209152913.1335068-5-marpagan@redhat.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: socfpga: remove the setting of clk-phase for sdmmc_clkDinh Nguyen2022-12-071-68/+0
| | | | | | | | | | Now that the SDMMC driver supports setting the clk-phase, we can remove the need to do it in the clock driver. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20221114230217.202634-5-dinguyen@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* clk: socfpga: arria10: Fix memory leak of socfpga_clk on error returnColin Ian King2021-04-071-0/+1
| | | | | | | | | | | | There is an error return path that is not kfree'ing socfpga_clk leading to a memory leak. Fix this by adding in the missing kfree call. Addresses-Coverity: ("Resource leak") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210406170115.430990-1-colin.king@canonical.com Acked-by: Dinh Nguyen <dinguyen@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* clk: socfpga: arria10: convert to use clk_hwDinh Nguyen2021-03-301-4/+4
| | | | | | | | | | As recommended by Stephen Boyd, convert the Arria10 clock driver to use the clk_hw registration method. Suggested-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20210302214151.1333447-2-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner2019-05-301-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: socfpga: Fix the smplsel on Arria10 and Stratix10Dinh Nguyen2017-06-191-1/+1
| | | | | | | | | | | | The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are offset by 1 additional bit. Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and Stratix10 platforms. Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use") Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: socfpga: allow for multiple parents on Arria10 periph clocksDinh Nguyen2016-02-221-5/+1
| | | | | | | | | | | | There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper function. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: socfpga: switch to GENMASK()Andy Shevchenko2015-07-281-1/+1
| | | | | | | | Convert the code to use GENMASK() helper instead of div_mask() macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: socfpga: Remove clk.h and clkdev.h includesStephen Boyd2015-07-201-0/+1
| | | | | | | | | | Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Remove the include here because this is a provider driver. The clkdev.h include isn't used either, remove it and add in slab.h to make sure things keep compiling. Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: socfpga: remove a stray tabDan Carpenter2015-06-091-1/+1
| | | | | | | | This line was indented too far. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* clk: socfpga: add a clock driver for the Arria 10 platformDinh Nguyen2015-05-211-0/+190
The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5 platform that it should just have it's own driver. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 06:46:04 +0000