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* clk: samsung: clk-exynos-audss: Fix module autoloadJavier Martinez Canillas2016-11-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 34b89b2967f284937be6759936ef3dc4d3aff2d0 upstream. If the driver is built as a module, autoload won't work because the module alias information is not filled. So user-space can't match the registered device with the corresponding module. Export the module alias information using the MODULE_DEVICE_TABLE() macro. Before this patch: $ modinfo drivers/clk/samsung/clk-exynos-audss.ko | grep alias alias: platform:exynos-audss-clk After this patch: $ modinfo drivers/clk/samsung/clk-exynos-audss.ko | grep alias alias: platform:exynos-audss-clk alias: of:N*T*Csamsung,exynos5420-audss-clockC* alias: of:N*T*Csamsung,exynos5420-audss-clock alias: of:N*T*Csamsung,exynos5410-audss-clockC* alias: of:N*T*Csamsung,exynos5410-audss-clock alias: of:N*T*Csamsung,exynos5250-audss-clockC* alias: of:N*T*Csamsung,exynos5250-audss-clock alias: of:N*T*Csamsung,exynos4210-audss-clockC* alias: of:N*T*Csamsung,exynos4210-audss-clock Fixes: 4d252fd5719b ("clk: samsung: Allow modular build of the Audio Subsystem CLKCON driver") Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: qoriq: Don't allow CPU clocks higher than starting valueScott Wood2016-11-181-5/+8
| | | | | | | | | | | | | | | | | | | | | commit 7c1c5413a7bdf1c9adc8d979521f1b8286366aef upstream. The boot-time frequency of a CPU is considered its rated maximum, as we have no other source of such information. However, this was previously only used for chips with 80% restrictions on secondary PLLs. This usually wasn't a problem because most chips/configs boot with a divider of /1, with other dividers being used only for dynamic frequency reduction. However, at least one config (LS1021A at less than 1 GHz) uses a different divider for top speed. This was causing cpufreq to set a frequency beyond the chip's rated speed. This is fixed by applying a 100%-of-initial-speed limit to all CPU PLLs, similar to the existing 80% limit that only applied to some. Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: divider: Fix clk_divider_round_rate() to use clk_readl()Geert Uytterhoeven2016-10-311-1/+1
| | | | | | | | | | | | | | | commit 2cf9a57811bddb6fa6b0f8d7376da164d5534813 upstream. clk-divider uses clk_readl()/clk_writel() everywhere, except in clk_divider_round_rate(), where plain readl() is used. Change this to clk_readl(), as it makes a difference on powerpc. Fixes: e6d5e7d90be92cee ("clk-divider: Fix READ_ONLY when divider > 1") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: core: Force setting the phase delay when no changeJean-Francois Moine2016-10-311-5/+0
| | | | | | | | | | | | | | | | | | | commit 3174b0c9a62bb3738b4a2a506b8a075d4430e353 upstream. This patch reverts commit 023bd7166be0 ("clk: skip unnecessary set_phase if nothing to do"), fixing two problems: * in some SoCs, the hardware phase delay depends on the rate ratio of the clock and its parent. So, changing this ratio may imply to set new hardware values, even if the logical delay is the same. * when the delay was the same as previously, an error was returned. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Fixes: 023bd7166be0 ("clk: skip unnecessary set_phase if nothing to do") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: Return errors from clk providers in __of_clk_get_from_provider()Stephen Boyd2016-10-311-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | commit f155d15b64e36b45ca89e3521fe0c1ccad5e5ff0 upstream. Before commit 0861e5b8cf80 (clk: Add clk_hw OF clk providers, 2016-02-05) __of_clk_get_from_provider() would return an error pointer of the provider's choosing if there was a provider registered and EPROBE_DEFER otherwise. After that commit, it would return EPROBE_DEFER regardless of whether or not the provider returned an error. This is odd and can lead to behavior where clk consumers keep probe deferring when they should be seeing some other error. Let's restore the previous behavior where we only return EPROBE_DEFER when there isn't a provider in our of_clk_providers list. Otherwise, return the error from the last provider we find that matches the node. Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Fixes: 0861e5b8cf80 ("clk: Add clk_hw OF clk providers") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: qoriq: fix a register offset errorTang Yuantian2016-10-311-1/+5
| | | | | | | | | | | | | | | commit 8964193f6bfda5c4cf14eedb7e94892c1f1c34f0 upstream. The offset of Core Cluster clock control/status register on cluster group V3 version is different from others, and should be plus 0x70000. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: Scott Wood <oss@buserror.net> Fixes: 9e19ca2f627e ("clk: qoriq: Add ls2080a support.") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: qcom: select GDSC for msm8996 gcc and mmccSrinivas Kandagatla2016-10-311-0/+2
| | | | | | | | | | | | | | | | | commit 6d91f2c0141330b919ae4d13395f38c341469564 upstream. This patch selects QCOM_GDSC Kconfig for msm8996 GCC and MMCC clock controllers, as these provide some of the gdscs on the SOC. Also selecting this config will make it align with other drivers which do the same. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 52111672f791 ("clk: qcom: gdsc: Add GDSCs in msm8996 GCC") Fixes: 7e824d507909 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: gcc-msm8996: Fix pcie 2 pipe register offsetSrinivas Kandagatla2016-10-311-2/+2
| | | | | | | | | | | | | commit ce61966c05f276294b6be04d1765ad0d827ddefd upstream. This patch corrects the register offset for pcie2 pipe clock. Offset according to datasheet is 0x6e018 instead of 0x6e108. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: bcm2835: Skip PLLC clocks when deciding on a new clock parentEric Anholt2016-10-311-0/+23
| | | | | | | | | | | | | | | | | | | | | commit 67615c588a059b731df9d019edc3c561d8006ec9 upstream. If the firmware had set up a clock to source from PLLC, go along with it. But if we're looking for a new parent, we don't want to switch it to PLLC because the firmware will force PLLC (and thus the AXI bus clock) to different frequencies during over-temp/under-voltage, without notification to Linux. On my system, this moves the Linux-enabled HDMI state machine and DSI1 escape clock over to plld_per from pllc_per. EMMC still ends up on pllc_per, because the firmware had set it up to use that. Signed-off-by: Eric Anholt <eric@anholt.net> Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Acked-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: clk-imx35: fix name for ckil clkUwe Kleine-König2016-10-311-1/+1
| | | | | | | | | | | | | | | commit fcff03813a7c612873303037cef5ba0329850c35 upstream. This fixes [ 0.000000] i.MX clk 82: register failed with -17 because the name is duplicated. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Fixes: 3713e3f5e927 ("clk: imx35: define two clocks for rtc") Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: imx6: fix i.MX6DL clock tree to reflect realityLucas Stach2016-10-281-12/+16
| | | | | | | | | | | | | | | | | | | | commit b1d51b448e4e6a392283b3eab06a7c5ec6d8a4e2 upstream. The current clock tree only implements the minimal set of differences between the i.MX6Q and the i.MX6DL, but that doesn't really reflect reality. Apply the following fixes to match the RM: - DL has no GPU3D_SHADER_SEL/PODF, the shader domain is clocked by GPU3D_CORE - GPU3D_SHADER_SEL/PODF has been repurposed as GPU2D_CORE_SEL/PODF - GPU2D_CORE_SEL/PODF has been repurposed as MLB_SEL/PODF Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: imx6: initialize GPU clocksLucas Stach2016-10-281-0/+18
| | | | | | | | | | | | | | | | | | commit d8846023aed1293e54d33499558fc2aa2b2f393f upstream. Initialize the GPU clock muxes to sane inputs. Until now they have not been changed from their default values, which means that both GPU3D shader and GPU2D core were fed by clock inputs whose rates exceed the maximium allowed frequency of the cores by as much as 200MHz. This fixes a severe GPU stability issue on i.MX6DL. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: mvebu: dynamically allocate resources in Armada CP110 system controllerMarcin Wojtas2016-10-221-9/+20
| | | | | | | | | | | | | | | | | | | commit a0245eb76ad0f652f1eb14f48ca2d3c4391aef66 upstream. Original commit, which added support for Armada CP110 system controller used global variables for storing all clock information. It worked fine for Armada 7k SoC, with single CP110 block. After dual-CP110 Armada 8k was introduced, the data got overwritten and corrupted. This patch fixes the issue by allocating resources dynamically in the driver probe and storing it as platform drvdata. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* clk: mvebu: fix setting unwanted flags in CP110 gate clockMarcin Wojtas2016-10-221-0/+2
| | | | | | | | | | | | | | | | | | commit ad715b268a501533ecb2e891a624841d1bb5137c upstream. Armada CP110 system controller comprises its own routine responsble for registering gate clocks. Among others 'flags' field in struct clk_init_data was not set, using a random values, which may cause an unpredicted behavior. This patch fixes the problem by resetting all fields of clk_init_data before assigning values for all gated clocks of Armada 7k/8k SoCs family. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'sunxi-clk-fixes-for-4.8' of ↵Stephen Boyd2016-09-084-14/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes Clock Fixes for the Allwinner SoCs, 4.8 Edition The usual bunch of fixes to the our clock drivers, mostly targetted to the brand new sunxi-ng drivers. * tag 'sunxi-clk-fixes-for-4.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi-ng: Fix wrong reset register offsets clk: sunxi-ng: nk: Make ccu_nk_find_best static clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock clk: sunxi: Fix return value check in sun8i_a23_mbus_setup() clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
| * clk: sunxi-ng: Fix wrong reset register offsetsJorik Jonker2016-08-291-8/+8
| | | | | | | | | | | | | | The reset register offsets for UART*, I2C* and SCR were off by a few bytes. Signed-off-by: Jorik Jonker <jorik@kippendief.biz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: nk: Make ccu_nk_find_best staticChen-Yu Tsai2016-08-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | make C=2 reports: CHECK drivers/clk/sunxi-ng/ccu_nk.c drivers/clk/sunxi-ng/ccu_nk.c:17:6: warning: symbol 'ccu_nk_find_best' was not declared. Should it be static? ccu_nk_find_best is only used within ccu_nk.c. So make it static to get rid of this warning. Fixes: adbfb0056e03 ("clk: sunxi-ng: Add N-K-factor clock support") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lockChen-Yu Tsai2016-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The condition passed to read*_poll_timeout() is the break condition, i.e. wait for this condition to happen and return success. The original code assumed the opposite, resulting in a warning when the PLL clock rate was changed but never lost it's lock as far as the readout indicated. This was verified by checking the read out register value. Fixes: 1d80c14248d6 ("clk: sunxi-ng: Add common infrastructure") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: Fix return value check in sun8i_a23_mbus_setup()Wei Yongjun2016-08-081-1/+1
| | | | | | | | | | | | | | | | | | In case of error, the function of_io_request_and_map() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()Wei Yongjun2016-08-081-2/+2
| | | | | | | | | | | | | | | | | | | | In case of error, the functions clk_register_composite() and clk_register_divider() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | Merge tag 'v4.8-rockchip-clk-fixes1' of ↵Stephen Boyd2016-08-291-5/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Some fixes for rk3399 register errors that revealed themself during actual use. * tag 'v4.8-rockchip-clk-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399 clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399 clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399 clk: rockchip: fix rk3399 aclk_vio gate bit
| * | clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399Xing Zheng2016-08-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't have code to handle any of the noc clocks in rk3399 and they're all just listed as critical clocks. Let's do the same for aclk_emmc_noc. Without this clock being marked as critical we have problems around suspend/resume after commit 20c389e656a8 ("clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399"). Before that change we were presumably not actually gating any of these clocks because we were setting the wrong gate. Fixes: 20c389e656a8 ("clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399") Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src on rk3399Xing Zheng2016-08-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sorry to refer incorrect clock diagram, we double check it that the bits configuration of the Xpll_aclk_perihp_src need to be fixed: bit 1 - shows aclk_perihp_cpll_src_en bit 0 - shows aclk_perihp_gpll_src_en Through the testing that plug/unplug the USB ethernet cable on the RK3399 kevin board. 1. the hclk_host0 and hclk_host1 are endpoint clocks: cpll --> G5[1] --> aclk_perihp_cpll_src --\ |--> hclk_host0 | --> ... ---> | gpll --> G5[0] --> aclk_perihp_gpll_src --/ |--> hclk_host1 2. there is no clock below the cpll_aclk_perihp_src, and the hclk_hostX are below the gpll_aclk_perihp_src: pll_cpll 1 1 800000000 0 0 cpll 7 19 800000000 0 0 cpll_aclk_perihp_src 0 0 800000000 0 0 ... pll_gpll 1 1 594000000 0 0 gpll 10 10 594000000 0 0 gpll_aclk_perihp_src 2 2 594000000 0 0 hclk_perihp 5 5 74250000 0 0 hclk_host1_arb 2 2 74250000 0 0 hclk_host1 2 2 74250000 0 0 hclk_host0_arb 2 2 74250000 0 0 hclk_host0 2 2 74250000 0 0 3. by default, G5[0] and G5[1] are enabled: localhost ~ # mem r 0xff760314 0x000003e0 4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet cable, the DUT still works well: localhost ~ # mem w 0xff760314 0xffff03e2 localhost ~ # mem r 0xff760314 0x000003e2 plug/unplug, the work statue is ok 5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet cable, the DUT will be crashed: localhost ~ # mem w 0xff760314 0xffff03e1 localhost ~ # mem r 0xff760314 0x000003e1 plug/unplug, the DUT is crashed Summary: bit 1 - shows aclk_perihp_cpll_src_en bit 0 - shows aclk_perihp_gpll_src_en Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src") Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> [here the clock-documentation in the manual was actually stating the wrong bits and thus only Xing's testing above revealed the issue] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399Xing Zheng2016-08-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dues to incorrect diagram, we need to fix incorrect bits for (c/g)pll_aclk_emmc_src: cpll_aclk_emmc_src --> G6[13] gpll_aclk_emmc_src --> G6[12] Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399") Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: fix rk3399 aclk_vio gate bitChris Zhong2016-08-111-1/+1
| |/ | | | | | | | | | | | | | | | | | | Fix incorrect rk3399 aclk_vio gating bit, it should be 0, not 10. Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399") Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2Vince Hsu2016-08-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when the DIS power domain is during up-powergating process but the clamp to this domain is not removed yet. That causes a timeout and aborts the power sequence, although the PLLD/PLLD2 has already locked. To remove the false alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the clocks as locked. Signed-off-by: Vince Hsu <vinceh@nvidia.com> Tested-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: renesas: r8a7795: Fix SD clocksYoshihiro Shimoda2016-08-111-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet, SDn clocks are from the SDSRC clock. And the SDSRC has a 1/2 divider. So, we should have ".sdsrc" as an internal core clock. Otherwise, since the sdhi driver will calculate clock for a sd card using the wrong parent clock rate, and then performance will be not good. Fixes: 90c073e53909da85 ("clk: shmobile: r8a7795: Add SD divider support") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: stable@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lockChen-Yu Tsai2016-08-101-1/+1
|/ | | | | | | | | | | | | | | The condition passed to read*_poll_timeout() is the break condition, i.e. wait for this condition to happen and return success. The original code assumed the opposite, resulting in a warning when the PLL clock rate was changed but never lost it's lock as far as the readout indicated. This was verified by checking the read out register value. Fixes: 1d80c14248d6 ("clk: sunxi-ng: Add common infrastructure") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* treewide: replace obsolete _refok by __refFabian Frederick2016-08-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There was only one use of __initdata_refok and __exit_refok __init_refok was used 46 times against 82 for __ref. Those definitions are obsolete since commit 312b1485fb50 ("Introduce new section reference annotations tags: __ref, __refdata, __refconst") This patch removes the following compatibility definitions and replaces them treewide. /* compatibility defines */ #define __init_refok __ref #define __initdata_refok __refdata #define __exit_refok __ref I can also provide separate patches if necessary. (One patch per tree and check in 1 month or 2 to remove old definitions) [akpm@linux-foundation.org: coding-style fixes] Link: http://lkml.kernel.org/r/1466796271-3043-1-git-send-email-fabf@skynet.be Signed-off-by: Fabian Frederick <fabf@skynet.be> Cc: Ingo Molnar <mingo@redhat.com> Cc: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2016-08-011-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Device tree contents continue to be the largest branches we submit. This time around, some of the contents worth pointing out is: New SoC platforms: - Freescale i.MX 7Solo - Broadcom BCM23550 - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_ - Hisilicon HI3519 - Renesas R8A7792 Some of the other delta that is sticking out, line-count wise: - Exynos moves of IP blocks under an SoC bus, which causes a large delta due to indentation changes - a new Tegra K1 board: Apalis - a bunch of small updates to many Allwinner platforms; new hardware support, some cleanup, etc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits) ARM: dts: sun8i: Add dts file for inet86dz board ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04 ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts ARM: dts: sun5i: reference-design-tablet: Remove mention of q8 ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi ARM: dts: at91: Don't build unnecessary dtbs ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions ARM: dts: at91: at91sam9g25ek: fix isi endpoint node ARM: dts: at91: move isi definition to at91sam9g25ek ARM: dts: at91: fix i2c-gpio node name ARM: dts: at91: vinco: fix regulator name ARM: dts: at91: ariag25 : fix onewire node ...
| * Merge tag 'sti-late-v4.8' of ↵Arnd Bergmann2016-07-143-14/+27
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/late Merge "STi late updates for v4.8" from Patrice Chotard: - Add STi DT critical clocks declaration - Remove SPI hack wich has dependecy with critical clocks These 2 STi DT patches and SPI hack MUST be applied after patches contained into Stephen Boyd's branch clk-next/clk-st-critical. This to ensure not to break SPI. * tag 'sti-late-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti: spi: st-ssc4: Remove 'no clocking' hack ARM: sti: stih410-clocks: Identify critical clocks ARM: sti: stih407-family: Supply defines for CLOCKGEN A0 clk: st: clkgen-pll: Detect critical clocks clk: st: clkgen-fsyn: Detect critical clocks clk: st: clk-flexgen: Detect critical clocks
| * \ Merge tag 'omap-for-v4.8/dt-part1-signed-v2' of ↵Olof Johansson2016-07-041-0/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Device tree changes for omaps for v4.8 merge window: - PWM binding updates and related dts changes - OCM RAM updates for dra7 - Enable n900 lirc-rx51 driver - omap3-gta04 updates for backlight, bma180, itg3200, hmc5843 and wifi - am335x, am437x and am57xx operating point updates and additions - am335x-icev2 pca9536 node - dra72-evm regulator updates - edma spelling fixes - am335x and am437x ethernet phy update - a series of mcbsp updates - omap3-gta04 eeprom - dra7 PCIe unit address fix - stdout-path for beaglebone variants - crypto accelerator nodes for am335x, am437x and dra7 * tag 'omap-for-v4.8/dt-part1-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (42 commits) ARM: dts: AM43xx: Add node for RNG ARM: dts: AM43xx: clk: Add RNG clk node ARM: dts: DRA7: Add DT node for RNG IP ARM: dts: DRA7: Add support for SHA IP ARM: dts: DRA7: Add DT nodes for AES IP ARM: dts: DRA7: Add DT node for DES IP ARM: dts: am335x-bone-common: use stdout-path in Beaglebone boards. ARM: dts: DRA7: fix unit address of second PCIe instance ARM: dts: omap3-gta04: Add RFID eeprom node ARM: dts: omap4-duovero: Add pdmclk binding for audio ARM: dts: omap4-var-som-om44: Add pdmclk binding for audio ARM: dts: omap4-sdp: Add pdmclk binding for audio ARM: dts: omap4-panda-common: Add pdmclk binding for audio ARM: dts: omap5-board-common: Add pdmclk binding for audio ARM: dts: omap3: Add clocks to McBSP nodes ARM: dts: am335x-bone-common: Mark MAC as having only one PHY ARM: dts: am437x-idk-evm: Mark MAC as having only one PHY ARM: dts: Correct misspelling, "emda3" -> "edma3" ARM: dts: dra72-evm: Rename 3.3V regulator tag ARM: dts: am335x-icev2: Add DT node for TI PCA9536 ... Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | ARM: dts: AM43xx: clk: Add RNG clk nodeLokesh Vutla2016-06-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clk node for RNG module. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | | Merge tag 'armsoc-drivers' of ↵Linus Torvalds2016-08-014-31/+7
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs. A slew of changes this release cycle. The reset driver tree, that we merge through arm-soc for historical reasons, is also sizable this time around. Among the changes: - clps711x: Treewide changes to compatible strings, merged here for simplicity. - Qualcomm: SCM firmware driver cleanups, move to platform driver - ux500: Major cleanups, removal of old mach-specific infrastructure. - Atmel external bus memory driver - Move of brcmstb platform to the rest of bcm - PMC driver updates for tegra, various fixes and improvements - Samsung platform driver updates to support 64-bit Exynos platforms - Reset controller cleanups moving to devm_reset_controller_register() APIs - Reset controller driver for Amlogic Meson - Reset controller driver for Hisilicon hi6220 - ARM SCPI power domain support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (100 commits) ARM: ux500: consolidate base platform files ARM: ux500: move soc_id driver to drivers/soc ARM: ux500: call ux500_setup_id later ARM: ux500: consolidate soc_device code in id.c ARM: ux500: remove cpu_is_u* helpers ARM: ux500: use CLK_OF_DECLARE() ARM: ux500: move l2x0 init to .init_irq mfd: db8500 stop passing around platform data ASoC: ab8500-codec: remove platform data based probe ARM: ux500: move ab8500_regulator_plat_data into driver ARM: ux500: remove unused regulator data soc: raspberrypi-power: add CONFIG_OF dependency firmware: scpi: add CONFIG_OF dependency video: clps711x-fb: Changing the compatibility string to match with the smallest supported chip input: clps711x-keypad: Changing the compatibility string to match with the smallest supported chip pwm: clps711x: Changing the compatibility string to match with the smallest supported chip serial: clps711x: Changing the compatibility string to match with the smallest supported chip irqchip: clps711x: Changing the compatibility string to match with the smallest supported chip clocksource: clps711x: Changing the compatibility string to match with the smallest supported chip clk: clps711x: Changing the compatibility string to match with the smallest supported chip ...
| * \ \ \ Merge tag 'ux500-cleanup-bundle' of ↵Arnd Bergmann2016-07-143-30/+6
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/drivers Merge "Ux500 cleanups from Arnd" from Linus Walleij: This is a set of cleanups for the Ux500 that reduce the number of machine-local files and boardfile-type data for regulators and ASoC. * tag 'ux500-cleanup-bundle' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: consolidate base platform files ARM: ux500: move soc_id driver to drivers/soc ARM: ux500: call ux500_setup_id later ARM: ux500: consolidate soc_device code in id.c ARM: ux500: remove cpu_is_u* helpers ARM: ux500: use CLK_OF_DECLARE() ARM: ux500: move l2x0 init to .init_irq mfd: db8500 stop passing around platform data ASoC: ab8500-codec: remove platform data based probe ARM: ux500: move ab8500_regulator_plat_data into driver ARM: ux500: remove unused regulator data
| | * | | | ARM: ux500: use CLK_OF_DECLARE()Arnd Bergmann2016-07-123-30/+6
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ux500 DT support predates the CLK_OF_DECLARE macro and calls directly into the clk driver from platform code. Converting this to CLK_OF_DECLARE makes the code much nicer and similar to how modern platforms do it today. It also removes the last user of cpu_is_u8500_family() etc. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * / | | clk: clps711x: Changing the compatibility string to match with the smallest ↵Alexander Shiyan2016-07-061-1/+1
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | supported chip This patch changes the compatibility string to match with the smallest supported chip (EP7209). Since the DT-support for this CPU is not yet announced, this change is safe. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | | Merge tag 'armsoc-soc' of ↵Linus Torvalds2016-08-012-0/+9
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "Improved and new platform support for various SoCs: New SoC support: - Broadcom BCM23550 - Freescale i.MX7Solo - Qualcomm MDM9615 - Renesas r8a7792 Improvements: - convert clps711x to multiplatform - debug uart improvements for Atmel platforms - Tango platform improvements: HOTPLUG_CPU, Suspend-to-ram - OMAP tweaks and improvements to hwmod - OMAP support for kexec on SMP" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (109 commits) ARM: davinci: fix build break because of undeclared dm365_evm_snd_data ARM: s3c64xx: smartq: Avoid sparse warnings ARM: sti: Implement dummy L2 cache's write_sec ARM: STi: Update machine _namestr to be more generic. arm: meson: explicitly select clk drivers ARM: tango: add Suspend-to-RAM support ARM: hisi: consolidate the hisilicon machine entries ARM: tango: fix CONFIG_HOTPLUG_CPU=n build MAINTAINERS: Update BCM281XX/BCM11XXX/BCM216XX entry MAINTAINERS: Update BCM63XX entry MAINTAINERS: Add NS2 entry MAINTAINERS: Fix nsp false-positives MAINTAINERS: Change L to M for Broadcom ARM/ARM64 SoC entries ARM: debug: Enable DEBUG_BCM_5301X for Northstar Plus SoCs ARM: clps711x: Switch to MULTIPLATFORM ARM: clps711x: Remove boards support ARM: clps711x: Add basic DT support ARM: clps711x: Reduce static map size ARM: SAMSUNG: Constify iomem address passed to s5p_init_cpu ARM: oxnas: Change OX810SE default driver config ...
| * \ \ \ Merge tag 'omap-for-v4.8/soc-signed' of ↵Olof Johansson2016-07-052-0/+9
| |\ \ \ \ | | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc SoC related changes for omaps for v4.8 merge window: - A series of DSS platform_data fixes to prepare for DSS driver changes - Add tblck clck aliases for PWM - A series of trivial spelling corrections - Remove bogus eQEP, ePWM and eCAP hwmod entries - A series of McBSP sidetone fixes - Remove QSPI and DSS addresses from hwmod, these come from dts - Fix RSTST register offset for pruss - Make ti81xx_rtc_hwmod static - Remove wrongly defined RSTST offset for PER Domain, note that the subject for this one wrongly has "dts" in the subject - Add support for omap5 and dra7 workaround for 801819 - A series of patches to make kexec work for SMP omaps * tag 'omap-for-v4.8/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (30 commits) ARM: OMAP2+: Fix build if CONFIG_SMP is not set ARM: OMAP4+: Allow kexec on SMP variants ARM: OMAP4+: Reset CPU1 properly for kexec ARM: OMAP4+: Prevent CPU1 related hang with kexec ARM: OMAP4+: Initialize SAR RAM base early for proper CPU1 reset for kexec ARM: dts: am43xx: Remove wrongly defined RSTST offset for PER Domain ARM: OMAP: make ti81xx_rtc_hwmod static ARM: AM43XX: hwmod: Fix RSTST register offset for pruss ARM: DRA7: hwmod: remove DSS addresses from hwmod ARM: DRA7: hwmod: Remove QSPI address space entry from hwmod ARM: OMAP2+: McBSP: Remove the old iclk allow/deny idle code ASoC: omap-mcbsp: sidetone: Use the new callback for iclk handling ASoC: omap-mcbsp: Rename omap_mcbsp_sysfs_remove() to omap_mcbsp_cleanup() ARM: OMAP3: pdata-quirks: Add support for McBSP2/3 sidetone handling ARM: OMAP3: McBSP: New callback for McBSP2/3 ICLK idle configuration ARM: OMAP3: hwmod data: Fix McBSP2/3 sidetone data ARM: AM335x/AM437x: hwmod: Remove eQEP, ePWM and eCAP hwmod entries ARM: OMAP2+: Fix typo in sdrc.h ARM: OMAP2+: Fix typo in omap_device.c ARM: OMAP2+: Fix typo in omap4-common.c ... Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | clk: ti: am335x/am4372: Add tbclk to pwm nodeFranklin S Cooper Jr2016-06-102-0/+9
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add tblck to the pwm nodes. This insures that the ehrpwm driver has access to the time-based clk. Do not remove similar entries for ehrpwm node. Later patches will switch from using ehrpwm node name to pwm. But to maintain ABI compatibility we shouldn't remove the old entries. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | | | Merge branch 'clk-fixes' into clk-nextMichael Turquette2016-07-213-6/+5
|\ \ \ \
| * | | | clk: at91: fix clk_programmable_set_parent()Boris Brezillon2016-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 1bdf02326b71e ("clk: at91: make use of syscon/regmap internally"), clk_programmable_set_parent() is always selecting the first parent (AKA slow_clk), no matter what's passed in the 'index' parameter. Fix that by initializing the pckr variable to the index value. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reported-by: Hans Verkuil <hans.verkuil@cisco.com> Fixes: 1bdf02326b71e ("clk: at91: make use of syscon/regmap internally") Cc: <stable@vger.kernel.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1468828152-18389-1-git-send-email-boris.brezillon@free-electrons.com
| * | | | Merge tag 'sunxi-clk-fixes-for-4.7' of ↵Michael Turquette2016-07-062-5/+4
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes Allwinner clock fixes for 4.7 A bunch of changes for the display clocks merged in 4.7
| | * | | | clk: sunxi: remove unused variableArnd Bergmann2016-06-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only use of the local num_parents variable was remove, so we now get a warning: drivers/clk/sunxi/clk-sun4i-tcon-ch1.c: In function 'tcon_ch1_get_parent': drivers/clk/sunxi/clk-sun4i-tcon-ch1.c:82:6: error: unused variable 'num_parents' [-Werror=unused-variable] This removes the variable. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 4de2d58bc973 ("clk: sunxi: tcon-ch1: Do not return a negative error in get_parent") Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | clk: sunxi: display: Add per-clock flagsMaxime Ripard2016-06-101-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TCON channel 0 clock that is the parent clock of our pixel clock is expected to change its rate depending on the resolution we want to output in our display engine. However, since it's only a mux, the only way it can do that is by changing its parents rate. Allow to give flags in our display clocks description, and add the CLK_SET_RATE_PARENT flag for the TCON channel 0 flag. Fixes: a3b4956ee6d9 ("clk: sunxi: display: Add per-clock flags") Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| | * | | | clk: sunxi: tcon-ch1: Do not return a negative error in get_parentMaxime Ripard2016-06-101-3/+0
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_parent is supposed to return an unsigned 8 bit integer, so returning -EINVAL is a bad idea. Remove it. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | | | clk: Makefile: re-sort and clean upMichael Turquette2016-07-191-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sorting is hard. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | | | Merge branch 'clk-s905' into clk-nextMichael Turquette2016-07-151-1/+1
|\ \ \ \ \
| * | | | | Revert "clk: gxbb: expose CLKID_MMC_PCLK"Michael Turquette2016-07-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e16fb2e6355c1c1b41623af9e01ada196e2af098. Updated documentation from the chip vendor reveals that this clock is not required for correct operation of the MMC controller. As such, do not expose it to DT. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | | | | | clk: samsung: Allow modular build of the Audio Subsystem CLKCON driverSylwester Nawrocki2016-07-133-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Any clock dependencies can be properly handled with deferred probing so we can remove core_initcall and switch to a proper loadable platform driver module. This change has been tested on Exynos4412 Odroid U3 based board. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1467987300-31450-1-git-send-email-s.nawrocki@samsung.com
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-17 15:54:28 +0000