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* Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-07-0453-871/+7363
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull more clk updates from Stephen Boyd: "Another set of clk driver updates and fixes for the merge window. The driver updates needed more time to bake in linux-next. Updates: - Support for more clk controllers in Qualcomm SoCs such as SM8350, SM8450, SDX75, SC8280XP, and IPQ9574 - Runtime PM enablement of some more Qualcomm clk controllers - Various fixes to Qualcomm clk driver data to use correct clk_ops and to check halt bits properly - AT91 updates to modernize with clk_parent_data structures Fixes: - Remove 'syscon' from dt binding fix for ti,j721e-system-controller - Fix determine rate in the Tegra driver that got wrecked by the refactorting of muxes this merge window" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (69 commits) clk: tegra: Avoid calling an uninitialized function dt-bindings: mfd: ti,j721e-system-controller: Remove syscon from example clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id clk: at91: sama7g5: switch to parent_hw and parent_data clk: at91: sckc: switch to parent_data/parent_hw clk: at91: clk-sam9x60-pll: add support for parent_hw clk: at91: clk-utmi: add support for parent_hw clk: at91: clk-system: add support for parent_hw clk: at91: clk-programmable: add support for parent_hw clk: at91: clk-peripheral: add support for parent_hw clk: at91: clk-master: add support for parent_hw clk: at91: clk-generated: add support for parent_hw clk: at91: clk-main: add support for parent_data/parent_hw clk: qcom: gcc-sc8280xp: Add runtime PM clk: qcom: gpucc-sc8280xp: Add runtime PM clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags clk: qcom: gpucc-sm6375: Enable runtime pm dt-bindings: clock: sm6375-gpucc: Add VDD_GX clk: qcom: gcc-sm6115: Add missing PLL config properties clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) ...
| * clk: tegra: Avoid calling an uninitialized functionThierry Reding2023-07-041-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 493ffb046cf5 ("clk: tegra: super: Switch to determine_rate") replaced clk_super_round_rate() by clk_super_determine_rate(), but didn't update one callsite that was explicitly calling the old tegra_clk_super_ops.round_rate() function, which was now NULL. This resulted in a crash on Tegra30 systems during early boot. Switch this callsite over to the clk_super_determine_rate() equivalent to avoid the crash. Fixes: 493ffb046cf5 ("clk: tegra: super: Switch to determine_rate") Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230630130748.840729-1-thierry.reding@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| *-. Merge branches 'clk-qcom' and 'clk-microchip' into clk-nextStephen Boyd2023-06-2652-868/+7351
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-qcom: (63 commits) clk: qcom: gcc-sc8280xp: Add runtime PM clk: qcom: gpucc-sc8280xp: Add runtime PM clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags clk: qcom: gpucc-sm6375: Enable runtime pm dt-bindings: clock: sm6375-gpucc: Add VDD_GX clk: qcom: gcc-sm6115: Add missing PLL config properties clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi) clk: qcom: gcc-ipq6018: remove duplicate initializers clk: qcom: gcc-ipq9574: Enable crypto clocks dt-bindings: clock: Add crypto clock and reset definitions clk: qcom: Add lpass audio clock controller driver for SC8280XP clk: qcom: Add lpass clock controller driver for SC8280XP dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP dt-bindings: clock: Add LPASSCC and reset controller for SC8280XP dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226 clk: qcom: gpucc-sm8550: Add support for graphics clock controller clk: qcom: Add support for SM8450 GPUCC clk: qcom: gcc-sm8450: Enable hw_clk_ctrl clk: qcom: rcg2: Make hw_clk_ctrl toggleable dt-bindings: clock: qcom: Add SM8550 graphics clock controller ... * clk-microchip: clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id clk: at91: sama7g5: switch to parent_hw and parent_data clk: at91: sckc: switch to parent_data/parent_hw clk: at91: clk-sam9x60-pll: add support for parent_hw clk: at91: clk-utmi: add support for parent_hw clk: at91: clk-system: add support for parent_hw clk: at91: clk-programmable: add support for parent_hw clk: at91: clk-peripheral: add support for parent_hw clk: at91: clk-master: add support for parent_hw clk: at91: clk-generated: add support for parent_hw clk: at91: clk-main: add support for parent_data/parent_hw
| | | * clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_idClaudiu Beznea2023-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s/ep_chg_chg_id/ep_chg_id in documentation of master clock structure. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-12-claudiu.beznea@microchip.com
| | | * clk: at91: sama7g5: switch to parent_hw and parent_dataClaudiu Beznea2023-06-211-342/+454
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch SAMA7G5 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. Extra time saved on registration is ~250us when running at 800MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-11-claudiu.beznea@microchip.com
| | | * clk: at91: sckc: switch to parent_data/parent_hwClaudiu Beznea2023-06-211-27/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch slow clock drivers to use parent_data and parent_hw. With this parent-child relation is described with pointers rather than strings. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-10-claudiu.beznea@microchip.com
| | | * clk: at91: clk-sam9x60-pll: add support for parent_hwClaudiu Beznea2023-06-214-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for parent_hw in SAM9X60 PLL clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-sam9x60-pll were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-9-claudiu.beznea@microchip.com
| | | * clk: at91: clk-utmi: add support for parent_hwClaudiu Beznea2023-06-2110-17/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for parent_hw in utmi clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-utmi were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-8-claudiu.beznea@microchip.com
| | | * clk: at91: clk-system: add support for parent_hwClaudiu Beznea2023-06-2114-19/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for parent_hw in system clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-system were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-7-claudiu.beznea@microchip.com
| | | * clk: at91: clk-programmable: add support for parent_hwClaudiu Beznea2023-06-2114-17/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for parent_hw in programmable clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-programmable were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-6-claudiu.beznea@microchip.com
| | | * clk: at91: clk-peripheral: add support for parent_hwClaudiu Beznea2023-06-2114-23/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for parent_hw in peripheral clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-peripheral were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-5-claudiu.beznea@microchip.com
| | | * clk: at91: clk-master: add support for parent_hwClaudiu Beznea2023-06-2114-35/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for parent_hw in master clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-master were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-4-claudiu.beznea@microchip.com
| | | * clk: at91: clk-generated: add support for parent_hwClaudiu Beznea2023-06-216-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for parent_hw in generic clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-generated were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-3-claudiu.beznea@microchip.com
| | | * clk: at91: clk-main: add support for parent_data/parent_hwClaudiu Beznea2023-06-2114-37/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for parent_data and parent_hw in main oscillator clock drivers. With this parent-child relations are described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-main were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-2-claudiu.beznea@microchip.com
| | * | clk: qcom: gcc-sc8280xp: Add runtime PMKonrad Dybcio2023-06-201-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GCC block on SC8280XP is powered by the CX rail. We need to ensure that it's enabled to prevent unwanted power collapse. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230619-topic-sc8280xp-clk-rpm-v1-2-1e5e1064cdb2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | * | clk: qcom: gpucc-sc8280xp: Add runtime PMKonrad Dybcio2023-06-201-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPU_CC block on SC8280XP is powered by the GFX rail. We need to ensure that it's enabled to prevent unwanted power collapse. Enable runtime PM to keep the power flowing only when necessary. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230619-topic-sc8280xp-clk-rpm-v1-1-1e5e1064cdb2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | * | clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flagsDmitry Baryshkov2023-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using PWRSTS_RET on msm8974's MDSS_GDSC causes display to stop working. The gdsc doesn't fully come out of retention mode. Change it's pwrsts flags to PWRSTS_OFF_ON. Fixes: d399723950c4 ("clk: qcom: gdsc: Fix the handling of PWRSTS_RET support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rajendra Nayak <quic_rjendra@quicinc.com> Tested-by: Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20230507175335.2321503-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| | * | clk: qcom: gpucc-sm6375: Enable runtime pmKonrad Dybcio2023-06-131-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPUCC block on SM6375 is powered by VDD_CX and VDD_GX. If the latter rail is not online, GX_GDSC will never turn on. Enable runtime pm so that we can reference VDD_GX from the dt to ensure that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230529-topic-sm6375gpuccpd-v1-2-8d57c41a6066@linaro.org
| | * | clk: qcom: gcc-sm6115: Add missing PLL config propertiesKonrad Dybcio2023-06-131-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the driver was ported upstream, PLL ctl register values were omitted. Add them to ensure the PLLs are fully configured like we expect them to. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Iskren Chernev <me@iskren.info> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230601-topic-alpha_ctl-v1-2-b6a932dfcf68@linaro.org
| | * | clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)Konrad Dybcio2023-06-132-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "vanilla" Alpha PLL configs are sometimes provided with an intention to only update certain bits of th register. Do so if a mask is found. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Iskren Chernev <me@iskren.info> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230601-topic-alpha_ctl-v1-1-b6a932dfcf68@linaro.org
| | * | clk: qcom: gcc-ipq6018: remove duplicate initializersArnd Bergmann2023-06-131-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent change added new initializers for .config_ctl_val and .config_ctl_hi_val but left the old values in place: drivers/clk/qcom/gcc-ipq6018.c:4155:27: error: initialized field overwritten [-Werror=override-init] 4155 | .config_ctl_val = 0x240d4828, | ^~~~~~~~~~ drivers/clk/qcom/gcc-ipq6018.c:4156:30: error: initialized field overwritten [-Werror=override-init] 4156 | .config_ctl_hi_val = 0x6, | ^~~ Remove the unused ones now to avoid confusion. Fixes: f4f0c8acee0e4 ("clk: qcom: gcc-ipq6018: update UBI32 PLL") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230601213416.3373599-1-arnd@kernel.org
| | * | clk: qcom: gcc-ipq9574: Enable crypto clocksAnusha Rao2023-06-131-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the clocks required for crypto operation. Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526161129.1454-3-quic_anusha@quicinc.com
| | * | clk: qcom: Add lpass audio clock controller driver for SC8280XPSrinivas Kandagatla2023-06-131-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the lpass audio clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230608125315.11454-5-srinivas.kandagatla@linaro.org
| | * | clk: qcom: Add lpass clock controller driver for SC8280XPSrinivas Kandagatla2023-06-133-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the lpass clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230608125315.11454-4-srinivas.kandagatla@linaro.org
| | * | clk: qcom: gpucc-sm8550: Add support for graphics clock controllerJagadeesh Kona2023-05-263-0/+620
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for gpucc driver on SM8550, which provides clocks for the graphics subsystem. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524181800.28717-3-quic_jkona@quicinc.com
| | * | clk: qcom: Add support for SM8450 GPUCCKonrad Dybcio2023-05-263-0/+775
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPUCC manages the clocks for the Adreno GPU found on the sm8450 SoCs. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-4-4f40e282af1d@linaro.org
| | * | clk: qcom: gcc-sm8450: Enable hw_clk_ctrlKonrad Dybcio2023-05-261-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hardware clock control on all RCGs. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-3-4f40e282af1d@linaro.org
| | * | clk: qcom: rcg2: Make hw_clk_ctrl toggleableKonrad Dybcio2023-05-262-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain SoCs use the HW_CLK_CTRL feature on some of the clocks they host. This allows the clocks to be turned on automatically when a downstream branch tries to change rate or config. Make it togglable so that we can utilize this. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-2-4f40e282af1d@linaro.org
| | * | clk: qcom: mmcc-msm8974: use clk_rcg2_shared_ops for mdp_clk_src clockDmitry Baryshkov2023-05-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mdp_clk_src clock should not be turned off. Instead it should be 'parked' to the XO, as most of other mdp_clk_src clocks. Fix that by using the clk_rcg2_shared_ops. Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230507175335.2321503-1-dmitry.baryshkov@linaro.org
| | * | clk: qcom: ipq5332: fix the order of SLEEP_CLK and XO clockKathiravan T2023-05-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The order of DT_SLEEP_CLK and DT_XO are swapped and it is incorrect. Due to which the clocks for which the parent should be XO is having parent as SLEEP_CLK and vice versa. So fix the same by re-ordering the entries. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Reported-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417105607.4091-1-quic_kathirav@quicinc.com
| | * | clk: qcom: ipq5332: fix the src parameter in ftbl_gcc_apss_axi_clk_srcKathiravan T2023-05-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 480MHz is derived from P_GPLL4_OUT_AUX not from P_GPLL4_OUT_MAIN. Update the freq_tbl with the correct src. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Reported-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417044342.9406-1-quic_kathirav@quicinc.com
| | * | clk: qcom: dispcc-qcm2290: Fix GPLL0_OUT_DIV handlingKonrad Dybcio2023-05-261-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPLL0_OUT_DIV (.fw_name = "gcc_disp_gpll0_div_clk_src") was previously made to reuse the same parent enum entry as GPLL0_OUT_MAIN (.fw_name = "gcc_disp_gpll0_clk_src") in parent_map_2. Resolve it by introducing its own entry in the parent enum and correctly assigning it in disp_cc_parent_map_2[]. Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v2-2-bce7dd512fe4@linaro.org
| | * | clk: qcom: dispcc-qcm2290: Fix BI_TCXO_AO handlingKonrad Dybcio2023-05-261-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BI_TCXO_AO (.fw_name = "bi_tcxo_ao") was previously made to reuse the same parent enum entry as BI_TCXO (.fw_name = "bi_tcxo") in parent_map_2. Resolve it by introducing its own entry in the parent enum and correctly assigning it in disp_cc_parent_map_2[]. Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v2-1-bce7dd512fe4@linaro.org
| | * | clk: qcom: ipq6018: fix networking resetsRobert Marko2023-05-261-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Networking resets in IPQ6018 all use bitmask as they require multiple bits to be set and cleared instead of a single bit. So, current networking resets have the same register and bit 0 set which is clearly incorrect. Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526190855.2941291-2-robimarko@gmail.com
| | * | clk: qcom: gcc-ipq6018: update UBI32 PLLRobert Marko2023-05-261-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the UBI32 alpha PLL config to the latest values from the downstream QCA 5.4 kernel. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526190855.2941291-1-robimarko@gmail.com
| | * | clk: qcom: apss-ipq-pll: Add support for IPQ9574Devi Priya2023-05-261-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the compatible and configuration values for A73 Huayra PLL found on IPQ9574. Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230406061314.10916-3-quic_devipriy@quicinc.com
| | * | clk: qcom: restrict drivers per ARM/ARM64Krzysztof Kozlowski2023-05-241-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point to allow selecting clock controller drivers for Qualcomm ARMv7 SoCs when building ARM64 kernel, and vice versa. This makes kernel configuration more difficult as many do not remember the Qualcomm SoCs model names/numbers. No features should be lost because: 1. There won't be a single image for ARMv7 and ARMv8/9 SoCs. 2. Newer ARMv8/9 SoCs won't be running in arm32 emulation mode. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230514114711.18258-1-krzysztof.kozlowski@linaro.org
| | * | clk: qcom: Add GCC driver support for SDX75Imran Shaik2023-05-243-0/+2979
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Global Clock Controller (GCC) support for SDX75 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230512122347.1219-6-quic_tdas@quicinc.com
| | * | clk: qcom: rpmh: Add RPMH clocks support for SDX75Imran Shaik2023-05-241-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for RPMH clocks for SDX75 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230512122347.1219-5-quic_tdas@quicinc.com
| | * | clk: qcom: branch: Extend the invert logic for branch2 clocksImran Shaik2023-05-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to handle the invert logic for branch2 clocks. Invert branch halt would indicate the clock ON when CLK_OFF bit is '1' and OFF when CLK_OFF bit is '0'. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230512122347.1219-2-quic_tdas@quicinc.com
| | * | clk: qcom: smd-rpm: conditionally enable scaling before doing handoverLuca Weiss2023-05-241-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On older platforms like msm8226, msm8974 and msm8916 the driver in the downstream kernel enables scaling first before doing the handover of the clocks. While this normally doesn't seem to cause noticeable problems, on apq8026-asus-sparrow this causes the device to immediately reboot, perhaps due to older rpm firmware that becomes unhappy. On newer platforms the order has swapped and enabling scaling is done after the handover, so let's introduce this behavior only conditionally for msm8226 and msm8974 for now. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230506-rpmcc-scaling-handover-v1-1-374338a8dfd9@z3ntu.xyz
| | * | clk: qcom: gcc-sdm660: drop redundant F defineChristian Marangi2023-05-241-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The same exact F frequency table entry is defined in clk-rcg.h Drop the redundant define to cleanup code. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417174408.23722-2-ansuelsmth@gmail.com
| | * | clk: qcom: gcc-ipq6018: drop redundant F defineChristian Marangi2023-05-241-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The same exact F frequency table entry is defined in clk-rcg.h Drop the redundant define to cleanup code. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417174408.23722-1-ansuelsmth@gmail.com
| | * | clk: qcom: gcc-qcm2290: Mark RCGs shared where applicableKonrad Dybcio2023-05-241-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vast majority of shared RCGs were not marked as such. Fix it. Fixes: 496d1a13d405 ("clk: qcom: Add Global Clock Controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230403174807.345185-1-konrad.dybcio@linaro.org
| | * | clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550Jagadeesh Kona2023-05-243-0/+481
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the video clock controller for video clients to be able to request for videocc clocks on SM8550 platform. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524145203.13153-4-quic_jkona@quicinc.com
| | * | clk: qcom: clk-alpha-pll: Add support to configure PLL_TEST_CTL_U2Jagadeesh Kona2023-05-242-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lucid ole pll reuses lucid evo ops but it has an additional test control register which is required to be programmed, add support to program the same. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524145203.13153-2-quic_jkona@quicinc.com
| | * | clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450Taniya Das2023-05-243-0/+473
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the video clock controller driver for peripheral clock clients to be able to request for video cc clocks. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524140656.7076-3-quic_tdas@quicinc.com
| | * | clk: qcom: Introduce SM8350 VIDEOCCKonrad Dybcio2023-05-243-0/+562
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Video Clock Controller found on the SM8350 SoC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-2-86c714a66a81@linaro.org
| | * | clk: qcom: gcc-ipq6018: Use floor ops for sdcc clocksMantas Pucka2023-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDCC clocks must be rounded down to avoid overclocking the controller. Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Mantas Pucka <mantas@8devices.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1682413909-24927-1-git-send-email-mantas@8devices.com
| | * | clk: qcom: smd-rpm: Make BI_TCXO_AO criticalKonrad Dybcio2023-05-241-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should never let go of the active-only XO vote, as otherwise the RPM may decide that there are no online users and it can be shut down, resulting in a total, uncontrolled system collapse. Guarantee this through adding the CLK_IS_CRITICAL flag. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Matti Lehtimäki <matti.lehtimaki@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501-topic-rpmcc_xo_a-v1-3-93f18e47b607@linaro.org
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-05 06:27:27 +0000