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* Merge tag 'devicetree-fixes-for-5.16-1' of ↵Linus Torvalds2021-11-148-9/+11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree fixes from Rob Herring: - Two fixes due to DT node name changes on Arm, Ltd. boards - Treewide rename of Ingenic CGU headers - Update ST email addresses - Remove Netlogic DT bindings - Dropping few more cases of redundant 'maxItems' in schemas - Convert toshiba,tc358767 bridge binding to schema * tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: dt-bindings: watchdog: sunxi: fix error in schema bindings: media: venus: Drop redundant maxItems for power-domain-names dt-bindings: Remove Netlogic bindings clk: versatile: clk-icst: Ensure clock names are unique of: Support using 'mask' in making device bus id dt-bindings: treewide: Update @st.com email address to @foss.st.com dt-bindings: media: Update maintainers for st,stm32-hwspinlock.yaml dt-bindings: media: Update maintainers for st,stm32-cec.yaml dt-bindings: mfd: timers: Update maintainers for st,stm32-timers dt-bindings: timer: Update maintainers for st,stm32-timer dt-bindings: i2c: imx: hardware do not restrict clock-frequency to only 100 and 400 kHz dt-bindings: display: bridge: Convert toshiba,tc358767.txt to yaml dt-bindings: Rename Ingenic CGU headers to ingenic,*.h
| * clk: versatile: clk-icst: Ensure clock names are uniqueRob Herring2021-11-111-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2d3de197a818 ("ARM: dts: arm: Update ICST clock nodes 'reg' and node names") moved to using generic node names. That results in trying to register multiple clocks with the same name. Fix this by including the unit-address in the clock name. Fixes: 2d3de197a818 ("ARM: dts: arm: Update ICST clock nodes 'reg' and node names") Cc: stable@vger.kernel.org Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20211109164650.2233507-3-robh@kernel.org
| * dt-bindings: Rename Ingenic CGU headers to ingenic,*.hPaul Cercueil2021-11-117-7/+7
| | | | | | | | | | | | | | | | | | | | | | Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files related to Ingenic SoCs with 'ingenic,'. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211016133322.40771-1-paul@crapouillou.net
* | Merge tag 'clk-for-linus' of ↵Linus Torvalds2021-11-1316-47/+94
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull more clk updates from Stephen Boyd: "This is the second batch of clk driver updates that needed a little more time to soak in linux-next. - Use modern i2c probe in vc5 - Cleanup some includes - Update links to datasheets - Add UniPhier NX1 SoC clk support - Fix DT bindings for SiFive FU740 - Revert the module platform driver support for Rockchip because it wasn't actually tested - Fix the composite clk code again as the previous fix had a one line bug that broke rate changes for clks that want to use the same parent still - Use the right table for a divider in ast2600 driver - Get rid of gcc_aggre1_pnoc_ahb_clk in qcom clk driver again because its critical but unused" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clk clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular composites clk/ast2600: Fix soc revision for AHB clk: composite: Fix 'switching' to same clock clk: rockchip: drop module parts from rk3399 and rk3568 drivers Revert "clk: rockchip: use module_platform_driver_probe" clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.c dt-bindings: clock: fu740-prci: add reset-cells clk: uniphier: Add SoC-glue clock source selector support for Pro4 dt-bindings: clock: uniphier: Add clock binding for SoC-glue clk: uniphier: Add NX1 clock support dt-bindings: clock: uniphier: Add NX1 clock binding clk: uniphier: Add audio system and video input clock control for PXs3 clk: si5351: Update datasheet references clk: vc5: Use i2c .probe_new clk/actions/owl-factor.c: remove superfluous headers clk: ingenic: Fix bugs with divided dividers
| * clk: qcom: gcc-msm8996: Drop (again) gcc_aggre1_pnoc_ahb_clkDmitry Baryshkov2021-11-051-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gcc_aggre1_pnoc_ahb_clk is crucial for the proper MSM8996/APQ8096 functioning. If it gets disabled, several subsytems will stop working (including eMMC/SDCC and USB). There are no in-kernel users of this clock, so it is much simpler to remove from the kernel. The clock was first removed in the commit 9e60de1cf270 ("clk: qcom: Remove gcc_aggre1_pnoc_ahb_clk from msm8996") by Stephen Boyd, but got added back in the commit b567752144e3 ("clk: qcom: Add some missing gcc clks for msm8996") by Rajendra Nayak. Let's remove it again in hope that nobody adds it back. Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Fixes: b567752144e3 ("clk: qcom: Add some missing gcc clks for msm8996") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20211104011155.2209654-1-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: imx8m: Do not set IMX_COMPOSITE_CORE for non-regular compositesAlexander Stein2021-11-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | Only imx8m_clk_hw_composite_core needs to set this flag. Fixes: a60fe746df94 ("clk: imx: Rework all imx_clk_hw_composite wrappers") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103123947.3222443-1-alexander.stein@ew.tq-group.com Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk/ast2600: Fix soc revision for AHBJoel Stanley2021-11-031-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the soc revision parsing to the initial probe, saving the driver from parsing the register multiple times. Use this variable to select the correct divisor table for the AHB clock. Before this fix the A2 would have used the A0 table. Fixes: 2d491066ccd4 ("clk: ast2600: Fix AHB clock divider for A1") Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210922235449.213631-1-joel@jms.id.au Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: composite: Fix 'switching' to same clockAlexander Stein2021-11-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During commit 6594988fd625 ("clk: composite: Use rate_ops.determine_rate when also a mux is available") setting req->best_parent_hw got lost, so best_parent_hw stays NULL during switch to the same parent. This results in the (debug) message: clk_calc_new_rates: lcdif_pixel not gated but wants to reparent and the following rate change is dropped. Fixes: 6594988fd625 ("clk: composite: Use rate_ops.determine_rate when also a mux is available") Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20211103122441.3208576-1-alexander.stein@ew.tq-group.com Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: rockchip: drop module parts from rk3399 and rk3568 driversHeiko Stuebner2021-11-023-10/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Both of these drivers were converted to real drivers and got a tristate build option. But them being builtin_platform_drivers, they only ever should be build-in - as the name suggests. So adapt the Kconfig symbol and drop the MODULE_* parts from the drivers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211027132616.1039814-3-heiko@sntech.de Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * Revert "clk: rockchip: use module_platform_driver_probe"Heiko Stuebner2021-11-022-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1da80da028fe5accb866c0d6899a292ed86bef45. Reading recent discussions [0] [1], I realized this change introduces a number of problems: - only converting to module_platform_driver creates the issue with the existing __init and __initdata attributes. When the driver would've been built as a module, all the missing clock-definitions (all are initdata) should've turned up as error in testing suggesting that the change wasn't at all - a clock driver is a very core component of soc bringup and making this able to be built as a module solely for enabling the soc vendor to add out of tree changes for Android implementations is not in our interest and also everything except a ramdisk won't probe without a clock controller. This is especially true when the changes aren't really tested and are merely added to move the mainline driver "out of the way". [0] https://lwn.net/Articles/872209/ [1] https://lore.kernel.org/all/163529604399.15791.378104318036812951@swboyd.mtv.corp.google.com/ Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211027132616.1039814-2-heiko@sntech.de Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk:mediatek: remove duplicate include in clk-mt8195-imp_iic_wrap.cRan Jianping2021-11-021-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | 'dt-bindings/clock/mt8195-clk.h' included in '/drivers/clk/mediatek/clk-mt8195-imp_iic_wrap.c' is duplicated.It is also included on the 13 line. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Ran Jianping <ran.jianping@zte.com.cn> Link: https://lore.kernel.org/r/20211019062939.979660-1-ran.jianping@zte.com.cn Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: uniphier: Add SoC-glue clock source selector support for Pro4Kunihiko Hayashi2021-11-023-0/+23
| | | | | | | | | | | | | | | | | | Add SoC-glue clock source selector for ahci controller on UniPhier SoCs. Currently this supports Pro4 only. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1634000035-3114-6-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: uniphier: Add NX1 clock supportKunihiko Hayashi2021-11-023-0/+45
| | | | | | | | | | | | | | | | | | | | Add basic clock data for UniPhier NX1 SoC. This includes PLL and clock division data for cpufreq support. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1634000035-3114-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: uniphier: Add audio system and video input clock control for PXs3Kunihiko Hayashi2021-11-021-0/+2
| | | | | | | | | | | | | | | | | | Add clocks for audio subsystem (AIO) and video input subsystem (EXIV) on UniPhier PXs3 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1634000035-3114-2-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: si5351: Update datasheet referencesJens Renner2021-11-022-5/+5
| | | | | | | | | | | | | | | | | | | | Silicon Labs is now part of Skyworks Inc. so update the URLs to the datasheet and application note. Signed-off-by: Jens Renner <renner@efe-gmbh.de> Link: https://lore.kernel.org/r/20210913074823.115212-1-renner@efe-gmbh.de Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: vc5: Use i2c .probe_newLuca Ceresoli2021-11-021-2/+2
| | | | | | | | | | | | | | | | The old .probe is "soon to be deprecated". Use the new, simpler form. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Link: https://lore.kernel.org/r/20210928095041.17116-1-luca@lucaceresoli.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk/actions/owl-factor.c: remove superfluous headersMianhan Liu2021-11-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | owl-factor.c hasn't use any macro or function declared in linux/slab.h. Thus, these files can be removed from owl-factor.c safely without affecting the compilation of the ./drivers/clk module Signed-off-by: Mianhan Liu <liumh1@shanghaitech.edu.cn> Link: https://lore.kernel.org/r/20210929065824.23691-1-liumh1@shanghaitech.edu.cn Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: ingenic: Fix bugs with divided dividersPaul Cercueil2021-11-021-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two fixes in one: - In the "impose hardware constraints" block, the "logical" divider value (aka. not translated to the hardware) was clamped to fit in the register area, but this totally ignored the fact that the divider value can itself have a fixed divider. - The code that made sure that the divider value returned by the function was a multiple of its own fixed divider could result in a wrong value being calculated, because it was rounded down instead of rounded up. Fixes: 4afe2d1a6ed5 ("clk: ingenic: Allow divider value to be divided") Co-developed-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20211001172033.122329-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | Merge tag 'mfd-next-5.16' of ↵Linus Torvalds2021-11-081-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "Removed Drivers: - Remove support for TI TPS80031/TPS80032 PMICs New Device Support: - Add support for Magnetic Reader to TI AM335x - Add support for DA9063_EA to Dialog DA9063 - Add support for SC2730 PMIC to Spreadtrum SC27xx - Add support for MacBookPro16,2 ICL-N UART Intel LPSS PCI - Add support for lots of new PMICS in QCom SPMI PMIC - Add support for ADC to Diolan DLN2 New Functionality: - Add support for Power Off to Rockchip RK817 Fix-ups: - Simplify Regmap passing to child devices in hi6421-spmi-pmic - SPDX licensing updates in ti_am335x_tscadc - Improve error handling in ti_am335x_tscadc - Expedite clock search in ti_am335x_tscadc - Generic simplifications in ti_am335x_tscadc - Use generic macros/defines in ti_am335x_tscadc - Remove unused code in ti_am335x_tscadc, cros_ec_dev - Convert to GPIOD in wcd934x - Add namespacing in ti_am335x_tscadc - Restrict compilation to relevant arches in intel_pmt - Provide better description/documentation in exynos_lpass - Add SPI device ID table in altera-a10sr, motorola-cpcap, sprd-sc27xx-spi - Change IRQ handling in qcom-pm8xxx - Split out I2C and SPI code in arizona - Explicitly include used headers in altera-a10sr - Convert sysfs show() function to in sysfs_emit - Standardise *_exit() and *_remove() return values in mc13xxx, stmpe, tps65912 - Trivial (style/spelling/whitespace) fixups in ti_am335x_tscadc, qcom-spmi-pmic, max77686-private - Device Tree fix-ups in ti,am3359-tscadc, samsung,s2mps11, samsung,s2mpa01, samsung,s5m8767, brcm,misc, brcm,cru, syscon, qcom,tcsr, xylon,logicvc, max77686, x-powers,ac100, x-powers,axp152, x-powers,axp209-gpio, syscon, qcom,spmi-pmic Bug Fixes: - Balance refcounting (get/put) in ti_am335x_tscadc, mfd-core - Fix IRQ trigger type in sec-irq, max77693, max14577 - Repair off-by-one in altera-sysmgr - Add explicit 'select MFD_CORE' to MFD_SIMPLE_MFD_I2C" * tag 'mfd-next-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (95 commits) mfd: simple-mfd-i2c: Select MFD_CORE to fix build error mfd: tps80031: Remove driver mfd: max77686: Correct tab-based alignment of register addresses mfd: wcd934x: Replace legacy gpio interface for gpiod dt-bindings: mfd: qcom: pm8xxx: Add pm8018 compatible mfd: dln2: Add cell for initializing DLN2 ADC mfd: qcom-spmi-pmic: Add missing PMICs supported by socinfo mfd: qcom-spmi-pmic: Document ten more PMICs in the binding mfd: qcom-spmi-pmic: Sort compatibles in the driver mfd: qcom-spmi-pmic: Sort the compatibles in the binding mfd: janz-cmoio: Replace snprintf in show functions with sysfs_emit mfd: altera-a10sr: Include linux/module.h mfd: tps65912: Make tps65912_device_exit() return void mfd: stmpe: Make stmpe_remove() return void mfd: mc13xxx: Make mc13xxx_common_exit() return void dt-bindings: mfd: syscon: Add samsung,exynosautov9-sysreg compatible mfd: altera-sysmgr: Fix a mistake caused by resource_size conversion dt-bindings: gpio: Convert X-Powers AXP209 GPIO binding to a schema dt-bindings: mfd: syscon: Add rk3368 QoS register compatible mfd: arizona: Split of_match table into I2C and SPI versions ...
| * | clk: ti: am43xx: Add clkctrl data for am43xx ADC1Miquel Raynal2021-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Declare ADC1 clkctrl which feeds the magnetic-reader/ADC1 hardware module. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211015081506.933180-2-miquel.raynal@bootlin.com
* | | Merge tag 'clk-for-linus' of ↵Linus Torvalds2021-11-03161-2350/+14591
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of clk driver updates and new driver additions. In terms of lines it's mainly Qualcomm and Mediatek code, supporting various SoCs and their multitude of clk controllers. New Drivers: - GCC and RPMcc support for Qualcomm QCM2290 SoCs - GCC support for Qualcomm MSM8994/MSM8992 SoCs - LPASSCC and CAMCC support for Qualcomm SC7280 SoCs - Support for Mediatek MT8195 SoCs - Initial clock driver for the Exynos850 SoC - Add i.MX8ULP clock driver and related bindings Updates: - Clock power management for new SAMA7G5 SoC - Updates to the master clock driver and sam9x60-pll to be able to use cpufreq-dt driver and avoid overclocking of CPU and MCK0 domains while changing the frequency via DVFS - Use ARRAY_SIZE in qcom clk drivers - Remove some impractical fallback parent names in qcom clk drivers - Make Mediatek clk drivers tristate - Refactoring of the CPU clock code and conversion of Samsung Exynos5433 CPU clock driver to the platform driver - A few conversions to devm_platform_ioremap_resource() - Updates of the Samsung Kconfig help text - Update video path realted clocks for Amlogic meson8 - Add SPI Multi I/O Bus and SDHI clocks and resets on Renesas RZ/G2L - Add SPI Multi I/O Bus (RPC) clocks on Renesas R-Car V3U - Add MediaLB clocks on Renesas R-Car H3, M3-W/W+, and M3-N - Remove unused helpers from i.MX specific clock header - Rework all i.MX clk based helpers to use clk_hw based ones - Rework i.MX gate/mux/divider wrappers - Rework imx_clk_hw_composite and imx_clk_hw_pll14xx wrappers - Update i.MX pllv4 and composite clocks to support i.MX8ULP - Disable i.MX7ULP composite clock during initialization - Add CLK_SET_RATE_NO_REPARENT flag to the i.MX7ULP composite - Disable the i.MX pfd when set pfdv2 clock rate - Add support for i.MX8ULP in pfdv2 - Add the pcc reset controller support on i.MX8ULP - Fix the build break when clk-imx8ulp is built as module - Move csi_sel mux to correct base register in i.MX6UL clock drivr - Fix csi clk gate register in i.MX6UL clock driver - Fix build bug making CLK_IMX8ULP select MXC_CLK - Add TPU (PWM), and Z (Cortex-A76) clocks on Renesas R-Car V3U - Add Ethernet clocks on Renesas RZ/G2L - Move Rockchip to use module_platform_probe - Enable usage of Coresight related clocks on Rockchip rk3399" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (170 commits) clk: use clk_core_get_rate_recalc() in clk_rate_get() clk: at91: sama7g5: set low limit for mck0 at 32KHz clk: at91: sama7g5: remove prescaler part of master clock clk: at91: clk-master: add notifier for divider clk: at91: clk-sam9x60-pll: add notifier for div part of PLL clk: at91: clk-master: fix prescaler logic clk: at91: clk-master: mask mckr against layout->mask clk: at91: clk-master: check if div or pres is zero clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL clk: at91: pmc: add sama7g5 to the list of available pmcs clk: at91: clk-master: improve readability by using local variables clk: at91: clk-master: add register definition for sama7g5's master clock clk: at91: sama7g5: add securam's peripheral clock clk: at91: pmc: execute suspend/resume only for backup mode clk: at91: re-factor clocks suspend/resume clk: ux500: Add driver for the reset portions of PRCC dt-bindings: clock: u8500: Rewrite in YAML and extend clk: composite: Use rate_ops.determine_rate when also a mux is available clk: samsung: describe drivers in Kconfig clk: samsung: exynos5433: update apollo and atlas clock probing ...
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| *-----. \ Merge branches 'clk-composite-determine-fix', 'clk-allwinner', 'clk-amlogic' ↵Stephen Boyd2021-11-0245-258/+1463
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and 'clk-samsung' into clk-next * clk-composite-determine-fix: clk: composite: Use rate_ops.determine_rate when also a mux is available clk: composite: Also consider .determine_rate for rate + mux composites * clk-allwinner: clk: sunxi: sun8i-apb0: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi: sun6i-ar100: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi: sun6i-apb0-gates: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi: sun6i-apb0: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun9i-a80-usb: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun9i-a80-de: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun9i-a80: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun8i-r40: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun8i-de2: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun8i-a83t: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun50i-h6: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi-ng: ccu-sun50i-a64: Make use of the helper function devm_platform_ioremap_resource() clk: sunxi: clk-mod0: Make use of the helper function devm_platform_ioremap_resource() dt-bindings: clocks: Fix typo in the H6 compatible clk: sunxi-ng: Use a separate lock for each CCU instance clk: sunxi-ng: Prevent unbinding CCUs via sysfs clk: sunxi-ng: Unregister clocks/resets when unbinding clk: sunxi-ng: Add machine dependency to A83T CCU clk: sunxi-ng: mux: Remove unused 'reg' field * clk-amlogic: clk: meson: meson8b: Make the video clock trees mutable clk: meson: meson8b: Initialize the HDMI PLL registers clk: meson: meson8b: Add the HDMI PLL M/N parameters clk: meson: meson8b: Add the vid_pll_lvds_en gate clock clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_sel clk: meson: meson8b: Export the video clocks * clk-samsung: clk: samsung: describe drivers in Kconfig clk: samsung: exynos5433: update apollo and atlas clock probing clk: samsung: add support for CPU clocks clk: samsung: Introduce Exynos850 clock driver dt-bindings: clock: Document Exynos850 CMU bindings dt-bindings: clock: Add bindings definitions for Exynos850 CMU clk: samsung: clk-pll: Implement pll0831x PLL type clk: samsung: clk-pll: Implement pll0822x PLL type clk: samsung: s5pv210-audss: Make use of devm_platform_ioremap_resource() clk: samsung: exynos5433: Make use of devm_platform_ioremap_resource() clk: samsung: exynos4412-isp: Make use of devm_platform_ioremap_resource() clk: samsung: exynos-audss: Make use of devm_platform_ioremap_resource()
| | | | | * | clk: samsung: describe drivers in KconfigKrzysztof Kozlowski2021-10-181-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Describe better which driver applies to which SoC, to make configuring kernel for Samsung SoC easier. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20210924133624.112593-1-krzysztof.kozlowski@canonical.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | | | | * | clk: samsung: exynos5433: update apollo and atlas clock probingWill McVicker2021-10-151-72/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the samsung common clk driver to initialize the apollo and atlas clocks. This removes their custom init functions and uses the samsung_cmu_register_one() instead. Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211014195347.3635601-3-willmcvicker@google.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | | | | * | clk: samsung: add support for CPU clocksWill McVicker2021-10-153-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds 'struct samsung_cpu_clock' and corresponding CPU clock registration function to the samsung common clk driver. This allows samsung clock drivers to register their CPU clocks with the samsung_cmu_register_one() API. Currently the exynos5433 apollo and atlas clks have their own custom init functions to handle registering their CPU clocks. With this patch we can drop their custom CLK_OF_DECLARE functions and directly call samsung_cmu_register_one(). Signed-off-by: Will McVicker <willmcvicker@google.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211014195347.3635601-2-willmcvicker@google.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | | | | * | clk: samsung: Introduce Exynos850 clock driverSam Protsenko2021-10-152-0/+836
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the initial implementation adding only basic clocks like UART, MMC, I2C and corresponding parent clocks. Design is influenced by Exynos5433 clock driver. Bus clock is enabled by default (in probe function) for all CMUs except CMU_TOP, the reasoning is as follows. By default if bus clock has no users its "enable count" value is 0. It might be actually running if it's already enabled in bootloader, but then in some cases it can be disabled by mistake. For example, such case was observed when dw_mci_probe() enabled the bus clock, then failed to do something and disabled that bus clock on error path. After that, even the attempt to read the 'clk_summary' file in DebugFS freezed forever, as CMU bus clock ended up being disabled and it wasn't possible to access CMU registers anymore. To avoid such cases, CMU driver must increment the ref count for that bus clock by running clk_prepare_enable(). There is already existing '.clk_name' field in struct samsung_cmu_info, exactly for that reason. It was added in commit 523d3de41f02 ("clk: samsung: exynos5433: Add support for runtime PM"), with next mentioning in commit message: > Also for each CMU there is one special parent clock, which has to be > enabled all the time when any access to CMU registers is being done. But that clock is actually only enabled in Exynos5433 clock driver right now. So the same code is added to exynos850_cmu_probe() function, As was described above, it might be helpful not only for PM reasons, but also to prevent possible erroneous clock gating on error paths. Another way to workaround that issue would be to use CLOCK_IS_CRITICAL flag for corresponding gate clocks. But that might be not very good design decision, as we might still want to disable that bus clock, e.g. on PM suspend. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211008154352.19519-6-semen.protsenko@linaro.org Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | | | | * | clk: samsung: clk-pll: Implement pll0831x PLL typeSam Protsenko2021-10-092-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pll0831x PLL is used in Exynos850 SoC for top-level fractional PLLs. The code was derived from very similar pll36xx type, with next differences: 1. Lock time for pll0831x is 500*P_DIV, when for pll36xx it's 3000*P_DIV 2. It's not suggested in Exynos850 TRM that S_DIV change doesn't require performing PLL lock procedure (which is done in pll36xx implementation) 3. The offset from PMS-values register to K-value register is 0x8 for pll0831x, when for pll36xx it's 0x4 When defining pll0831x type, CON3 register offset should be provided as a "con" parameter of PLL() macro, like this: PLL(pll_0831x, 0, "fout_mmc_pll", "oscclk", PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, pll0831x_26mhz_tbl), To define PLL rates table, one can use PLL_36XX_RATE() macro, e.g.: PLL_36XX_RATE(26 * MHZ, 799999877, 31, 1, 0, -15124) as it's completely appropriate for pl0831x type and there is no sense in duplicating that. If bit #1 (MANUAL_PLL_CTRL) is not set in CON1 register, it won't be possible to set new rate, with next error showing in kernel log: Could not lock PLL fout_mmc_pll That can happen for example if bootloader clears that bit beforehand. PLL driver doesn't account for that, so if MANUAL_PLL_CTRL bit was cleared, it's assumed it was done for a reason and it shouldn't be possible to change that PLL's rate at all. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211008154352.19519-3-semen.protsenko@linaro.org Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | | | | * | clk: samsung: clk-pll: Implement pll0822x PLL typeSam Protsenko2021-10-092-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pll0822x PLL is used in Exynos850 SoC for top-level integer PLLs. The code was derived from very similar pll35xx type, with next differences: 1. Lock time for pll0822x is 150*P_DIV, when for pll35xx it's 270*P_DIV 2. It's not suggested in Exynos850 TRM that S_DIV change doesn't require performing PLL lock procedure (which is done in pll35xx implementation) When defining pll0822x type, CON3 register offset should be provided as a "con" parameter of PLL() macro, like this: PLL(pll_0822x, 0, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, exynos850_shared0_pll_rates), To define PLL rates table, one can use PLL_35XX_RATE() macro, e.g.: PLL_35XX_RATE(26 * MHZ, 1600 * MHZ, 800, 13, 0) as it's completely appropriate for pl0822x type and there is no sense in duplicating that. If bit #1 (MANUAL_PLL_CTRL) is not set in CON1 register, it won't be possible to set new rate, with next error showing in kernel log: Could not lock PLL fout_shared1_pll That can happen for example if bootloader clears that bit beforehand. PLL driver doesn't account for that, so if MANUAL_PLL_CTRL bit was cleared, it's assumed it was done for a reason and it shouldn't be possible to change that PLL's rate at all. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20211008154352.19519-2-semen.protsenko@linaro.org Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | | | | * | clk: samsung: s5pv210-audss: Make use of devm_platform_ioremap_resource()Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210907085122.4305-1-caihuoqing@baidu.com
| | | | | * | clk: samsung: exynos5433: Make use of devm_platform_ioremap_resource()Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210907085115.4254-1-caihuoqing@baidu.com
| | | | | * | clk: samsung: exynos4412-isp: Make use of devm_platform_ioremap_resource()Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210907085107.4203-1-caihuoqing@baidu.com
| | | | | * | clk: samsung: exynos-audss: Make use of devm_platform_ioremap_resource()Cai Huoqing2021-09-131-3/+1
| | | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210907085100.4152-1-caihuoqing@baidu.com
| | | | * | clk: meson: meson8b: Make the video clock trees mutableMartin Blumenstingl2021-09-231-38/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch from the "_ro" clock op variants to the mutable ones for all video clocks. This will allow the VPU driver to change the clocks as needed for the different video output modes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210713232510.3057750-6-martin.blumenstingl@googlemail.com
| | | | * | clk: meson: meson8b: Initialize the HDMI PLL registersMartin Blumenstingl2021-09-232-5/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the reg_sequence to initialize the HDMI PLL with the settings for a video mode that doesn't require PLL internal clock doubling. These settings are taken from the 3.10 vendor kernel's driver for the 2970MHz PLL setting used for the 1080P video mode. This puts the PLL into a defined state and the Linux kernel can take over. While not all bits for this PLL are implemented using these "defaults" and then applying M, N and FRAC seems to work fine. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210713232510.3057750-5-martin.blumenstingl@googlemail.com
| | | | * | clk: meson: meson8b: Add the HDMI PLL M/N parametersMartin Blumenstingl2021-09-231-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 3.10 vendor kernel uses only specific HDMI PLL M/N parameter combinations. The PLL won't lock for values smaller than 50 if the internal doubling (which is yet unknown how to use it) is disabled. However, when this doubling is enabled then the values smaller than 50 will lock just fine. The only restriction for values greater than 50 is that the resulting frequency must not exceed the 3.0GHz limit. These values are taken from the endlessm 3.10 kernel which includes additional M/N combinations for some VESA and 75Hz display modes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210713232510.3057750-4-martin.blumenstingl@googlemail.com
| | | | * | clk: meson: meson8b: Add the vid_pll_lvds_en gate clockMartin Blumenstingl2021-09-232-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HHI_VID_DIVIDER_CNTL[11] must be enabled for the video clock tree to work. This bit is described as "LVDS_CLK_EN". It is not 100% clear where this bit has to be placed in the hierarchy. But since the "LVDS_OUT" of the HDMI PLL uses it's own set of registers it's more likely that this "LVDS_CLK_EN" bit actually enables the input of the "hdmi_pll_lvds_out" clock to the "vid_pll_in_sel" tree. Add a gate definition for this bit (which will not be exported) so that the kernel can manage all required bits to enable and disable the video clocks. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210713232510.3057750-3-martin.blumenstingl@googlemail.com
| | | | * | clk: meson: meson8b: Use CLK_SET_RATE_NO_REPARENT for vclk{,2}_in_selMartin Blumenstingl2021-09-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use CLK_SET_RATE_NO_REPARENT for the vclk{,2}_in_sel clocks. The only parent which is actually used is vid_pll_final_div. This should be set using assigned-clock-parents in the .dts rather than removing some "unwanted" clock parents from the clock driver. Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210713232510.3057750-2-martin.blumenstingl@googlemail.com
| | | | * | clk: meson: meson8b: Export the video clocksMartin Blumenstingl2021-09-231-11/+1
| | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting the video clocks requires fine-tuned adjustments of various video clocks. Export the required ones to allow changing the video clock for the CVBS and HDMI outputs at runtime. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210713232510.3057750-7-martin.blumenstingl@googlemail.com
| | | * | clk: sunxi: sun8i-apb0: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085319.5121-1-caihuoqing@baidu.com
| | | * | clk: sunxi: sun6i-ar100: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085312.5070-1-caihuoqing@baidu.com
| | | * | clk: sunxi: sun6i-apb0-gates: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085305.5019-1-caihuoqing@baidu.com
| | | * | clk: sunxi: sun6i-apb0: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085257.4968-1-caihuoqing@baidu.com
| | | * | clk: sunxi-ng: ccu-sun9i-a80-usb: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085250.4917-1-caihuoqing@baidu.com
| | | * | clk: sunxi-ng: ccu-sun9i-a80-de: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085243.4866-1-caihuoqing@baidu.com
| | | * | clk: sunxi-ng: ccu-sun9i-a80: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085235.4815-1-caihuoqing@baidu.com
| | | * | clk: sunxi-ng: ccu-sun8i-r40: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085228.4764-1-caihuoqing@baidu.com
| | | * | clk: sunxi-ng: ccu-sun8i-de2: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085221.4713-1-caihuoqing@baidu.com
| | | * | clk: sunxi-ng: ccu-sun8i-a83t: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085213.4662-1-caihuoqing@baidu.com
| | | * | clk: sunxi-ng: ccu-sun50i-h6: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085206.4611-1-caihuoqing@baidu.com
| | | * | clk: sunxi-ng: ccu-sun50i-a64: Make use of the helper function ↵Cai Huoqing2021-09-131-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210907085158.4560-1-caihuoqing@baidu.com
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